KR20040010932A - Method for forming the capacitor of Metal-Insulator-Metal structure - Google Patents
Method for forming the capacitor of Metal-Insulator-Metal structure Download PDFInfo
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- KR20040010932A KR20040010932A KR1020020043975A KR20020043975A KR20040010932A KR 20040010932 A KR20040010932 A KR 20040010932A KR 1020020043975 A KR1020020043975 A KR 1020020043975A KR 20020043975 A KR20020043975 A KR 20020043975A KR 20040010932 A KR20040010932 A KR 20040010932A
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- 239000002184 metal Substances 0.000 title claims abstract description 105
- 239000003990 capacitor Substances 0.000 title claims abstract description 54
- 238000000034 method Methods 0.000 title claims abstract description 32
- 239000010410 layer Substances 0.000 claims abstract description 54
- 239000011229 interlayer Substances 0.000 claims abstract description 31
- 239000004065 semiconductor Substances 0.000 claims abstract description 20
- 238000005530 etching Methods 0.000 claims abstract description 19
- 238000004519 manufacturing process Methods 0.000 claims abstract description 17
- 238000000151 deposition Methods 0.000 claims abstract description 15
- 239000000126 substance Substances 0.000 claims abstract description 11
- 239000000758 substrate Substances 0.000 claims abstract description 10
- 230000009977 dual effect Effects 0.000 claims description 16
- 238000007517 polishing process Methods 0.000 claims description 11
- 238000009792 diffusion process Methods 0.000 claims description 9
- 230000004888 barrier function Effects 0.000 claims description 8
- 230000015572 biosynthetic process Effects 0.000 claims description 7
- 239000004020 conductor Substances 0.000 claims description 4
- 230000008021 deposition Effects 0.000 claims description 3
- 150000004767 nitrides Chemical class 0.000 claims description 3
- HBMJWWWQQXIZIP-UHFFFAOYSA-N silicon carbide Chemical compound [Si+]#[C-] HBMJWWWQQXIZIP-UHFFFAOYSA-N 0.000 claims description 3
- 229910010271 silicon carbide Inorganic materials 0.000 claims description 3
- 239000000463 material Substances 0.000 claims description 2
- 239000002887 superconductor Substances 0.000 claims 1
- 239000012212 insulator Substances 0.000 abstract 1
- 238000005498 polishing Methods 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 description 8
- 230000000873 masking effect Effects 0.000 description 2
- 238000001465 metallisation Methods 0.000 description 2
- 229910052581 Si3N4 Inorganic materials 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000008878 coupling Effects 0.000 description 1
- 238000010168 coupling process Methods 0.000 description 1
- 238000005859 coupling reaction Methods 0.000 description 1
- 230000018109 developmental process Effects 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/60—Electrodes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
- H01L21/76813—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures involving a partial via etch
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
- H01L28/40—Capacitors
- H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
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- Power Engineering (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
본 발명은 반도체소자의 배선과 상호 연결되는 MIM 구조의 커패시터 제조방법에 관한 것으로서, 보다 상세하게는 MIM 구조의 커패시터 패턴 형성을 위한 포토공정을 생략하여 그에 따른 반도체 소자의 제조 공정을 단순화하게 하는 MIM 구조의 커패시터 제조방법에 관한 것이다.The present invention relates to a method of manufacturing a capacitor of the MIM structure interconnected with the wiring of the semiconductor device, and more particularly, MIM to simplify the manufacturing process of the semiconductor device by omitting the photo process for forming the capacitor pattern of the MIM structure It relates to a capacitor manufacturing method of the structure.
MIM 구조의 커패시터는 다른 반도체소자와 동시에 구현되어야 하므로 상호 연결배선(interconnection line)인 금속배선을 통해서 반도체소자와 전기적으로 연결되어 있다.Since the capacitor of the MIM structure must be implemented at the same time as other semiconductor devices, the capacitor is electrically connected to the semiconductor device through a metal wiring, which is an interconnection line.
상기의 MIM 구조의 커패시터를 혼합 신호(Mixed Signal) 및 RF(Radio Frequency) IC으로 적용되기 위해서는 단위 정전 용량(Unit capacitance)의 요구 사양이 용도에 따라 다르다. 예를 들어, 아날로그(Analog) 및 RF 커플링 커패시터(Coupling capacitor)의 정전 용량은 1 내지 3 fF/㎟이고, 필터 커패시터(Filter capacitor)의 정전 용량은 2 내지 5 fF/㎟이며, RF 바이패스 커패시터(Bypass Capacitor)는 정전 용량은 5 내지 10 fF/㎟이다. 따라서 단일칩(System-on-a-chip)으로의 적용이 가능하기 위해서는 상기의 조건(Spec)을 만족하는 커패시터들을 통합(Integration)하여야 하며, 동일 레이어(Layer)에서 형성시켜야 비용(Cost) 측면에서 강점을 가질 수 있다.In order to apply the capacitor of the MIM structure as a mixed signal and a RF (Radio Frequency) IC, the requirements of unit capacitance vary depending on the application. For example, the capacitance of analog and RF coupling capacitors is 1 to 3 fF / mm 2, the capacitance of the filter capacitor is 2 to 5 fF / mm 2, and the RF bypass The capacitor has a capacitance of 5 to 10 fF / mm 2. Therefore, in order to be applicable as a system-on-a-chip, capacitors satisfying the above specifications must be integrated and formed in the same layer. Can have strengths.
도 1a 내지 도 1c는 종래 MIM 구조의 커패시터 제조방법을 설명하기 위해 순차적으로 나타낸 단면도이다.1A to 1C are cross-sectional views sequentially illustrating a method of manufacturing a capacitor having a conventional MIM structure.
먼저, 도 1a에 도시된 바와 같이, 제1금속배선(2)이 형성된 반도체기판(1) 상에 제1층간절연막(5)을 증착한 후, 듀얼 다마신 공정을 진행하여 플러그 형성 패턴과 제2금속배선 패턴을 동시에 제1층간절연막(5) 내에 형성한다. 그리고, 플러그 형성 패턴(미도시함)과 제2금속배선 패턴(미도시함)이 형성된 결과물 전체에 제1금속막(예컨대, Cu)을 증착한 후, 제1층간절연막(5) 상부까지 제1금속막을 화학기계적 연마하여 평탄화함으로써 제1금속배선과 제2금속배선을 연결할 플러그(3) 및 제2금속배선(4)을 형성한다.First, as shown in FIG. 1A, the first interlayer insulating film 5 is deposited on the semiconductor substrate 1 on which the first metal wiring 2 is formed, and then a dual damascene process is performed to form a plug forming pattern and a second insulating film. A two metal wiring pattern is simultaneously formed in the first interlayer insulating film 5. After depositing the first metal layer (eg, Cu) on the entire product on which the plug formation pattern (not shown) and the second metal wiring pattern (not shown) are formed, the first interlayer insulating film 5 is formed. The first metal film is chemically polished and planarized to form a plug 3 and a second metal wire 4 connecting the first metal wire and the second metal wire.
이어서, 도 1b에 도시된 바와 같이, 상기 결과물 상에 실리콘나이트라이드로 이루어진 유전막(6)과 제2금속막(7)(예컨대, Cu)을 증착하고, 제2금속막 상부에 감광막(미도시함)을 도포하여 커패시터 영역이 형성되도록 노광 및 현상공정을 진행하여 제1감광막 패턴(미도시함)을 형성한 후, 이를 식각마스크로 제2금속막(7)과 유전막(6)을 식각하여 MIM 구조의 커패시터 패턴을 형성한다.Subsequently, as illustrated in FIG. 1B, a dielectric film 6 made of silicon nitride and a second metal film 7 (eg, Cu) are deposited on the resultant, and a photoresist film (not shown) is formed on the second metal film. Exposure and development processes to form a capacitor region by forming a first photoresist layer pattern (not shown), and then etching the second metal layer 7 and the dielectric layer 6 using an etching mask. The capacitor pattern of the MIM structure is formed.
이때, 상기 제2금속막(7)은 MIM 구조의 상부전극으로 사용된다.In this case, the second metal film 7 is used as an upper electrode of the MIM structure.
이어서, 도 1c에 도시된 바와 같이, 제1감광막 패턴(미도시함)을 제거한 후, 제2층간절연막(8)을 증착한다.Subsequently, as shown in FIG. 1C, after the first photosensitive film pattern (not shown) is removed, the second interlayer insulating film 8 is deposited.
그리고, 상기 제2층간절연막(8)을 증착한 후, 제2층간절연막(8) 내에 하부 제2금속배선(4)과 MIM 구조의 커패시터의 상부전극(7)이 상부 다른 배선과 전기적으로 연결되도록 듀얼다마신 공정에 의해 플러그(9)를 형성한다.After the deposition of the second interlayer insulating film 8, the lower second metal wiring 4 and the upper electrode 7 of the capacitor of the MIM structure are electrically connected to the other upper wiring in the second interlayer insulating film 8. The plug 9 is formed by a dual damascene process as much as possible.
그 후, 결과물 상에 제3금속막(미도시함)을 증착한 후, 식각하여 제3금속배선(10)을 형성한다.Thereafter, a third metal film (not shown) is deposited on the resultant, and then etched to form a third metal wiring 10.
그러나, 상기와 같은 종래 기술의 MIM 구조의 커패시터 제조방법을 이용하게 되면, 제1금속막을 식각하여 상기 반도체기판 상에 제2금속배선과 MIM 구조의 커패시터 패턴의 하부전극을 동시에 형성한 후, MIM 구조의 상부전극과 절연막 및 하부전극 즉, MIM 구조의 커패시터 패턴을 형성하기 위해 MIM 구조의 커패시터 패턴을 형성하기 위한 포토 마스킹 공정을 추가 진행하여 공정이 복잡해지는 어려움이 있었으며, 그에 따라 반도체소자의 제조수율이 감소되는 문제점이 있었다.However, if the conventional method of manufacturing a capacitor of the MIM structure as described above is used, the first metal film is etched to simultaneously form the second electrode and the lower electrode of the capacitor pattern of the MIM structure on the semiconductor substrate. In order to form the upper electrode, the insulating film, and the lower electrode of the structure, that is, the capacitor pattern of the MIM structure, a photo masking process for forming the capacitor pattern of the MIM structure was additionally performed, and thus, the process was complicated. There was a problem that the yield is reduced.
본 발명은 상기와 같은 문제점을 해결하기 위해 안출된 것으로, 본 발명의 목적은 상부 금속배선과 하부 금속배선을 연결할 수 있도록 상부 금속배선과 하부 금속배선 사이의 층간절연막 내에 플러그를 형성을 위한 듀얼다마신 식각공정 시, MIM 구조의 커패시터 형성영역도 같이 식각하여 MIM 구조의 커패시터 패턴을 형성함으로써, 반도체소자의 제조공정을 단순화하여 반도체소자의 제조 수율을 향상시키도록 하는 MIM 구조의 커패시터 제조방법을 제공하는 것이다.The present invention has been made to solve the above problems, an object of the present invention is a dual for forming a plug in the interlayer insulating film between the upper metal wiring and the lower metal wiring to connect the upper metal wiring and the lower metal wiring. In the etching process, the capacitor formation region of the MIM structure is also etched to form the capacitor pattern of the MIM structure, thereby simplifying the manufacturing process of the semiconductor device, thereby providing a manufacturing method of the capacitor of the MIM structure. It is.
도 1a 내지 도 1c는 종래 MIM 구조의 커패시터 제조방법을 설명하기 위해 순차적으로 나타낸 단면도이다.1A to 1C are cross-sectional views sequentially illustrating a method of manufacturing a capacitor having a conventional MIM structure.
도 2a 내지 도 2g는 본 발명의 실시예에 따른 MIM 구조의 커패시터 제조방법을 설명하기 위해 순차적으로 나타낸 단면도이다.2A through 2G are cross-sectional views sequentially illustrating a method of manufacturing a capacitor having a MIM structure according to an embodiment of the present invention.
-- 도면의 주요부분에 대한 부호의 설명 ---Explanation of symbols for the main parts of the drawing-
100 : 반도체기판 105 : 하부 금속배선100: semiconductor substrate 105: lower metal wiring
107 : 플러그 110 : 제1금속배선107: plug 110: first metal wiring
120：제1식각정지막 125 : 제1층간절연막120: first etching stop film 125: first interlayer insulating film
130 : 제1비아홀 133 : 상부 금속배선 패턴130: first via hole 133: upper metal wiring pattern
135 : MIM 구조의 커패시터 패턴 형성영역135: capacitor pattern forming region of the MIM structure
140 : 금속 확산방지막 145 : 제1금속막140: metal diffusion barrier 145: the first metal film
150 : 유전막 160 : 제2식각정지막150: dielectric film 160: second etching stop film
170 : 제2층간절연막 180 : 제2비아홀170: second interlayer insulating film 180: second via hole
200 : 제2금속막200: second metal film
상기 목적을 달성하기 위하여, 본 발명은 다른 반도체소자와 상호 연결되는MIM 구조의 커패시터를 제조하는 방법에 있어서, 하부에 제1금속배선이 형성된 반도체 기판 상에 제1식각정지막과 제1층간절연막을 증착하고 듀얼다마신 식각공정에 의해 제1금속배선 상부에 제1비아홀과 상부 금속배선을 형성하는 동시에 MIM 구조의 커패시터 패턴 형성영역을 형성하는 단계와, 상기 제1비아홀이 형성된 결과물 전면에 제1금속막을 증착하는 단계와, 상기 제1금속막이 증착된 결과물 상에 유전막을 증착하고 제1층간절연막 상부가 드러나도록 유전막과 제1금속막을 순차적으로 화학기계적 연마 공정을 진행하여 제거하는 단계와, 상기 제1층간절연막이 드러난 결과물 전체에 제2식각정지막과 제2층간절연막을 증착하고 듀얼다마신 식각에 의해 제1금속막 상부에 제2비아홀을 형성하는 동시에 유전막 상부에 MIM 구조의 커패시터의 상부전극 형성영역을 형성하는 단계와, 상기 제2비아홀이 형성된 결과물 전체에 제2금속막을 증착하여 제2층간절연막 내에 제2플러그와 MIM 구조의 커패시터의 상부전극을 동시에 형성하는 단계를 포함한다.In order to achieve the above object, the present invention provides a method for manufacturing a capacitor having a MIM structure interconnected with another semiconductor device, the first etching stop film and the first interlayer insulating film on a semiconductor substrate having a first metal wiring formed thereon Forming a first via hole and an upper metal wiring on the first metal wiring by a dual damascene etching process and simultaneously forming a capacitor pattern forming region of a MIM structure; Depositing a first metal film, depositing a dielectric film on the resultant on which the first metal film is deposited, and sequentially removing the dielectric film and the first metal film by a chemical mechanical polishing process so that an upper portion of the first interlayer insulating film is exposed; A second etch stop layer and a second interlayer dielectric layer are deposited on the entire resultant layer of the first interlayer dielectric layer, and the upper portion of the first metal layer is formed by dual damascene etching. Forming a second via hole and simultaneously forming an upper electrode formation region of a capacitor having a MIM structure on the dielectric layer; and depositing a second metal film on the entire product on which the second via hole is formed; Simultaneously forming the upper electrode of the capacitor of the structure.
본 발명은 상기 제1금속막과 제2금속막 증착단계 전에 전도성 물질을 사용하여 금속 확산 방지막을 형성하는 단계를 더 포함하는 것을 특징으로 한다.The present invention may further include forming a metal diffusion barrier layer using a conductive material before the deposition of the first metal layer and the second metal layer.
또한, 본 발명은 상기 유전막과 제1금속막을 화학기계적 연마 공정에 의해 제거 시, 제2금속막과 유전막을 동시에 제1금속막 상부까지 화학기계적 연마 공정을 진행하여 한번에 제거할 수 있는 것을 특징으로 한다.In addition, the present invention is characterized in that when the dielectric film and the first metal film is removed by a chemical mechanical polishing process, the second metal film and the dielectric film can be removed at a time by performing a chemical mechanical polishing process to the upper portion of the first metal film at the same time. do.
또한, 본 발명은 상기 유전막 형성 시, 질화물, 산화물, 실리콘 카바이드 및 강유전체 중 적어도 어느 하나를 사용하여 형성하며, 이때, 강유전체는 PZT 또는 BST 중 어느 하나를 사용하는 것을 특징으로 한다.In addition, the present invention is formed by using at least one of nitride, oxide, silicon carbide and ferroelectric when forming the dielectric film, wherein the ferroelectric is characterized in that using any one of PZT or BST.
이하, 첨부한 도면을 참조하여 본 발명의 바람직한 실시예에 대해 상세히 설명하고자 한다.Hereinafter, exemplary embodiments of the present invention will be described in detail with reference to the accompanying drawings.
도 2a 내지 도 2g는 본 발명의 실시예에 따른 MIM 구조의 커패시터 제조방법을 설명하기 위해 순차적으로 나타낸 단면도이다.2A through 2G are cross-sectional views sequentially illustrating a method of manufacturing a capacitor having a MIM structure according to an embodiment of the present invention.
먼저, 도 2a에 도시된 바와 같이 듀얼 다마신 공정에 의해 플러그 패턴 및 제1금속배선 패턴(미도시함)이 형성된 반도체기판(100) 상에 Cu를 증착한 후, 반도체기판(100) 상부까지 Cu를 화학기계적 연마하여 플러그(107) 및 제1금속배선(110)을 형성한다.First, as shown in FIG. 2A, Cu is deposited on a semiconductor substrate 100 on which a plug pattern and a first metal wiring pattern (not shown) are formed by a dual damascene process, and then to the upper portion of the semiconductor substrate 100. The Cu is mechanically polished to form the plug 107 and the first metal wiring 110.
또한, 상기 듀얼 다마신 공정에 의해 플러그 패턴 및 제1금속배선 패턴(미도시함)이 형성된 반도체기판(100)의 하부에는 후속 공정에 의해 형성될 MIM 커패시터의 하부전극을 외부 회로에 연결하기 위해 싱글 다마신(single damascene)공정에 의해 형성된 하부 금속배선(105)을 통해 미리 외부회로와 연결되어져 있다.In addition, in order to connect the lower electrode of the MIM capacitor to be formed by a subsequent process to the lower portion of the semiconductor substrate 100 on which the plug pattern and the first metal wiring pattern (not shown) are formed by the dual damascene process. It is previously connected to an external circuit through the lower metal wiring 105 formed by a single damascene process.
그리고, 도 2b에 도시된 바와 같이, 제1금속배선(110)이 형성된 반도체기판(100) 전면에 제1식각정지막(120)과 제1층간절연막(125)을 순차적으로 증착한다.As shown in FIG. 2B, the first etch stop layer 120 and the first interlayer insulating layer 125 are sequentially deposited on the entire surface of the semiconductor substrate 100 on which the first metal wiring 110 is formed.
도 2c에 도시된 바와 같이, 상기 제1층간절연막(125) 상부에 감광막을 도포하고 노광 및 현성공정을 진행하여 제1층간절연막(125) 상부에 제1비아홀과 상부 금속배선 및 MIM 구조의 커패시터 패턴 형성영역이 형성되도록 감광막 패턴(미도시함)을 형성한다. 그리고, 상기 감광막 패턴(미도시함)을 식각마스크로 듀얼다마신 식각 공정을 진행하여 제1층간절연막(125) 내에 제1금속배선(110) 상부에 제1비아홀(130)과 상부 금속배선 패턴(133)을 형성하는 동시에 MIM 구조의 커패시터 패턴 형성영역(135)을 형성한다. 이때, 상기 MIM 구조의 커패시터 패턴 형성영역(135)은 제1비아홀(130)의 상부 즉, 상부 금속배선 패턴의 CD보다 넓은 CD가 형성된다.As shown in FIG. 2C, a photoresist film is coated on the first interlayer insulating layer 125, and an exposure and a formation process are performed to form a capacitor having a first via hole, an upper metal wiring, and a MIM structure on the first interlayer insulating layer 125. A photoresist pattern (not shown) is formed to form a pattern formation region. In addition, a dual damascene etching process is performed using the photoresist pattern (not shown) as an etch mask to form a first via hole 130 and an upper metal wiring pattern on the first metal wiring 110 in the first interlayer insulating layer 125. The capacitor pattern forming region 135 of the MIM structure is formed at the same time as forming the 133. In this case, the capacitor pattern forming region 135 of the MIM structure has a CD that is wider than the CD of the upper portion of the first via hole 130, that is, the upper metal wiring pattern.
다음에, 도 2d에 도시된 바와 같이 듀얼다마신 식각 공정에 의해 제1비아홀(130)과 상부 금속배선 패턴 및 MIM 구조의 커패시터 패턴 형성영역(135)이 형성된 결과물 상에 Cu를 증착하여 제1금속막(140)을 형성한 후, 제1금속막(145) 상부에 유전막(150)을 형성한다. 이때, 상기 유전막(150)은 질화물, 산화물, 실리콘 카바이드 및 강유전체 중 적어도 어느 하나를 사용하여 형성하며, 또한 강유전체는 PZT 또는 BST 중 어느 하나를 사용한다.Next, as shown in FIG. 2D, Cu is deposited on the resultant formed by the dual damascene etching process to form the first via hole 130, the upper metallization pattern, and the capacitor pattern forming region 135 of the MIM structure. After the metal layer 140 is formed, the dielectric layer 150 is formed on the first metal layer 145. In this case, the dielectric layer 150 is formed using at least one of nitride, oxide, silicon carbide, and ferroelectric, and the ferroelectric uses any one of PZT or BST.
그리고, 상기 듀얼다마신 식각 공정에 의해 제1비아홀(130)과 상부 금속배선 패턴 및 MIM 구조의 커패시터 패턴 형성영역(135)이 형성된 결과물 상에 제1금속막(145)을 증착하기 전에 제1금속막(145)인 Cu가 확산되는 것을 방지하기 위해 전도체 물질을 이용하여 금속 확산 방지막(140)을 형성할 수 도 있다.The first via hole 130 and the upper metallization pattern and the capacitor pattern forming region 135 of the MIM structure are formed by the dual damascene etching process before the first metal layer 145 is deposited on the resultant. In order to prevent diffusion of Cu, the metal layer 145, the metal diffusion barrier layer 140 may be formed using a conductor material.
이때, 상기 제1비아홀(130)과 상부 금속배선 패턴은 CD가 작아 제1금속막(145)으로 완전히 매립되어 제1금속배선과 상부 금속배선을 전기적으로 연결해주는 제1플러그와 상부 금속배선의 역할을 하며, MIM 구조의 커패시터 패턴 형성영역(135)은 CD가 넓어 측벽과 하부에만 제1금속막(145)이 존재하여 MIM 구조의 커패시터의 하부전극 역할을 한다.In this case, the first via hole 130 and the upper metal wiring pattern have a small CD and are completely embedded in the first metal layer 145, so that the first plug and the upper metal wiring electrically connect the first metal wiring and the upper metal wiring. In the capacitor pattern forming region 135 of the MIM structure, since the CD is wide, the first metal layer 145 exists only on the sidewall and the bottom thereof, and thus serves as a lower electrode of the capacitor of the MIM structure.
이어서, 도 2e에 도시된 바와 같이 결과물 상의 유전막(150)과 제1금속막(145)을 화학기계적 연마 공정을 각각 진행하여 제1층간절연막(125) 상부가 드러나도록 화학기계적 연마 공정을 진행하여 유전막(150)과 제1금속막(145)을 제거한다. 이때, 상기 제1금속막(145) 형성 전에 금속 확산방지막(140)을 형성하였을 경우, 금속 확산 방지막(145) 또한 화학기계적 연마 공정에 의해 제거한다.Subsequently, as shown in FIG. 2E, the dielectric film 150 and the first metal film 145 on the resultant are subjected to a chemical mechanical polishing process so that the upper part of the first interlayer insulating film 125 is exposed. The dielectric layer 150 and the first metal layer 145 are removed. In this case, when the metal diffusion barrier 140 is formed before the first metal layer 145 is formed, the metal diffusion barrier 145 is also removed by a chemical mechanical polishing process.
또한, 상기 유전막(150)과 제1금속막(145)을 화학기계적 연마 공정에 의해 제거 시, 제1금속막(145)과 유전막(150)을 동시에 제1층간절연막(125) 상부까지 화학기계적 연마 공정을 진행하여 한번에 제거할 수 도 있다.In addition, when the dielectric film 150 and the first metal film 145 are removed by a chemical mechanical polishing process, the first metal film 145 and the dielectric film 150 are simultaneously chemically mechanically disposed on the upper portion of the first interlayer insulating film 125. It may be removed at a time by the polishing process.
다음에, 도 2f에 도시된 바와 같이 화학기계적 연마 공정에 의해 평탄해진 결과물 전체에 제2식각정지막(160)과 제2층간절연막(170)을 순차적으로 증착한다. 그리고, 상기 제2층간절연막(170) 상부에 감광막을 도포하고 노광 및 현성공정을 진행하여 제2층간절연막(170) 상부에 제2비아홀과 MIM 구조의 커패시터의 상부전극 형성영역이 형성되도록 감광막 패턴(미도시함)을 형성한다.Next, as illustrated in FIG. 2F, the second etch stop layer 160 and the second interlayer insulating layer 170 are sequentially deposited on the entire resultant flattened by the chemical mechanical polishing process. In addition, a photoresist film is coated on the second interlayer insulating film 170, and a photoresist pattern is formed such that an upper electrode formation region of the capacitor having a second via hole and a MIM structure is formed on the second interlayer insulating film 170. (Not shown).
이어서, 상기 감광막 패턴(미도시함)을 식각마스크로 듀얼다마신 식각 공정을 진행하여 제1금속막(145) 상부에 제2비아홀(180))을 형성하는 동시에 유전막(150) 상부에 MIM 구조의 커패시터의 상부전극 형성영역(185)을 형성한다.Subsequently, a dual damascene etching process is performed using the photoresist pattern (not shown) as an etch mask to form a second via hole 180 on the first metal layer 145 and at the same time, a MIM structure on the dielectric layer 150. An upper electrode forming region 185 of the capacitor is formed.
그 후, 도 2g에 도시된 바와 같이 듀얼다마신 식각 공정에 의해 제2비아홀(미도시함)과 MIM 구조의 커패시터의 상부전극 형성영역(미도시함)이 형성된 결과물 상에 Cu를 증착하여 제2금속막(200)을 형성한다. 또한, 상기 듀얼다마신 식각 공정에 의해 제2비아홀과 MIM 구조의 커패시터의 상부전극 형성영역이 형성된 결과물 상에 제2금속막(200)을 증착하기 전에 제2금속막(200)인 Cu가 확산되는 것을 방지하기 위해 전도체 물질을 이용하여 금속 확산 방지막(190)을 형성할 수 도 있다.Subsequently, as shown in FIG. 2G, Cu is deposited on a resultant on which a second via hole (not shown) and an upper electrode forming region (not shown) of the capacitor of the MIM structure are formed by a dual damascene etching process. The second metal film 200 is formed. In addition, Cu, which is the second metal layer 200, is diffused before the second metal layer 200 is deposited on the resultant formed by forming the second via hole and the upper electrode forming region of the capacitor having the MIM structure by the dual damascene etching process. The metal diffusion barrier layer 190 may be formed by using a conductive material to prevent it from being formed.
이때, 상기 제2비아홀은 제2금속막(200)으로 완전히 매립되어 제2플러그 역할을 하며, MIM 구조의 커패시터의 상부전극 형성영역 또한, 제2금속막(200)으로 매립되어 MIM 구조의 커패시터의 상부전극 역할을 한다.In this case, the second via hole is completely filled with the second metal film 200 to serve as a second plug, and the upper electrode forming region of the capacitor of the MIM structure is also filled with the second metal film 200 to form the capacitor of the MIM structure. It serves as the upper electrode of.
따라서, 상기한 바와 같이, 본 발명에 따른 반도체소자의 배선과 상호 연결되는 MIM 구조의 커패시터 제조방법을 이용하게 되면, 상부 금속배선과 하부 금속배선을 연결할 수 있도록 상부 금속배선과 하부 금속배선 사이의 층간절연막 내에 플러그를 형성을 위한 듀얼다마신 식각공정 시, MIM 구조의 커패시터 형성영역도 같이 식각하여 MIM 구조의 커패시터 패턴을 형성함으로써, 기존의 MIM 구조의 커패시터 패턴을 형성하기 위한 포토 마스킹 공정을 생략할 수 있어 반도체소자의 제조공정을 단순화시키며, 그에 따른 반도체소자의 제조 수율을 향상시킬 수 있다.Therefore, as described above, when the capacitor manufacturing method of the MIM structure interconnected with the wiring of the semiconductor device according to the present invention is used, between the upper metal wiring and the lower metal wiring so as to connect the upper metal wiring and the lower metal wiring. In the dual damascene etching process for forming a plug in the interlayer insulating film, the capacitor formation region of the MIM structure is also etched to form a capacitor pattern of the MIM structure, thereby omitting a photo masking process for forming a capacitor pattern of the existing MIM structure. It is possible to simplify the manufacturing process of the semiconductor device, thereby improving the manufacturing yield of the semiconductor device.
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| KR101100764B1 (en) * | 2004-12-02 | 2012-01-02 | 매그나칩 반도체 유한회사 | MIM capacitor fabricating method |
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| KR100364818B1 (en) * | 2000-04-06 | 2002-12-16 | 주식회사 하이닉스반도체 | method for manufacturing of semiconductor device |
| US6338999B1 (en) * | 2001-06-15 | 2002-01-15 | Silicon Integrated Systems Corp. | Method for forming metal capacitors with a damascene process |
| KR20040004809A (en) * | 2002-07-05 | 2004-01-16 | 주식회사 하이닉스반도체 | Method of manufacturing a copper wiring and a capacitor in a semiconductor device |
| KR100865944B1 (en) * | 2002-07-18 | 2008-10-30 | 매그나칩 반도체 유한회사 | Method for forming the capacitor of Metal-Insulator-Metal structure |
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| KR101100764B1 (en) * | 2004-12-02 | 2012-01-02 | 매그나칩 반도체 유한회사 | MIM capacitor fabricating method |
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