KR100250745B1 - Method of forming inter metal oxide of semiconductor device - Google Patents
Method of forming inter metal oxide of semiconductor device Download PDFInfo
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- KR100250745B1 KR100250745B1 KR1019930031173A KR930031173A KR100250745B1 KR 100250745 B1 KR100250745 B1 KR 100250745B1 KR 1019930031173 A KR1019930031173 A KR 1019930031173A KR 930031173 A KR930031173 A KR 930031173A KR 100250745 B1 KR100250745 B1 KR 100250745B1
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- South Korea
- Prior art keywords
- sog
- semiconductor device
- insulating film
- forming
- entire upper
- Prior art date
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- 238000000034 method Methods 0.000 title claims abstract description 38
- 239000004065 semiconductor Substances 0.000 title claims abstract description 10
- 229910044991 metal oxide Inorganic materials 0.000 title abstract description 3
- 150000004706 metal oxides Chemical class 0.000 title abstract description 3
- 239000002184 metal Substances 0.000 claims abstract description 14
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 claims abstract description 9
- LFQSCWFLJHTTHZ-UHFFFAOYSA-N Ethanol Chemical compound CCO LFQSCWFLJHTTHZ-UHFFFAOYSA-N 0.000 claims abstract description 8
- 239000011521 glass Substances 0.000 claims abstract description 7
- 238000011065 in-situ storage Methods 0.000 claims abstract description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 5
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 5
- 239000010703 silicon Substances 0.000 claims abstract description 5
- 239000000243 solution Substances 0.000 claims description 8
- 239000011248 coating agent Substances 0.000 claims description 7
- 238000000576 coating method Methods 0.000 claims description 7
- 238000000151 deposition Methods 0.000 claims description 4
- 239000000758 substrate Substances 0.000 claims description 4
- 239000010419 fine particle Substances 0.000 claims description 3
- 238000000206 photolithography Methods 0.000 claims description 3
- 238000002347 injection Methods 0.000 claims description 2
- 239000007924 injection Substances 0.000 claims description 2
- 239000003595 mist Substances 0.000 claims description 2
- 238000001259 photo etching Methods 0.000 abstract 1
- 238000005507 spraying Methods 0.000 description 2
- 230000004888 barrier function Effects 0.000 description 1
- 238000007664 blowing Methods 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000005260 corrosion Methods 0.000 description 1
- 230000007797 corrosion Effects 0.000 description 1
- 238000007865 diluting Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Formation Of Insulating Films (AREA)
Abstract
Description
제1(a)도 내지 제1(d)도는 본 발명에 따른 반도체 소자의 절연막 형성방법을 설명하기 위한 소자의 단면도.1 (a) to 1 (d) are cross-sectional views of a device for explaining a method of forming an insulating film of a semiconductor device according to the present invention.
* 도면의 주요부분에 대한 부호의 설명* Explanation of symbols for main parts of the drawings
1 : 중간 절연막 2 : 금속배선1: intermediate insulating film 2: metal wiring
3 : 제 1 산화막 4 : SOG3: first oxide film 4: SOG
5 : 제 2 산화막 10 : 실리콘 기판5: second oxide film 10: silicon substrate
본 발명은 반도체 소자의 절연막 형성방법에 관한 것으로, 특히 금속선층 사이에 절연막 형성시 인-시투(In-Situ) 공정에 의해 불필요한 영역의 SOG(Spin-On-Glass)를 제거하기 위해 알콜성분의 용액을 분사시키는 동시에 N2총(Gun)으로 블로우-오프(blow-off)시키므로써 금속선층 절연막(Inter Metal Oxide)의 평탄화를 이룰 수 있는 반도체 소자의 절연막 형성방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of forming an insulating film of a semiconductor device, and more particularly, to remove spin-on-glass (SOG) in an unnecessary area by an in-situ process when forming an insulating film between metal wire layers. The present invention relates to a method for forming an insulating film of a semiconductor device capable of achieving planarization of an inter metal oxide by blowing a solution and blow-off with an N 2 gun.
일반적으로 SOG 코팅(Coating)을 이용한 금속선층 사이의 절연막(Inter Metal Oxide) 평탄화 방법은 SOG를 코팅(coating)후 그대로 사용하는 방법과 SOG를 코팅한 후 에치-백(etch-back)하여 필요없는 부분의 SOG를 제거하는 방법이 사용되는데, 그대로 사용하는 방법은 SOG-산화막으로부터 금속선을 부식시키고 단차(Topology)를 나쁘게 만들며, 불필요한 영역의 SOG를 제거하는 방법은 공정수가 증가하고 오염문제가 발생된다.In general, an intermetal oxide planarization method between SOG coating (SOG coating) is used as it is after coating (SOG) coating and etch-back after the SOG coating is not necessary The method of removing the SOG of the part is used. The method of using it as it is corrodes the metal wire from the SOG-oxide film and makes the topology worse, and the method of removing the unnecessary area of SOG increases the number of processes and causes the problem of contamination. .
따라서 본 발명은 금속선층 사이에 절연막 형성시 인-시투(In-Situ) 공정에 의해 불필요한 영역의 SOG(Spin-On-Glass)를 제거하기 위해 알콜성분의 용액을 분사시키는 동시에 N2총(Gun)으로 블로우-오프(blow-off)시키므로써 상기한 단점을 해소할 수 있는 반도체 소자의 절연막 형성방법을 제공하는데 그 목적이 있다.Therefore, in the present invention, when an insulating film is formed between the metal wire layers, an alcohol-based solution is sprayed to remove unnecessary SOG (Spin-On-Glass) in an in-situ process, and an N 2 gun (Gun It is an object of the present invention to provide a method for forming an insulating film of a semiconductor device that can solve the above disadvantages by blow-off ().
상기한 목적을 달성하기 위한 본 발명은 실리콘 기판(10)상의 중간 절연막(1) 상부에 소정두께의 금속층을 형성한 다음 마스크 공정 및 사진식각 공정을 진행하여 금속선(2)을 형성하고 그 상부 전체면에 PECVD 공정에 의해 제 1 산화막(3)을 증착하는 단계와, 상기 단계로부터 상부 전체면에 SOG(Spin-On-Glass)(4)를 코팅(coating) 한 다음 필요없는 부분의 SOG를 인-시투(In-Situ) 공정에 의해 제거하기 위하여 웨이퍼를 빠른 속도로 회전시키면서 초음파에 의해 미립자의 안개상태로 만들어진 알콜성분의 용액을 웨이퍼 상부에 적당간격 및 방향으로 설정된 노즐을 통하여 분사하는 동시에 N2총(Gun)으로 블로우-오프(blow-off)시키는 단계와, 상기 단계로부터 SOG를 큐어링(Curing)시킨 다음 상부 전체면에 PECVD 공정에 의해 제 2 산화막(5)을 증착하는 단계로 이루어지는 것을 특징으로 한다.The present invention for achieving the above object is to form a metal layer of a predetermined thickness on the intermediate insulating film (1) on the silicon substrate 10, and then proceed to the mask process and photolithography process to form the metal wire (2) and the entire upper portion Depositing a first oxide film 3 on the surface by a PECVD process, coating spin-on-glass 4 on the entire upper surface from the step, and While spraying the wafer at high speed to remove it by the in-situ process, an alcohol-based solution made of fine particles of mist by ultrasonic waves is sprayed on the top of the wafer through nozzles set at suitable intervals and directions. Blow-off with 2 guns, and curing the SOG from the step, and then depositing a second oxide film 5 on the entire upper surface by a PECVD process. Thing And a gong.
이하, 첨부된 도면을 참조하여 본 발명을 상세히 설명하기로 한다.Hereinafter, with reference to the accompanying drawings will be described in detail the present invention.
제1(a) 내지 1(d)도는 본 발명에 따른 반도체 소자의 절연막 형성방법을 설명하기 위한 소자의 단면도로서, 제1(a)도는 실리콘 기판(10)상의 중간 절연막(1) 상부에 소정두께의 금속층을 형성한 다음 마스크 공정 및 사진식각 공정을 진행하여 금속선(2)을 형성하고 그 상부 전체면에 PECVD(Plama-Enhanced CVD)공정에 의해 제 1 산화막(3)을 증착한 상태의 단면도이다.1 (a) to 1 (d) are cross-sectional views of a device for explaining a method of forming an insulating film of a semiconductor device according to the present invention. FIG. 1 (a) is a predetermined portion over an intermediate insulating film 1 on a silicon substrate 10. FIG. After forming a metal layer having a thickness, a mask process and a photolithography process are performed to form a metal line 2, and a cross-sectional view of a state in which the first oxide film 3 is deposited by a plasma-enhanced CVD (PECVD) process on the entire upper surface thereof. to be.
제1(b)도는 제1(a)도의 상부 전체면에 SOG(Spin-On-Glass)를 코팅(coating)한 상태의 단면도이다.FIG. 1 (b) is a cross-sectional view of a state in which spin-on-glass (SOG) is coated on the entire upper surface of FIG. 1 (a).
제1(c)도는 필요없는 부분의 SOG를 인-시투(In-Situ) 공정에 의해 제거하기 위하여 제1(b)도 상태의 웨이퍼를 빠른 속도로 회전시키며 초음파에 의해 미립자의 안개 상태로 만들어진 알콜성분의 용액이 웨이퍼 상부에 적당간격 및 방향으로 설정된 노즐(nozzle)을 통하여 분사하면서 N2총(Gun)으로 블로우-오프(blow-off) 시키면 외부에서 강제적으로 불어넣어 주는 N2의 압력에 의해 필요없는 부분의 SOG는 알콜성분에 의해 희석되어 제거되고 골짜기 또는 구석진 부분은 장벽역할을 하여 SOG(4)가 남아있는 상태의 단면도인데, 이때 알콜성분의 용액분사는 생략되어도 된다.In order to remove the SOG of the first part (c) which is not necessary by the in-situ process, the wafer of the first part (b) is rotated at a high speed and made into fine particles by ultrasonic waves. When the alcohol-based solution is blown off with the N 2 Gun while spraying the nozzle on the wafer through the nozzle set at the proper interval and direction, it is forced to the pressure of N 2 which is forcibly blown from the outside. This is a cross-sectional view of the SOG of the part which is not necessary by diluting by the alcohol component, and the valley or the corner part serving as a barrier, so that the SOG 4 remains. In this case, the solution injection of the alcohol component may be omitted.
제1(d)도는 제3도의 상태에서 SOG(4)를 큐어링(Curing) 시킨다음 상부전체면에 PECVD 공정에 의해 제 2 산화막(5)을 증착한 후 평탄화된 상태의 단면도이다.FIG. 1 (d) is a cross-sectional view of the planarized state after the SOG 4 is cured in the state shown in FIG. 3 and the second oxide film 5 is deposited on the entire upper surface by a PECVD process.
상술한 바와같이 본 발명에 의하면 금속선층 사이에 절연막 형성시 인-시투(In-Situ) 공정에 의해 불필요한 영역의 SOG(Spin-On-Glass)를 제거하기 위해 알콜성분의 용액을 분사시키는 동시에 N2총(Gun)으로 블로우-오프(blow-off)시키므로써 금속선의 부식 및 단차(Topology)를 감소시키며 절연막의 평탄화를 달성할 수 있는 탁월한 효과가 있다.As described above, according to the present invention, an N-containing solution is sprayed to remove unnecessary spin-on-glass (SOG) in an in-situ process when an insulating film is formed between the metal wire layers. 2 Blow-off by Gun reduces the corrosion and topology of the metal wire and has an excellent effect of achieving planarization of the insulating film.
Claims (2)
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930031173A KR100250745B1 (en) | 1993-12-30 | 1993-12-30 | Method of forming inter metal oxide of semiconductor device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| KR1019930031173A KR100250745B1 (en) | 1993-12-30 | 1993-12-30 | Method of forming inter metal oxide of semiconductor device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| KR950021162A KR950021162A (en) | 1995-07-26 |
| KR100250745B1 true KR100250745B1 (en) | 2000-06-01 |
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| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| KR1019930031173A KR100250745B1 (en) | 1993-12-30 | 1993-12-30 | Method of forming inter metal oxide of semiconductor device |
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| Country | Link |
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| KR (1) | KR100250745B1 (en) |
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100390892B1 (en) * | 1996-10-29 | 2003-10-04 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device |
-
1993
- 1993-12-30 KR KR1019930031173A patent/KR100250745B1/en not_active IP Right Cessation
Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100390892B1 (en) * | 1996-10-29 | 2003-10-04 | 주식회사 하이닉스반도체 | Method for manufacturing semiconductor device |
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| Publication number | Publication date |
|---|---|
| KR950021162A (en) | 1995-07-26 |
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