JPH06181289A - Semiconductor device - Google Patents

Abstract

PURPOSE:To provide a semiconductor device which is used in a high frequency band and has an inductance to be freely placed. CONSTITUTION:A metal thin film grounded substantially on an entire surface except a peripheral part is formed on a surface of a semiconductor substrate through an insulating film made of polyimide, etc., and an inductance 6 is formed thereon also through a polyimide film. Pads 7, 9 of the inductance 6 and a pad 101 of the metal thin film are formed on a peripheral edge part not formed with the metal thin film. Since the metal thin film is formed, high frequency characteristics are improved, a position of the inductance 6 can be formed at an arbitrary place on the metal thin film, and the degree of freedom of design is increased.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device having an inductance and excellent high frequency characteristics, and a method of manufacturing the same.

[0002]

2. Description of the Related Art Semiconductor devices such as ICs and LSIs are equipped with passive elements such as inductances, resistors and capacitors. A conventional semiconductor device having an inductance will be described with reference to FIGS. As the semiconductor substrate, for example, a silicon semiconductor substrate 13 is used, and a MOSIC or a bipolar is formed on the surface area of the main surface of the semiconductor substrate 13.
An integrated circuit (not shown) such as a semiconductor integrated circuit is formed.
An interlayer insulating film ₂ such as SiO ₂ is formed on the semiconductor substrate 13, and a predetermined pattern electrically connected to the integrated circuit formed inside the semiconductor substrate 13 is formed thereon. The wiring 3 made of Al or polysilicon having a metal is formed. The connection wiring 3 is connected to the integrated circuit by connecting the wiring 3 to an electrode pad formed on the peripheral portion of the main surface of the semiconductor substrate 13 and connecting the electrode pad to the integrated circuit inside the semiconductor substrate 13. Done by The wiring 3 can be directly connected to the element region of the semiconductor substrate 13 without connecting to the electrode pad in this way, or a single layer or multilayer wiring on the semiconductor substrate 13 connected to this integrated circuit You can also connect. Further, an interlayer insulating film 4 such as SiO ₂ is applied on the wiring 3 to cover the wiring 3. The interlayer insulating film 4 has a flattened surface and Al
A planar type inductance 6 composed of, for example, is formed in a spiral shape. A terminal 5 is formed at the center of the spiral inductance 6, and the terminal 5 is connected to the wiring 3 through a contact hole 41 formed in the interlayer insulating film 4. The inductance 6 is a passivation film (not shown) made of a well-known insulating film such as BPSG.
Is covered and protected. The semiconductor substrate 13 has an integrated circuit formed therein, but without forming an internal circuit in this semiconductor substrate, at least one semiconductor substrate having an integrated circuit formed therein is separately prepared. It is also known to form a multi-chip type semiconductor device by encapsulating the semiconductor substrate 13 in one package.

[0003]

In recent years, semiconductor devices have been increasingly used at high frequencies. In the above-described conventional semiconductor device including an inductance, the reflection of a signal in a spiral inductance has become a serious problem in consideration of use in a high frequency region. This is especially characteristic
The cause is that the dance is not consistent. Conventionally, a silicon oxide film is used for the interlayer insulating film,
Since its dielectric constant is large, there is also a problem that the capacitance between wirings becomes large. Al or the like is usually used as the wiring material, but its resistance is large, and the resistance component increases as the semiconductor device becomes finer. Therefore, in the semiconductor device having this structure, in the frequency band of 100 MHz or higher, Q
The factor is reduced and good inductance cannot be formed. Further, the ratio of the area of the inductance to the integrated circuit is considerably large, and it has been difficult to incorporate it into the integrated circuit. The present invention has been made under such circumstances, and an object of the present invention is to provide a semiconductor device having a planar type inductance that can be used in a high frequency region and can be freely arranged.

[0004]

According to the present invention, a thin metal layer which is grounded is formed close to an inductance formed on a semiconductor substrate, and a low dielectric constant material is used as a material for an interlayer insulating film. Is characterized by. A semiconductor device of the present invention includes a semiconductor substrate, a first insulating film formed on a main surface of the semiconductor substrate, and a first insulating film formed on the first insulating film, and covering substantially the entire main surface of the semiconductor substrate. A grounded metal thin layer for covering, a second insulating film formed on the main surface of the semiconductor substrate so as to cover the metal thin layer, and arranged so as to be arranged on the metal thin layer, The first characteristic is that the inductor is provided on the second insulating film. The semiconductor substrate, the first insulating film formed on the main surface of the semiconductor substrate, the inductance formed on the first insulating film, and the first insulating film so as to cover the inductance. A second insulating film formed on the second insulating film, and a grounded metal thin layer formed on the second insulating film and covering substantially the entire main surface of the semiconductor substrate. It has a second feature. A metal layer connected to the thin metal layer by a connection wiring is further on the same plane as the inductance,
It can be formed close to this. A metal film may be provided on the insulating film on the thin metal layer to form a capacitor having the metal film as a first electrode and the thin metal layer as a second electrode.

The inductance may be provided with terminals formed at both ends thereof and at least one terminal formed in the middle thereof. Furthermore, a semiconductor substrate, an insulating film having a device hole on which the semiconductor substrate is mounted, an inductance formed on the first main surface of the insulating film, and electrically connected to the semiconductor substrate, Formed on the first main surface of the insulating film,
A plurality of leads, one end of which is connected to the connection electrode of the semiconductor substrate, and a grounded metal thin film, which is opposed to almost the entire second main surface of the insulating film and is joined thereto, are provided. The third feature is the provision. And
At least one semiconductor substrate, a lead frame having two or more substrate mounting portions formed thereon, and an insulating film formed on substantially the entire surface of at least one of the substrate mounting portions;
And an inductance formed on the insulating film, the semiconductor substrate is not placed on the substrate placing portion on which the inductance is formed, and the substrate placing portion is grounded, A fourth feature is that the semiconductor substrates are respectively mounted on the remaining substrate mounting portions.

[0006]

By forming the thin metal layer, the characteristic impedance of the metal wiring can be accurately set to 50Ω. Further, by using a low dielectric constant material such as polyimide for the insulating film between layers, the capacitance between wirings can be greatly reduced. Due to the presence of the grounded thin metal layer formed on almost the entire surface of the semiconductor substrate, it is possible to secure a sufficient degree of freedom in the design stage when forming the inductance, the lead or the capacitance.

[0007]

Embodiments of the present invention will be described below with reference to the drawings. First, a first embodiment will be described with reference to FIGS. FIG. 1 is a plan view of the semiconductor device, and FIG. 2 is a cross-sectional view taken along the line AA ′ in the previous figure. FIG. 3 is a characteristic diagram showing the frequency dependence of the high frequency loss of the semiconductor device of the conventional example and that of the present invention. 4 to 6 are partial cross-sectional views showing other examples of the substrate. For example, a silicon semiconductor substrate 1 is used as a substrate, and a first insulating film 2 made of, for example, polyimide is formed on the silicon semiconductor substrate 1. Next, a thin metal layer 10 made of Cu, for example, is formed on substantially the entire surface of the semiconductor substrate 1 by, for example, sputtering. The thin metal layer 10 is located in the peripheral portion of the semiconductor substrate 1, and is a region where a connection electrode, that is, an electrode pad, is provided for electrically connecting the metal thin film 10 and an inductance formed later to the other. Since it is not formed on the semiconductor substrate 1,
Does not completely cover the entire surface. This thin metal layer 1
A second insulating film 4 made of polyimide or the like is formed thereon so as to cover 0, a connection wiring 3 made of Cu or the like is formed on the second insulating film 4, and this is covered with a third insulating film 8 made of polyimide or the like. To do. One end of the connection wiring 3 is connected to the electrode pad 7 exposed at the peripheral portion of the semiconductor substrate 1.

Next, using a patterned photoresist, RIE (Reactive Reactive) is applied to a predetermined region of the insulating film 8.
The connection wiring 3 is partially exposed by forming the contact hole 81 by Ion etching or the like. Then, on the insulating film 8, using a photoresist, for example, Cu
The inductance 6 is formed in a spiral shape. One end thereof is formed substantially at the center of the inductance 6, and the connection wiring 3 is formed through the terminal 5 formed in the contact hole 81.
Is connected to the other end of. The other end of the inductance 6 is
It is connected to the electrode pad 9 exposed at the peripheral portion of the semiconductor substrate 1. Next, the surface of the semiconductor substrate 1 including the inductance 6 is protected by a passivation film (not shown) such as polyimide. In FIG. 1, the illustration of the insulating films 2, 4, and 8 shown in FIG. 2 is omitted. In this embodiment, no integrated circuit is formed on the semiconductor substrate 1. Then, at least one semiconductor substrate having an integrated circuit formed therein is prepared separately, and this semiconductor substrate is sealed together with the semiconductor substrate 1 into one package to form a multi-chip type semiconductor device. This semiconductor device can be integrated on a system scale by adopting a multi-chip structure.

Substrate 1 on which this inductance is formed
Can be bonded to a semiconductor substrate having an element region in which an integrated circuit is formed, for example, a silicon semiconductor substrate, packaged, and incorporated into a small device such as a mobile communication device as a one-chip semiconductor device. As described above, it is possible to incorporate passive elements such as capacitors and resistors on a semiconductor substrate on which an inductance is formed and an integrated circuit is not formed. A semiconductor substrate incorporating this passive element and a semiconductor substrate on which an integrated circuit is formed To form a semiconductor device. As a method of combination, first, there is a method of directly attaching the substrate of the passive element to the semiconductor substrate on which the integrated circuit is formed by using an adhesive or the like. There is also a combination method of connecting the semiconductor substrate and the substrate of the passive element by wiring such as wire bonding. TAB (Tape
Automated Bonding) tape can be used, and both substrates can be electrically connected using a lead frame. A plurality of terminals 101 exposed on the surface are formed on the thin metal layer 10. One is connected to a thin metal layer formed on another semiconductor substrate, and the other is a GND terminal to be grounded.

The thin metal layer can eliminate variations in characteristic impedance that prevent reflection of high frequency signals entering the inductance. As shown in the characteristic diagram of FIG. 3, when the thin metal layer is not formed, assuming that −3.0 dB is the reference line that determines the quality of the characteristic, the frequency is about 0.1 to 3 GHz.
When it is about the range, the characteristics are good, but when it is out of this range, the loss becomes large and it becomes difficult to use. On the other hand, by providing this thin metal layer, it can be used up to 10.0 GHz or higher. In this way, the inductance matches the characteristic impedance by forming it on the thin metal layer,
Although reflection and loss of high-frequency signals passing through the inductance can be reduced, the effect of such a thin metal layer is caused by the thin metal layer being close to the inductance. It doesn't really matter if they are close in shape.

For example, FIG. 4 shows an example in which a thin metal layer is formed under the inductance, and a metal layer branched from this thin metal layer is arranged between the spirals of the inductance. A first insulating film 2 made of polyimide is formed on a silicon semiconductor substrate 1, and a thin metal layer 10 is formed on the first insulating film 2 on almost the entire surface of the semiconductor substrate except the peripheral portion. A second insulating film 4 made of polyimide is covered thereover, and the connecting wiring 3 for the inductance is formed thereon by Cu or the like. Next, the third insulating film 8 made of polyimide is formed on the connection wiring 3 and the second insulating film 4, and the spiral inductance 6 is formed thereon. A terminal 5 is formed at the tip of the central portion of the inductance 6, and this terminal is connected to the connection wiring 3 through a contact hole formed in the third insulating film 8. A metal layer 104 of Cu or the like is formed in an arbitrary shape on the third insulating film 8 so as to be arranged between the spiral inductances 6, and is formed on the second and third insulating films 4 and 8. The metal layer 104 and the thin metal layer 10 are connected by the connection electrode 103 through the contact hole. The surface of this semiconductor substrate 1 is
It is protected by a polyimide passivation film (not shown). According to this structure, the inductance 6 and the metal layer 104
The distance d ′ between the thin metal layer 10 and the inductance 6 shown in FIG. 2 can be halved, and the distance between the thin metal layer 10 and the inductance 6 needs to be particularly considered. Therefore, the position of the thin metal layer 10 can be set arbitrarily.

That is, d'can be set to about d / 2, but in the figure, it is exaggeratedly drawn to emphasize the size of d '. Next, another example of this embodiment will be described with reference to FIG. In this example, a thin metal layer is formed on the inductance, and a metal layer branched from the thin metal layer is arranged between the spirals of the inductance. A first insulating film 2 made of polyimide is formed on a silicon semiconductor substrate 1, and a connection wiring 3 having an inductance such as Cu is formed on the first insulating film 2. A second insulating film 4 made of polyimide is formed thereon, and a spiral inductance 6 made of Cu or the like is formed on the second insulating film 4 and Cu having an arbitrary shape is formed between the spiral spiral members.
The metal layer 104 of is formed. And the inductance 6
The terminal 5 is formed at the tip of the central part of the
Connection wiring 3 through the contact hole formed in the insulating film 4 of
Connect with. Then, the inductance 6 and the metal layer 10
A third insulating film 8 made of polyimide is formed so as to cover 4 and the like, and a thin metal layer 10 is formed on the third insulating film 8 on almost the entire surface of the semiconductor substrate except the peripheral portion. Next, the metal layer 10 is passed through the contact hole formed in the third insulating film 8.
4 and the thin metal layer 10 are connected by a connecting electrode. The surface of the semiconductor substrate 1 is protected by a polyimide passivation film (not shown). The metal layer 104 branched from the thin metal layer thus formed can match the characteristic impedance of the inductance.

Therefore, if the metal layer 104 is close to the inductance 6, even if the metal thin layer 10 is slightly away from the inductance 6, there is no particular effect on the function and effect. As a result, the characteristic impedance does not change even if the thin metal layer is arranged at a stepped portion where the change is large. Furthermore, as shown in FIG. 6, a structure in which the positions of the inductance 6 and the metal thin layer 10 in FIG. 2 are simply replaced can be applied to the present invention. In this case, it is preferable that the distance between them be the same as in FIG. The material of the thin metal layer is not limited to Cu, but Au, Al, or the like can be used. Materials having a low dielectric constant used for an insulating film such as an interlayer insulating film include epoxy resin in addition to polyimide. The distance d between the inductance 6 and the thin metal layer 10 is
About several μm to several tens of μm is suitable. In particular, the insulating film thickness between polyimide and a thin metal layer is about 1 to 10 μm for polyimide and about 10 to 50 μm for SiO ₂ film.

Next, a second embodiment will be described with reference to FIGS. FIG. 7 is a plan view of a semiconductor substrate having an inductance and a capacitor closet formed on its surface, and FIG. 8 is the same plan view as FIG.
S2 is added. 9 is a partial plan view of the inductance forming region of the region S1, FIG. 10 is a partial plan view of the capacitor region of the region S2, and FIG. 11 is BB 'of FIG.
It is a sectional view of a part. A semiconductor substrate 1 is covered with a first interlayer insulating film 2 having a low dielectric constant such as polyimide. A thin metal layer 10 of Cu or the like is formed on the first interlayer insulating film 2 over almost the entire surface of the semiconductor substrate 1 except for the peripheral portion thereof.
For example, it is formed by vacuum vapor deposition or the like. In this metal thin layer 10, at least one electrode pad 101 that serves as a GND terminal and at least one electrode pad 102 that is used as a lead electrode of a capacitor are formed in the peripheral portion of the semiconductor substrate 1. The thin metal layer 10 is covered with the second interlayer insulating film 4 made of a low dielectric constant material such as polyimide. An inductance connecting wiring 3 is formed on the second interlayer insulating film 4 by an etching process using a photoresist, and one end thereof is formed in a region where a central portion of the spiral inductance is to be formed, The other end is led out to the periphery of the semiconductor substrate 1 and the electrode pad 7 serving as an external terminal is formed there. Other connection wirings 31 and 32 are further formed on the second interlayer insulating film 4.

One end of them is formed in a region where a spiral inductance is to be formed, and the other end thereof is led out to the peripheral portion of the semiconductor substrate 1 and an electrode pad 9 serving as an external terminal is formed there.
1 and 92 are formed respectively. A third interlayer insulating film 8 of a low dielectric constant material such as polyimide is formed on the second interlayer insulating film 4 so as to cover these connection wirings. A pair of spiral inductors 6 made of a low resistance material such as Cu is formed on the interlayer insulating film 8. A contact hole is formed in the interlayer insulating film 8 by anisotropic etching or the like to expose one end portion of the connection wiring 3 below the interlayer insulating film 8, and the inductance 6 and the connection wiring 3 are contacted by the terminal 5 of the inductance 6. Connection is made through a hole (this contact portion has the same structure as in FIG. 2). Similarly, contact holes are formed in the other portions of the third interlayer insulating film 8 to expose one ends of the connection wirings 31 and 32, respectively, and the arbitrary portions of the inductance 6 and the connection wirings 31 and 3 are exposed.
2 are connected by terminals 51 and 52 formed in these contact holes, respectively. After the connection wiring is connected to the inductance, the surface of the semiconductor substrate 1 is covered and protected with a passivation insulating film (not shown) such as BPSG. The distance d between the surface of the thin metal layer 10 and the surface of the third interlayer insulating film 8 on which the inductance 6 is formed, that is, the inductance / thin metal layer is the interlayer insulating film 4 in this embodiment.
Since polyimide is used for 8, it is about 1 μm to 10 μm
I have to.

As described above, when the inductance is formed on the thin metal layer, the characteristic impedance is matched and reflection of a high frequency signal passing through the inductance can be reduced. Further, since the thin metal layer is formed on almost the entire surface of the semiconductor substrate, the degree of freedom of the position of the inductance formed on the semiconductor substrate is increased. Further, in this embodiment, in addition to the electrode pads 9 and the terminals 5 at both ends of the inductance 6, some terminals 51 and 52 are formed in the middle of the metal wiring pattern of the inductance 6. In this embodiment, two terminals are formed, but the number of terminals is arbitrary and can be provided as required. The terminals provided in the middle of these metal wiring patterns play the same role as the electrode pad 9, and any one of these terminals including the electrode pad 9 and the terminal formed at the center of the inductance 6 are provided. Inductance with 5 is formed. Then, by selecting any one of the terminals, the characteristic of the configured inductance can be arbitrarily determined.

Next, the capacitor of this embodiment will be described with reference to FIGS. The thin metal layer 10 made of Cu or the like used in the present invention can be used for one electrode of the capacitor. An electrode pad 102 used as a lead electrode of a capacitor is connected to the thin metal layer 10, and the surface of the electrode pad 102 is exposed. A second insulating film 4 made of polyimide or the like is formed on the thin metal layer 10, and a plurality of metal layers 11 made of Cu or the like serving as the other electrode of the capacitor are formed thereon. A metal wiring layer 12 made of Cu or the like is formed on these so as to connect the metal layers 11 to each other. The metal wiring layer 12 has a region extending to the peripheral portion of the semiconductor substrate 1, and a plurality of terminals 121 exposed on the surface of the semiconductor substrate 1 are formed in this region. Here, a capacitor having the metal thin layer 10 and the metal layer 11 as opposed electrodes and the second insulating film 4 as a dielectric is formed. As described above, in order to form a semiconductor device using a semiconductor substrate on which an inductance is formed, an example of forming an integrated circuit on the semiconductor substrate itself, a semiconductor on which the inductance is formed on the semiconductor substrate on which the integrated circuit is formed Examples include mounting a substrate or mounting a plurality of semiconductor substrates including a semiconductor substrate having an inductance formed on a semiconductor substrate mounting portion of a lead frame and housing these semiconductor substrates in one package.

Next, with reference to FIGS. 12 to 20, an example of a semiconductor device configured by combining the semiconductor substrate having the inductance formed thereon with another semiconductor substrate will be described. 12
FIG. 4 is a sectional view of a semiconductor device in which the inductance is formed on a semiconductor substrate on which an integrated circuit and the like are formed. An integrated circuit, a resistor array, etc. are formed on the semiconductor substrate 13, a wiring structure such as a multilayer wiring is formed on the surface thereof, and a passivation insulating film is formed so as to cover them (not shown). . The lead wiring 1 made of Al or the like is formed on the surface of the semiconductor substrate 13 having the surface thus treated.
4 is formed by using a sputtering method or the like. The surface of the lead wiring is plated with Au or Sn. The semiconductor substrate 1 having the inductance 6 formed on the surface of the semiconductor substrate 13 is bonded with an adhesive such as an insulating epoxy resin. The electrode pads 7 and 9 of the inductance and the capacitor formed in the peripheral portion of the semiconductor substrate 1 and the lead wiring 14 on the semiconductor substrate 13 are connected by wire bonding 15 or the like. The thin metal layer 10 is connected to the GND terminal of the semiconductor substrate 13 by one of wire bondings 14. Since the drawing is schematically drawn, the entire surface of the semiconductor substrate 1 is covered with the metal thin film 10. However, in practice, this thin film is not formed on the peripheral portion of the semiconductor substrate 1 as shown in FIG. The following drawings are also the same.

FIG. 13 is a sectional view of a semiconductor device in which the lead wiring 14 on the semiconductor substrate 13 and the semiconductor substrate 1 are connected via Au bumps or the like formed on the electrode pads 7 and 9 on the semiconductor substrate 1. is there. Bumps are also attached to the terminals 101 of the thin metal layer 10 on the surface of the semiconductor substrate 1 and connected to the ground lead wire of the lead wires 14. Figure 14
3 is a cross-sectional view of a semiconductor device in which the semiconductor substrate 1 is mounted on a TAB (Tape Automated Bonding) tape, and the leads 17 attached to the insulating film 16 of the TAB tape are soldered to the lead wirings 14 of the semiconductor substrate 13. FIG. The semiconductor substrate 1 on which the inductance and the capacitor are formed is not efficient to use the TAB tape because it does not use many leads. The leads 17 are also connected to the terminals of the thin metal layer 10 on the surface of the semiconductor substrate 1, and the terminals are connected to the ground lead wires of the lead wires 14 via the leads 17.
The surface of the semiconductor substrate 1 is covered with, for example, a mold resin 25.

FIG. 15 is a plan view of a semiconductor device having an inductance mounted on a TAB tape, and FIG. 16 is a partial sectional view thereof. In this embodiment, the inductance 6 is formed together with the lead 17 on the insulating film 16 of the TAB tape. In accordance with the method of forming a TAB tape, a Cu foil is attached to the polyimide film 16 and is selectively etched to form the inductance and the lead 17 in the same process. At one end of the inductance connected to the external circuit, connection wires 31 and 32 are formed at a branch portion where a branch point is provided near the one end of the inductance,
Their ends are also adapted to be connected to external circuits. The other end of the inductance 6 is connected to a connection wiring 3 such as Cu, and this connection wiring 3 projects into the device hole 19 of the TAB tape,
It is connected to the connection electrodes formed in the peripheral portion of the semiconductor substrate 13 mounted inside. In this TAB tape, after the unnecessary portion is connected and removed, the lead 17 and the connection wiring 3 of the branch portion
1, 32 and the one end of the inductance coil are connected to the circuit pattern of the circuit board. To attach the metal thin film 10 to the TAB tape, the second insulating film 21 having the metal thin layer 10 such as Cu foil attached is attached to the back side of the first insulating film 16 having the connection wirings 3, 31, 32 formed thereon. . At this time, when the thin metal layer is attached so as to cover almost the entire area of the polyimide film 16 (the peripheral portion such as the feed hole portion may be included, or only the portion surrounded by the opening may be attached), The high frequency characteristics for the leads can also be improved (FIG. 16).

FIG. 17 shows an example of the TAB tape 26 having two device holes formed therein. The number of device holes in the TAB tape may be two or more, and each size may be different. One device hole 1
The semiconductor substrate 1 having an inductance formed therein is mounted at 91, while the semiconductor substrate 13 having an integrated circuit and a resistor array formed thereon is mounted at the device hole 192. It is also possible to form the inductance of FIG. 16 on the film 16 of the TAB tape 26 described in this figure, and the configuration can be appropriately combined.

Next, a semiconductor device using a lead frame will be described. FIG. 18 is a sectional view of the semiconductor device. The semiconductor substrate mounting portion (hereinafter referred to as bed portion) 22 of the lead frame made of Cu or the like is mounted with the semiconductor substrate 1 having an inductance, and the other bed portions 221 and 222 are integrated circuits. A semiconductor substrate 13 on which a resistor array is formed is mounted. Bonding wires 15 are used to connect the semiconductor substrates and the semiconductor substrate and the leads 23 of the lead frame to each other. Thin metal layer 10 of semiconductor substrate 1
Is also connected to the ground lead 24 of the lead frame using a bonding wire. The semiconductor substrate, the bed portion, the bonding wires, and part of the leads are covered with a mold resin 25 such as an epoxy resin. FIG. 19 is a sectional view of another semiconductor device using a lead frame. The feature here is that the bed portion 22 is used as the thin metal layer 10. The bed portion can be used as a thin metal layer having a shielding effect as long as it can be connected to the ground lead. As shown in the figure, the insulating film 2 made of polyimide is formed on the surface of the bed portion 22, and the inductance 6 is formed on the insulating film 2.
To form. The bed 22 and the ground lead 24 are connected to each other via the bonding wire 15.

The bed portion 221 or 222 can also mount the semiconductor substrate 1 having an inductance. The bed 22 and the semiconductor substrate 13 are connected by a bonding wire 15. When using a lead frame,
A TAB tape may be used to connect the semiconductor substrates mounted on the plurality of beds to each other. As described above, in the present invention, the characteristic impedance of 50Ω that prevents reflection of a signal entering the inductance is set to about ± 1 by bringing the thin metal layer close to the inductance coil.
It can be formed with a precision of 5% without variations. If the inductance material is a low resistance material such as Cu and the interlayer insulating film is a low dielectric constant material such as polyimide, the resistance component of the inductance is reduced by about 40%, and the capacitance component is about 40%. It is reduced by 50%. Further, it can be used in a frequency band of 100 MHz or more. Further, since a plurality of terminals are taken out from one end of the inductance coil, the degree of freedom in handling the semiconductor device is increased. Moreover, by forming a plurality of semiconductor substrates each including an inductance individually and adopting a multi-chip structure in which these semiconductor substrates are used as one semiconductor device, integration on a system scale becomes possible. At this time, since the inductance is formed on the silicon substrate, it can be dealt with in the conventional assembly process.

[0024]

As described above, the grounded thin metal layer formed on almost the entire surface of the substrate is brought close to the inductance, thereby
It is possible to obtain a semiconductor device having a high frequency characteristic in which an inductance is formed, which has a good characteristic even in a frequency band of MHz or more, and which has a high degree of freedom in design.

[Brief description of drawings]

FIG. 1 is a partial plan view of a semiconductor substrate according to a first embodiment of the present invention.

FIG. 2 is a partial cross-sectional view of a portion AA ′ in FIG.

FIG. 3 is a characteristic diagram showing frequency dependence of high frequency loss.

FIG. 4 is a partial cross-sectional view of the semiconductor substrate according to the first embodiment.

FIG. 5 is a partial cross-sectional view of the semiconductor substrate according to the first embodiment.

FIG. 6 is a partial cross-sectional view of the semiconductor substrate according to the first embodiment.

FIG. 7 is a plan view of a semiconductor substrate according to a second embodiment.

FIG. 8 is a plan view of a semiconductor substrate according to a second embodiment.

9 is a partial plan view of the semiconductor substrate shown in FIG.

10 is a partial plan view of the semiconductor substrate shown in FIG.

11 is a partial cross-sectional view of the semiconductor substrate shown in FIG.

FIG. 12 is a cross-sectional view of a semiconductor device of the present invention.

FIG. 13 is a cross-sectional view of a semiconductor device of the present invention.

FIG. 14 is a cross-sectional view of a semiconductor device of the present invention.

FIG. 15 is a plan view of a semiconductor device of the present invention.

16 is a cross-sectional view of the semiconductor device shown in FIG.

FIG. 17 is a plan view of a semiconductor device of the present invention.

FIG. 18 is a plan view of a semiconductor device of the present invention.

FIG. 19 is a cross-sectional view of a semiconductor device of the present invention.

FIG. 20 is a partial plan view of a semiconductor substrate used for a conventional semiconductor device.

21 is a partial cross-sectional view of the semiconductor substrate of FIG.

[Explanation of symbols]

1, 13 Semiconductor substrate 2, 4, 8 Insulating film 3, 31, 32 Connection wiring 5, 51, 52 Terminal 6 Inductance 7, 9, 91, 92, 101, 102, 121 Electrode pad 10 Metal thin layer 11 Capacitor electrode 12 Metal wiring layer 14 Lead wiring 15 Bonding wire 16 Polyimide film 17, 23 Lead 19, 191, 192 Device hole 21 Insulating film 22, 222, 222 Bed portion 24 Grounding lead 25 Mold resin 26 TAB tape 41, 81 Contact hole 103 Connection electrode 104 metal layer

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[Procedure amendment]

[Submission date] July 29, 1993

[Procedure Amendment 1]

[Document name to be corrected] Drawing

[Correction target item name] All drawings

[Correction method] Change

[Correction content]

[Figure 1]

[Fig. 2]

[Figure 5]

[Fig. 12]

FIG. 16

[Figure 3]

[Figure 4]

[Figure 6]

[Figure 7]

[Figure 8]

[Figure 9]

[Fig. 13]

[Figure 10]

FIG. 11

FIG. 14

FIG. 15

FIG. 17

FIG. 18

FIG. 19

FIG. 20

FIG. 21

Claims (7)

[Claims] 1. A semiconductor substrate, a first insulating film formed on a main surface of the semiconductor substrate, and a substantially entire surface of the main surface of the semiconductor substrate formed on the first insulating film. A grounded metal thin layer; a second insulating film formed on the main surface of the semiconductor substrate so as to cover the metal thin layer; and a second insulating film disposed on the metal thin layer. And an inductance formed on the second insulating film. 2. A semiconductor substrate, a first insulating film formed on a main surface of the semiconductor substrate, an inductance formed on the first insulating film, and an insulating film covering the inductance. A second insulating film formed on the first insulating film; and a grounded metal thin layer formed on the second insulating film and covering substantially the entire main surface of the semiconductor substrate. A semiconductor device characterized in that. 3. The metal layer, which is connected to the thin metal layer by a connection wiring, is further formed on the same plane as the inductance and adjacent thereto. The semiconductor device according to. 4. A metal film is provided on an insulating film on the thin metal layer, and a capacitor having the metal film as a first electrode and the thin metal layer as a second electrode is formed. The semiconductor device according to claim 1. 5. The inductor according to claim 1, wherein the inductance includes terminals formed at both ends thereof and at least one terminal formed in the middle thereof. Semiconductor device. 6. A semiconductor substrate, an insulating film having a device hole on which the semiconductor substrate is mounted, a first main surface of the insulating film, and being electrically connected to the semiconductor substrate. Inductance and a plurality of leads formed on the first main surface of the insulating film and having one end connected to the connection electrode of the semiconductor substrate.
And a grounded metal thin film facing substantially the entire second main surface of the insulating film and joined thereto. 7. At least one semiconductor substrate, a lead frame having two or more substrate mounting portions formed thereon, and an insulating film formed on substantially the entire surface of at least one of the substrate mounting portions. And an inductance formed on the insulating film, wherein the semiconductor substrate is not placed on the substrate placing part on which the inductance is formed, and the substrate placing part is grounded. And the semiconductor substrate is mounted on each of the remaining substrate mounting portions.