JPH06112406A - Semiconductor integrated circuit - Google Patents

Abstract

PURPOSE:To provide a semiconductor integrated circuit in which the performance degradation generating when capacitive coupling is conducted is prevented, and also to avoid an increase in cost. CONSTITUTION:The first layer wiring 12 which is formed on the semiconductor substrate 11 having a semiconductor element and electrically connected to the semiconductor element, an insulating film 13, to be used for formation of a capacitor of the prescribed thickness, which is formed on the above-mentioned first layer wiring, and the second layer wiring 14, to be used for a bonding pad, formed on the insulating film, are provided on the title semiconductor integrated circuit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit, and more particularly to a semiconductor integrated circuit capable of capacitive coupling with the outside.

[0002]

2. Description of the Related Art In a conventional integrated circuit, when capacitive coupling is performed with the outside, a capacitor 2 is externally attached to the input / output portion of the integrated circuit 1 by soldering as shown in FIG.

[0003]

However, when the capacitor 2 is externally attached to the integrated circuit 1 as described above,
(1) The number of parts increases, (2) the manufacturing process increases,
(3) The parasitic inductance increases due to the leads of the capacitor 2 and the like, and (4) the occupied area of the integrated circuit 1 + capacitor 2 increases, which results in lower performance and higher cost.

The present invention has been made in order to solve the above-mentioned conventional problems, and an object thereof is a semiconductor that prevents performance deterioration and cost increase that occur when capacitive coupling with the outside is performed. It is to provide an integrated circuit.

[0005]

In order to achieve the above object, a feature of the present invention is that a first insulating film is formed on a semi-insulating substrate having a semiconductor element and is electrically connected to the semiconductor element.
A layer wiring, an insulating film having a predetermined film thickness for forming a capacitance formed on the first layer wiring, and a second layer wiring for a bonding pad formed on the insulating film.

The insulating film for forming the capacitance may be formed in a process different from that of the other insulating film formed on the semi-insulating substrate, and its film thickness or material may be different from that of the other insulating film. Good.

An insulating film may be formed between the semi-insulating substrate and the first layer wiring.

[0008]

According to the above-described structure, the first layer wiring, the insulating film for forming the capacitance, and the second layer wiring used as the bonding pad form a capacitance, and the capacitor is externally attached as in the conventional case. It becomes possible to capacitively couple with an external circuit without the need.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the present invention will be described below with reference to the drawings. FIG. 1 is a sectional configuration diagram of an input / output unit of a semiconductor integrated circuit embodying the present invention.

As shown in FIG. 1, on a semiconductor substrate 11 of an input / output portion of this semiconductor integrated circuit, a first layer wiring 12 such as aluminum extending inside the semiconductor integrated circuit is formed, and further, the first layer wiring 12 is formed. On the surface of the first layer wiring 12, a second layer wiring 14 which is a bonding pad is formed via an insulating film (SiO2) 13 having a predetermined thickness. A capacitor is formed by the first and second layer wirings 12 and 14 and the insulating film 13, and this semiconductor integrated circuit can be capacitively coupled to the outside.

FIG. 2 is a sectional view showing the case where the semiconductor integrated circuit of FIG. 1 is mounted in a package, and FIG. 3 is a partial plan view of this case.

The above semiconductor integrated circuit is housed in the package, and the input / output section of FIG. 1 is mounted on the bottom surface 21 of the package shown in FIG. The first layer wiring 12 and the insulating film 13 are formed on the semiconductor substrate 11 in the input / output section.
The protective film 22 for protecting the second layer wiring 14 is formed so as to cover the end faces of the first layer wiring 12, the insulating film 13, and the second layer wiring 14.

Further, the second layer wiring 14 of the bonding pad and the internal lead 24 of the package are electrically connected by the bonding wire 23, and the internal lead 2
4 is connected to the external lead 25. Since the capacitor is housed inside the IC chip as described above, the semiconductor integrated circuit of this embodiment is different from the conventional external circuit connected to the external lead 25 without externally attaching the capacitor. Capacitive coupling is possible.

The present invention is not limited to the above embodiment,
Various modifications are possible. The following are examples of such modifications.

(1) The insulating film 13 may be formed in the same step as the interlayer insulating film other than directly below the second layer wiring 14, or may be formed in a different step to change the film thickness, or by a different material. It is also possible to change the shape.

(2) In the above embodiment, the first layer wiring 12 is formed directly on the semiconductor substrate 11 as shown in FIG. 1, but the insulating film 30 is formed on the semiconductor substrate 11 as shown in FIG. 4, for example. The first layer wiring 12 may be formed via the.

[0017]

As described above in detail, in the present invention, the capacitor is formed by the first layer wiring, the insulating film and the second layer wiring, so that the capacitor is externally mounted as in the conventional case. Without the need for capacitive coupling with the outside. As a result, the number of parts is reduced, and the step for externally attaching the capacitor can be omitted, resulting in a cost reduction compared to the conventional case. Furthermore, since it is possible to prevent an increase in parasitic inductance, it is possible to prevent performance deterioration.

[Brief description of drawings]

FIG. 1 is a cross-sectional configuration diagram of an input / output unit of a semiconductor integrated circuit embodying the present invention.

FIG. 2 is a cross-sectional configuration diagram when the semiconductor integrated circuit of FIG. 1 is mounted in a package.

FIG. 3 is a partial plan view of the semiconductor integrated circuit of FIG. 1 mounted on a package.

FIG. 4 is a diagram showing a modification of the above embodiment.

FIG. 5 is a diagram showing external capacitive coupling in a conventional semiconductor integrated circuit.

[Explanation of symbols]

 11 semi-insulating substrate 12 first layer wiring 13 and 30 insulating film 14 second layer wiring

Claims (3)

[Claims] 1. A first layer wiring formed on a semi-insulating substrate having a semiconductor element and electrically connected to the semiconductor element, and a capacitor having a predetermined thickness formed on the first layer wiring. Insulation film and a second bonding pad formed on the insulation film
A semiconductor integrated circuit comprising: a layer wiring. 2. The insulating film for forming the capacitance is formed in a step different from that of the other insulating film formed on the semi-insulating substrate, and the film thickness or material thereof is different from the other insulating film. The semiconductor integrated circuit according to claim 1, wherein: 3. The semiconductor integrated circuit according to claim 1, wherein an insulating film is formed between the semi-insulating substrate and the first layer wiring.