JPH08195443A - Semiconductor device and its manufacture - Google Patents

Abstract

PURPOSE: To obtain a semiconductor device in which a large current generated by static electricity or the like is made to escape to a semiconductor substrate by a method wherein an N-type MOS transistor and a P-type MOS transistor as protection elements are formed on a support substrate. CONSTITUTION: An insulating film 12 is formed on a P-type semiconductor substrate 10, and a semiconductor layer 14 is formed on the insulating film 12. Semiconductor elements as an N-type MOS transistor 18 and a P-type transistor 20 are formed so as to be separated by an element isolation film 16. On the other hand, an N-type MOS transistor 22 and a P-type MOS transistor 24 are formed on the P-type semiconductor substrate 10 other than a region for the elements, and a protection element is constituted. Then, an interconnection layer 38 is formed on them via an interlayer insulating film 36, and drain diffused layers for the N-type MOS transistor 22 and the P-type MOS transistor are connected to an input end. Consequently, an overvoltage can be made to escape to the substrate 10.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and its manufacturing technology, and more particularly to SOI (Silicon On Insulator).
Provided are a semiconductor device and a method for manufacturing the same, which improves the protection performance of a semiconductor device having a structure.

[0002]

2. Description of the Related Art The SOI technique is a technique for forming an element on a single crystal silicon thin film formed on an insulating substrate or an insulating film. Since the SOI structure enables complete element isolation, parasitic capacitance such as diffusion layer capacitance can be significantly reduced, and the operating speed of a semiconductor device can be improved. Is one.

However, when a large current flows into the semiconductor device due to discharge of static electricity charged on the human body (hereinafter referred to as ESD) or the like, in a normal semiconductor device formed on bulk silicon, the current is directed toward the silicon substrate. While there is a path for escape, the SOI structure has an insulating film formed under the element, so that the current can only escape in the lateral direction, and there is a problem that the element is easily destroyed. Therefore, in a semiconductor device having an SOI structure, a technique of protecting an element from ESD is particularly important.

Incorporating a protective element into a semiconductor device is
It is generally used as a method of protecting a semiconductor element from ESD. Typical protection elements include a resistance-type protection element that reduces an applied overvoltage and a discharge-type protection element that releases the overvoltage to a power supply line or a reference potential line. Hereinafter, the description will be limited to the discharge type protection element. Usually, the discharge type protection element is formed by a diode, a MOS transistor or the like, and emits an excessive current through these elements. At this time, the discharge effect increases as the junction area of the diffusion layer increases, so that it is necessary to form an element having a wide junction area in order to enhance the discharge effect.

Further, since the protective element itself is required to be less likely to be broken by ESD, it is desirable to relax the internal electric field at the junction to make the element less likely to be destroyed. Therefore, for example, in a protection element using a MOS transistor, by making the source / drain diffusion layer deeper than that of the internal integrated circuit element, the impurity concentration profile of the diffusion layer has a gradient, and the electric field concentration at the junction is concentrated. Is being suppressed.

Inclination of the impurity concentration profile of the diffusion layer in this way has the effect of increasing the junction area and the punch-through current between the source and drain, in addition to relaxing the internal electric field, so that the discharge capability is improved. You can also plan. On the other hand, in the SOI structure, a single crystal silicon thin film (hereinafter referred to as SO
It is desirable to form a protective element on the I layer). This is because it is excellent in compatibility with the manufacturing process of a semiconductor device using an SOI substrate. However, in order to improve the device characteristics, it is desirable to reduce the capacitance of the diffusion layer by making the SOI layer thin so that the lower surface of the diffusion layer is in contact with the insulating film, and the SOI layer is thickened to improve the discharge effect. It conflicts with the requirements for devices.

Therefore, a method has been proposed in which the protective element is not formed in the SOI layer but is formed in the supporting silicon substrate. For example, in the semiconductor device described in JP-A-4-345064, as shown in FIG. 16A, an N-type MOS transistor 22 is formed on a supporting silicon substrate 10 and used as a protection element. That is, SO
A semiconductor integrated circuit element 68 is formed on the I layer 14, and an N-type MOS transistor 22 for protecting the semiconductor integrated circuit element 68 is formed on the supporting silicon substrate 10. The gate electrode 70 of the N-type MOS transistor 22 is S
The gate insulating film 72 is formed of the OI layer 14, and the gate insulating film 72 is formed of the insulating film 12 between the supporting silicon substrate 10 and the SOI layer 14. The operation of the protection element of FIG. This will be described using an equivalent circuit. As shown in the figure, the drain and gate of the N-type MOS transistor 22 which is a protection element are connected to the input / output pad 40. Therefore, when a negative ESD surge voltage is applied to the input / output pad 40, the drain diffusion layer becomes a forward bias state. As a result, a large current generated by static electricity can be released to the supporting silicon substrate 10, so that it is possible to suppress the influence on the semiconductor integrated circuit element.

Further, since the protective element is formed on the supporting silicon substrate 10, the junction area of the diffusion layer can be increased. Further, since the protection element is formed at the same time as the N-type MOS transistor of the semiconductor integrated circuit element, the SO
It is also excellent in compatibility with the manufacturing process of a semiconductor device using an I substrate.

[0009]

However, in the above conventional semiconductor device, since one N-type MOS transistor and one protection element are formed, an ESD surge voltage such that a reverse bias is applied to the pn junction of the protection element is generated. When applied, the protective element is discharged only by the junction breakdown, so that there is a problem that sufficient protective ability cannot be obtained.

Further, there is a problem that the protection circuit can be provided only on one of the power supply line and the reference potential line. In addition, when a semiconductor device is manufactured using an SOI substrate, a well is not usually formed.
As shown in FIG. 6, when an N well 74 is formed on a supporting silicon substrate and a protection circuit is to be formed by the N type MOS transistor 22 and the P type MOS transistor 24, a well forming step must be added separately. There was a problem that it had to be.

Further, in the CMOS integrated circuit, since parasitic pn junctions are formed on the power supply line and the reference potential line of the output buffer, when a reverse ESD surge voltage is applied to the output pad, Before the protective element breaks down due to the reverse voltage, there is a problem in that the current may concentrate on any of the parasitic pn junctions that are biased in the forward direction, resulting in junction breakdown.

An object of the present invention is to provide a semiconductor device using an SOI substrate, which has an excellent discharge capability with respect to positive and negative polarity ESD surge voltages, and the number of manufacturing steps of such a semiconductor device. It is an object of the present invention to provide a method for manufacturing a semiconductor device that can be manufactured without increasing the number.

[0013]

The above object is to provide a P-type semiconductor substrate, an insulating film formed on the P-type semiconductor substrate, a semiconductor layer formed on the insulating film, and the semiconductor layer. In a semiconductor device having a formed semiconductor element and a protection element that protects the semiconductor element, the protection element includes a first N-type source diffusion layer and a first N-type source formed on the semiconductor substrate. A source region provided inside the diffusion layer, the source region including a second N-type source diffusion layer shallower than the first N-type source diffusion layer; and a first N-type drain diffusion layer formed on the semiconductor substrate. A drain region formed inside the first N-type drain diffusion layer and formed of a second N-type drain diffusion layer shallower than the first N-type drain diffusion layer; and the source region and the drain region. Said semiconductor substrate between An N-type MOS transistor having a gate insulating film made of the insulating film and a gate electrode made of the semiconductor layer on the gate insulating film; and an N-type diffusion layer and an N-type diffusion layer formed on the semiconductor substrate. A source region formed inside of the P-type source diffusion layer shallower than the N-type diffusion layer, and a drain region formed inside the N-type diffusion layer formed of a P-type drain diffusion layer shallower than the N-type diffusion layer. A P-type MOS transistor having a gate insulating film made of the insulating film on the semiconductor substrate between the source region and the drain region and a gate electrode made of the semiconductor layer on the gate insulating film. This is achieved by a semiconductor device characterized by the above.

In the above semiconductor device, the P
Of a depletion layer formed between the N-type diffusion layer and the P-type source diffusion layer or the P-type drain diffusion layer when a power source voltage is applied to the P-type source diffusion layer or the P-type drain diffusion layer. The depth of the N-type diffusion layer and the P-type source so that the width is smaller than the difference between the depth of the N-type diffusion layer and the depth of the P-type source diffusion layer or the P-type drain diffusion layer. It is desirable that the depth of the diffusion layer or the P-type drain diffusion layer be controlled.

In the above semiconductor device, the N
The depth of the type diffusion layer is preferably at least 100 nm or more deeper than the depth of the P type source diffusion layer or the P type drain diffusion layer. A P-type semiconductor substrate, an insulating film formed on the P-type semiconductor substrate, a semiconductor layer formed on the insulating film, a semiconductor element formed on the semiconductor layer, and the semiconductor element In a semiconductor device having a protection element for protection, the protection element is provided inside a first N-type cathode diffusion layer formed on the semiconductor substrate and the first N-type cathode diffusion layer. N
Type cathode diffusion layer, a first diode having a cathode formed of a second N type cathode diffusion layer shallower than the type cathode diffusion layer, an anode formed of the semiconductor substrate, and a third N type cathode diffusion formed on the semiconductor substrate. A second diode having a cathode made of a layer and an anode provided inside the third N-type cathode diffusion layer and having a P-type anode diffusion layer shallower than the third N-type cathode diffusion layer. It is also achieved by a semiconductor device characterized by having.

In the above semiconductor device, the P
When a power supply voltage is applied to the anode diffusion layer
The width of the depletion layer formed between the N-type cathode diffusion layer and the P-type anode diffusion layer is equal to the depth of the third N-type cathode diffusion layer and the depth of the P-type anode diffusion layer. It is desirable that the depth of the third N-type cathode diffusion layer and the depth of the P-type anode diffusion layer are controlled so as to be smaller than the difference.

In the above semiconductor device, the depth of the second N type diffusion layer is preferably at least 100 nm or more deeper than the depth of the first P type diffusion layer. In the above semiconductor device, the semiconductor layer preferably has a film thickness of 300 nm or less. A P-type semiconductor substrate, an insulating film formed on the P-type semiconductor substrate, a semiconductor layer formed on the insulating film, a semiconductor element formed on the semiconductor layer, and the semiconductor element In a method of manufacturing a semiconductor device having a protective element for protection, the insulating layer and the semiconductor layer are patterned to form the semiconductor layer in a first region forming an N-type MOS transistor forming the protective element. First
P-type M that forms the gate electrode of the
A gate electrode forming step of forming a second gate electrode made of the semiconductor layer in a second region for forming an OS transistor, and the first gate electrode and the second gate electrode as a mask, A first N-type impurity introduction step of introducing N-type impurities into the first region and the second region;
The semiconductor substrate introduced with the N-type impurities is thermally oxidized to form a gate oxide film in the semiconductor element region, and a first N-type source diffusion layer and a first N-type are provided in the first region. Forming a drain diffusion layer in the second region to form an N-type diffusion layer, and introducing a P-type impurity into the second region by using the second gate electrode as a mask to form the N-type diffusion layer. Forming a P-type source diffusion layer and a P-type drain diffusion layer in the diffusion layer, and at the same time forming a P-type region of the semiconductor element region;
An N-type impurity is introduced into the first region by using the gate electrode as a mask, and a second N-type impurity is introduced into the first N-type source diffusion layer.
A N-type impurity diffusion step of forming a N-type source diffusion layer and a second N-type drain diffusion layer in the first N-type drain diffusion layer, and at the same time forming an N-type region of the semiconductor element region. A P-type MOS transistor having the second gate electrode, the P-type source diffusion layer, and the P-type drain diffusion layer, the first gate electrode, the first N-type source diffusion layer, and the second Manufacturing a semiconductor device comprising: an N-type source diffusion layer; an N-type MOS transistor having the first N-type drain diffusion layer and the second N-type drain diffusion layer. It is also achieved by the method.

In the method of manufacturing a semiconductor device described above, in the first N-type impurity introduction step, the N-type impurity is introduced when a power supply voltage is applied to the P-type source diffusion layer or the P-type drain diffusion layer. The width of the depletion layer formed between the diffusion layer and the P-type source diffusion layer or the P-type drain diffusion layer is the depth of the N-type diffusion layer and the P-type source diffusion layer or the P-type drain. It is desirable to introduce an N-type impurity into the first region and the second region so that the difference becomes smaller than the difference in depth of the diffusion layer.

Further, a P-type semiconductor substrate, an insulating film formed on the P-type semiconductor substrate, a semiconductor layer formed on the insulating film, a semiconductor element formed on the semiconductor layer, In a method of manufacturing a semiconductor device having a protective element for protecting a semiconductor element, the insulating film and the semiconductor layer are patterned to form a first diode forming the protective element, and the protective element. An opening forming step of forming an opening reaching the semiconductor substrate in a second region forming the second diode forming the second diode, and introducing an N-type impurity into the first region and the second region. A first N-type impurity introduction step and thermal oxidation of the semiconductor substrate into which the N-type impurity has been introduced to form a gate oxide film in the semiconductor element region, and a first N-type impurity in the first region. Type caustic A diffusion layer, a gate oxide film forming step of forming a second N-type cathode diffusion layer in the second region, and introducing a P-type impurity into the second region to form the third N-type cathode diffusion layer. A P-type anode diffusion layer is formed therein, and at the same time, a P-type region of the semiconductor element region is formed.
And a step of introducing an N-type impurity into the first region to form a second N-type cathode diffusion layer in the first N-type cathode diffusion layer, and at the same time to form an N-type impurity in the semiconductor device region. An N-type impurity introducing step of forming a region, the first N-type cathode diffusion layer and a second N-type cathode diffusion layer, and an anode made of the semiconductor substrate. And a second diode having a cathode made of the third N-type cathode diffusion layer and an anode made of the P-type anode diffusion layer formed on the semiconductor substrate. It is also achieved by a method of manufacturing a characteristic semiconductor device.

In the method of manufacturing a semiconductor device described above, in the first N-type impurity introduction step, when a power supply voltage is applied to the P-type anode diffusion layer, the third N-type cathode diffusion layer is formed. The width of the depletion layer formed between the P-type anode diffusion layer and the P-type anode diffusion layer is smaller than the difference between the depth of the third N-type cathode diffusion layer and the depth of the P-type anode diffusion layer. It is desirable to introduce N-type impurities into the first region and the second region.

[0021]

According to the present invention, in a semiconductor device having an SOI structure, an N-type MOS transistor and a P-type MOS transistor are formed as protective elements on a supporting substrate, so that a large current generated by static electricity or the like is directed toward the semiconductor substrate. Since it can be released, it is possible to suppress deterioration or destruction of the semiconductor device due to the current.

Further, when a negative ESD surge voltage is applied to the input / output pad, the drain diffusion layer of the N-type MOS transistor is in a forward biased state, so that an excessive voltage can be released to the supporting substrate, Positive ESD on the pad
When a surge voltage is applied, the drain diffusion layer of the P-type MOS transistor is in a forward bias state, so that an excessive voltage can be released to the power supply line.

The source of the N-type MOS transistor /
Since the drain diffusion layer is formed by the deep N-type diffusion layer and the shallow N-type diffusion layer, there is no sharp impurity concentration gradient, and discharge is performed by the PN junction formed by the source / drain diffusion layer and the supporting substrate. It is possible to avoid the concentration of the electric field at the junction when being exposed. In addition, P-type MOS
When a power supply voltage is applied to the source / drain diffusion layer of the transistor, the width of the depletion layer formed between the N-type diffusion layer directly below and the P-type source / drain diffusion layer is equal to the depth of the N-type diffusion layer. And the depth difference between the P-type source / drain diffusion layer and the P-type source / drain diffusion layer are smaller than each other. Can be prevented.

By making the depth of the N-type diffusion layer deeper than the depth of the P-type diffusion layer by at least 100 nm or more, the effect is more remarkable. Further, in a semiconductor device having an SOI structure, by forming two diodes as protection elements on a supporting substrate, a large current generated by static electricity or the like can be released in the direction of the semiconductor substrate. It is possible to suppress deterioration and destruction of the.

Further, when a negative ESD surge voltage is applied to the input / output pad, one diode is in a forward bias state, so that an excessive voltage can be released to the supporting substrate. Further, when a positive ESD surge voltage is applied to the input / output pad, the other diode is in a forward bias state, so that an excessive voltage can be released to the power supply line.

Further, since the cathode diffusion layer of one diode is formed by the deep N-type diffusion layer and the shallow N-type diffusion layer, there is no sharp impurity concentration gradient, and the cathode diffusion layer and the supporting substrate are formed. It is possible to avoid concentration of an electric field at the junction when discharging is performed by the PN junction. In addition, when a power supply voltage is applied to the anode diffusion layer, the width of the depletion layer formed between the N-type diffusion layer immediately below and the anode diffusion layer is equal to the depth of the N-type diffusion layer and the anode diffusion layer. Since it is smaller than the depth difference,
The depletion layer formed by the N-type diffusion layer and the anode diffusion layer can prevent a leak current from flowing in the substrate direction.

Further, by making the depth of the N-type diffusion layer deeper than the depth of the P-type diffusion layer by at least 100 nm or more, the effect is more remarkable. Further, since the protective element is formed in the supporting substrate in order to enhance the discharge effect of the protective element, it is difficult to obtain a sufficient discharge effect at about 300n.
Even in a semiconductor device formed on an SOI layer of m or less,
The discharge effect can be enhanced.

Further, since the N-type diffusion layer is formed before the gate oxidation step, it diffuses deeply into the supporting substrate due to the heat treatment for gate oxidation. As a result, the N-type diffusion layer becomes P-type M
It can be used as a substitute well for forming an OS transistor. Further, since the substitute well thus formed does not require a long-time heat treatment for forming the well, the substitute well is formed without significantly increasing the manufacturing process or processing time of the semiconductor device using the SOI substrate. be able to.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS A semiconductor device and a method of manufacturing the same according to a first embodiment of the present invention will be described with reference to FIGS. FIG.
2 is a diagram showing the structure of the semiconductor device according to the present embodiment, FIG. 2 is a circuit diagram for measurement used in testing the semiconductor device according to the present embodiment, and FIGS. It is a figure explaining.

The semiconductor device according to this embodiment is shown in FIG.
As shown in, N-type MOS transistor and P-type MOS
It has a protective element composed of a transistor. That is, the N-type MOS transistor and the P-type MOS transistor are connected to the wiring connecting the input / output pad and the semiconductor integrated circuit element. The N-type MOS transistor is provided between the reference potential line and the wiring, the source electrode and the drain electrode are connected to the reference potential line and the wiring, respectively, and the gate electrode is connected to the reference potential line. The P-type MOS transistor is provided between the power supply line and the wiring, the source electrode and the drain electrode are connected to the wiring and the power supply line, respectively, and the gate electrode is connected to the power supply line.

A cross section of the semiconductor device in the region where the protective element is formed is shown in FIG. The support substrate 10 is, for example, p
An insulating film 12 made of, for example, a silicon oxide film is formed on the upper surface of the type silicon substrate. An SOI layer 14 is formed on the insulating film 12. SO
In the I layer 14, an N-type MOS transistor 18 and a P-type MOS transistor 20 which form an integrated circuit are formed separately by an element isolation film 16.

An N-type MOS transistor 22 and a P-type MOS transistor 24 having an insulating film 12 as a gate oxide film and an SOI layer as a gate electrode are formed on the supporting substrate 10 outside the integrated circuit element region. This N-type MO
The S transistor 22 and the P-type MOS transistor 24 form a protection element. N-type MOS transistor 22
The source / drain diffusion layer is formed by the deep N-type diffusion layer 26 and the shallow N-type diffusion layer 28 formed in the deep diffusion layer 26. The P-type MOS transistor 24 is
N-type diffusion layer 30 formed simultaneously with deep N-type diffusion layer 26
A P-type diffusion layer 32 formed inside and formed in the N-type diffusion layer 30 constitutes a source / drain region. Furthermore,
A shallow N-type layer 34 is formed in the N-type diffusion layer 30, and a contact region for drawing out wiring from the N-type diffusion layer 30 is provided.

A wiring layer 38 is formed on the upper layer of these transistors with an interlayer insulating film 36 interposed therebetween. Next, the operation of the semiconductor device according to the present embodiment will be described. As illustrated, the input / output pad 40 is connected to the drain diffusion layer of the N-type MOS transistor 22 and the drain diffusion layer of the P-type MOS transistor.

Therefore, when a negative ESD surge voltage is applied to the input / output pad, the N-type MOS transistor 22
Since the drain diffusion layer of 1 is in a forward bias state, an excessive voltage can be released to the supporting substrate 10. On the other hand, when a positive ESD surge voltage is applied to the I / O pad, P
Since the drain diffusion layer of the MOS transistor 24 is in the forward bias state, an excessive voltage can be released to the power supply line.

Further, since the source / drain diffusion layer of the N-type MOS transistor 22 is formed by the deep N-type diffusion layer 26 and the shallow N-type diffusion layer 28, there is no abrupt impurity concentration gradient and the source / drain diffusion is not performed. Layer and supporting substrate 10
It is possible to avoid concentration of an electric field at the junction when discharging is performed by the PN junction formed by.
The depth of the N-type diffusion layer 30 is such that the width of the depletion layer formed by the N-type diffusion layer 30 and the P-type diffusion layer 32 when the power supply voltage is applied to the P-type diffusion layer 32 is the N-type diffusion layer 30. Is preferably smaller than the difference in the junction depth between the P type diffusion layer 32 and the P type diffusion layer 32.
This is because when the power supply voltage is applied to the P-type diffusion layer 32, N
This is because the depletion layer formed by the type diffusion layer 30 and the P type diffusion layer 32 pinches off the N type diffusion layer 30 and causes a leak current to always flow in the substrate direction.

Therefore, the depth of the N type diffusion layer 30 is preferably deeper than the P type diffusion layer 32 by at least 100 nm or more. The above protection circuit was tested by the measuring circuit shown in FIG. As shown in the figure, the capacitor 62 was charged with the variable voltage 60, and then the high voltage discharged from the capacitor 62 was applied to the semiconductor device to measure the discharge effect of the protective element.

When a test is conducted with the measuring device shown in the figure, it is generally said that a withstand voltage of 300 V or higher is sufficient. It was found that the semiconductor device according to this example has a withstand voltage of 300 V or more with respect to the applied voltage in both the positive and negative directions. The conventional semiconductor device has a withstand voltage of 300 V or more with respect to an applied voltage in the negative direction, but can obtain only a withstand voltage of about 80 V in the positive direction.

Next, a method of manufacturing the semiconductor device according to this embodiment will be described. First, the insulating film 1 is formed on the P-type support substrate 10.
An SOI substrate having an SOI layer 14 which is a single crystal silicon layer is formed via the substrate 2. For example, SIMOX for forming a buried silicon oxide film layer by oxygen ion implantation
Such an SOI substrate is formed by using the (Separation by IMplanted OXygen) method (FIG. 3A).

Next, although not shown, the SOI in the region where the P-type MOS transistor 20 of the integrated circuit element is to be formed.
Phosphorus, for example, is introduced into the layer as an n-type impurity. After that, the SOI layer 14 and the insulating film 1 in the region where the protective element is formed
2 is removed using photolithography technique. Since the SOI layer 14 is used for the gate electrode of the protection element, the SOI layer is left in the gate region of the protection element (FIG. 3B).

Next, an oxide film 42, which will be a pad for forming an element isolation film, is formed by thermal oxidation, and a silicon nitride film 44, which will be an oxidation mask, is formed thereon by chemical vapor deposition (C).
It is deposited by the VD method (FIG. 4A). Then, the silicon nitride film 44 is processed into a pattern of an element isolation film by a photolithography technique (FIG. 4B).

After that, thermal oxidation is performed using the silicon nitride film 44 as a mask to form the element isolation film 16. As a result, the element isolation film 16 is formed on the support substrate 10 in the area where the protective element is formed and in the SOI layer area where the integrated circuit element is formed. After the element isolation film is formed in this manner, the silicon nitride film 44 is removed (FIG. 5A). Then, in the region where the deep N-type diffusion layer 26 and the N-type diffusion layer 30 are formed,
For example, phosphorus ions are introduced by the ion implantation method (FIG. 5).
(B)).

Then, the gate oxide film 46 of the integrated circuit element is formed.
Are formed by thermal oxidation, and a polysilicon film 48 to be a gate electrode is deposited by the CVD method. By the heat treatment for forming the gate oxide film, the impurities introduced to form the deep N-type diffusion layer 26 and the N-type diffusion layer 30 are diffused and spread deep into the support substrate 10. At this time, P type M
The impurities introduced into the region forming the OS transistor 24 are connected to each other by thermal diffusion, and the N-type diffusion layer 30 is formed. On the other hand, the impurities introduced into the region forming the N-type MOS transistor 22 are not connected to each other even after thermal diffusion, and the deep diffusion layer 26 is formed (FIG. 6A).

At an acceleration energy of 60 keV, 5E
As a result of performing a simulation in the case of implanting 13 cm ⁻² of phosphorus ions, the depth of the N-type diffusion layer 30 finally formed was about 3.7 μm. Then, the polysilicon film 44 is processed by the photolithography technique to form the gate electrode 48 of the integrated circuit element (FIG. 6).
(B)).

Next, a P-type impurity is introduced into the formation region of the P-type MOS transistor to form a source / drain diffusion layer. As a result, the P-type diffusion layer 32 which is the source / drain diffusion layer of the protection element and the source / drain diffusion layer 50 of the integrated circuit element are simultaneously formed (FIG. 7A). In addition, BF ₂ ions are accelerated to 5E at an acceleration energy of 20 keV.
As a result of performing a simulation for the case of implanting at 15 cm ⁻² , the depth of the P-type diffusion layer 32 finally formed was about 0.2 μm. Therefore, the N-type diffusion layer 30
Is sufficiently deeper than that of the P-type diffusion layer, and even when a power supply voltage is applied to the P-type diffusion layer 32, the depletion layer formed by the N-type diffusion layer 30 and the P-type diffusion layer 32 causes , N-type diffusion layer 30 is not pinched off, and leak current does not always flow in the substrate direction.

Subsequently, N-type impurities are introduced into the formation region of the N-type MOS transistor to form source / drain diffusion layers. As a result, the shallow N-type diffusion layer 28 which is the source / drain diffusion layer of the protection element and the source / drain diffusion layer 52 of the integrated circuit element are simultaneously formed. Furthermore, a shallow N-type layer 34 is also formed in the N-type diffusion layer 30 (FIG. 7).
(B)).

After that, the interlayer insulating film 36 is deposited by the CVD method to open the contact hole 56 (FIG. 8).
(A)). Next, for example, tungsten is deposited as a metal film to be the wiring layer 38, and the wiring layer 38 is formed by processing using a photolithography technique (FIG. 8B). In this way, the semiconductor device shown in FIG. 1 can be manufactured.

As described above, according to this embodiment, in the semiconductor device having the SOI structure, the N-type MOS transistor 22 and the P-type MOS transistor 24 are formed as the protection elements on the supporting substrate, and the large current generated by static electricity or the like is generated. By allowing the current to escape, deterioration or destruction of the semiconductor device due to the current can be suppressed. In addition, when a negative ESD surge voltage is applied to the input / output pad, the N-type M
Since the drain diffusion layer of the OS transistor 22 is in a forward bias state, an excessive voltage can be released to the supporting substrate 10, and the drain of the P-type MOS transistor 24 when a positive ESD surge voltage is applied to the input / output pad. Since the diffusion layer is in the forward bias state, the excessive voltage can be released to the power supply line.

Further, since the source / drain diffusion layer of the N-type MOS transistor 22 is formed by the deep N-type diffusion layer 26 and the shallow N-type diffusion layer 28, there is no abrupt impurity concentration gradient, and the source / drain diffusion is not performed. Layer and supporting substrate 10
It is possible to avoid concentration of an electric field at the junction when discharging is performed by the PN junction formed by.
Further, since the N-type diffusion layer 30 is formed before the gate oxidation step, it diffuses deeply into the support substrate 10 with the heat treatment for gate oxidation. As a result, the N-type diffusion layer 30 becomes a P-type M
It can be used as a substitute well for forming the OS transistor 24.

Since the substitute well thus formed does not require a long-time heat treatment for forming the well, the manufacturing process and processing time of the semiconductor device using the SOI substrate can be significantly increased. Can be formed without. A semiconductor device and a method of manufacturing the same according to the second embodiment of the present invention will be described with reference to FIGS.

FIG. 9 is a diagram showing the structure of the semiconductor device according to the present embodiment, and FIGS. 10 to 15 are diagrams for explaining the method of manufacturing the semiconductor device according to the present embodiment. The semiconductor device according to the present embodiment has a protection element composed of two diodes, as shown in FIG. That is, an input / output pad,
Two diodes 64 and 66 are connected to the wiring that connects the semiconductor integrated circuit element. Diode 64
Is provided between the reference potential line and the wiring, and the cathode and the anode are connected to the reference potential line and the wiring, respectively. The diode 66 is provided between the power supply line and the wiring, and the cathode and the anode are connected to the wiring and the power supply line, respectively.

A cross section of the semiconductor device in the region where the protective element is formed is shown in FIG. The support substrate 10 is, for example, p
An insulating film 12 made of, for example, a silicon oxide film is formed on the upper surface of the type silicon substrate. An SOI layer 14 is formed on the insulating film 12. SO
In the I layer 14, an N-type MOS transistor 18 and a P-type MOS transistor 20 which form an integrated circuit are formed separately by an element isolation film 16.

On the support substrate 10 outside the integrated circuit element region, a diode having the deep N-type diffusion layer 26 and the shallow N-type diffusion layer 28 formed in the deep diffusion layer 26 as the cathode and the support substrate 10 as the anode. 66 is formed. Further, a diode 64 having an N-type diffusion layer 30 formed simultaneously with the deep N-type diffusion layer 26 as a cathode and a P-type diffusion layer 32 formed in the N-type diffusion layer 30 as an anode is formed.

An interlayer insulating film 36 is formed on the upper layer of these elements.
The wiring layer 38 is formed via the. Next, the operation of the semiconductor device according to the present embodiment will be described. As shown
The terminals of two diodes 64 and 66 having different polarities are connected to the input / output pad 40.

Therefore, when a negative ESD surge voltage is applied to the input / output pad, the diode 66 is in a forward bias state, so that an excessive voltage can be released to the support substrate 10. On the other hand, when a positive ESD surge voltage is applied to the input / output pad, the diode 64 is in a forward bias state, so that an excessive voltage can be released to the power supply line.

Further, since the cathode diffusion layer of the diode 66 is formed by the deep N-type diffusion layer 26 and the shallow N-type diffusion layer 28, there is no steep impurity concentration gradient, and the cathode diffusion layer and the supporting substrate 10 form the cathode diffusion layer. It is possible to avoid concentration of an electric field at the junction when discharging is performed by the formed PN junction. The depth of the N-type diffusion layer 30 is determined by applying a power supply voltage to the P-type diffusion layer 32.
The width of the depletion layer formed by the P-type diffusion layer 32 and the P-type diffusion layer 32 is preferably smaller than the difference in junction depth between the N-type diffusion layer 30 and the P-type diffusion layer 32. This is because when a power supply voltage is applied to the P type diffusion layer 32, the N type diffusion layer 30 and the P type diffusion layer 32 are
This is because the N-type diffusion layer 30 is pinched off by the depletion layer formed by and the leak current always flows in the substrate direction.

Therefore, the depth of the N type diffusion layer 30 is preferably deeper than the P type diffusion layer 32 by at least 100 nm or more. The above protection circuit was tested by the measuring circuit shown in FIG. As shown in the figure, the capacitor 62 was charged by the variable voltage 60, and then the high voltage discharged from the capacitor 62 was regarded as ESD, and an experiment was conducted.

When a test is conducted with the measuring device shown in the figure, it is generally said that a withstand voltage of 300 V or more is sufficient. It was found that the semiconductor device according to this example has a withstand voltage of 300 V or more with respect to the applied voltage in both the positive and negative directions. The conventional semiconductor device has a withstand voltage of 300 V or more with respect to an applied voltage in the negative direction, but can obtain only a withstand voltage of about 80 V in the positive direction.

Next, a method of manufacturing the semiconductor device according to this embodiment will be described. First, the insulating film 1 is formed on the P-type support substrate 10.
An SOI substrate having an SOI layer 14 which is a single crystal silicon layer is formed via the substrate 2. For example, SIMOX for forming a buried silicon oxide film layer by oxygen ion implantation
Such an SOI substrate is formed by using the (Separation by IMplanted OXygen) method (FIG. 10A).

Next, although not shown, the SOI in the region where the P-type MOS transistor 20 of the integrated circuit element is to be formed.
Phosphorus, for example, is introduced into the layer as an n-type impurity. After that, the SOI layer 14 and the insulating film 1 in the region where the protective element is formed
2 is removed using a photolithography technique (FIG. 10B). Next, an oxide film 42 that serves as a pad when forming an element isolation film is formed by thermal oxidation, and a silicon nitride film 44 that serves as an oxidation mask is deposited on the oxide film 42 by a chemical vapor deposition (CVD) method (FIG. 11 ( a)).

Subsequently, the silicon nitride film 44 is processed into a pattern of an element isolation film by a photolithography technique (FIG. 11B). After that, thermal oxidation is performed using the silicon nitride film 44 as a mask to form the element isolation film 16. Thereby, the support substrate 1 in the region where the protective element is formed
An element isolation film 16 is formed on the upper surface of the semiconductor layer and in the SOI layer region forming the integrated circuit element. After forming the element isolation film in this manner, the silicon nitride film 44 is removed (FIG. 12).
(A)).

Then, for example, phosphorus ions are introduced into the regions where the deep N-type diffusion layer 26 and the N-type diffusion layer 30 are to be formed, by an ion implantation method (FIG. 12B). Then, the gate oxide film 46 of the integrated circuit element is formed by thermal oxidation, and the polysilicon film 48 to be the gate electrode is deposited by the CVD method. By the heat treatment for forming the gate oxide film, the impurities introduced to form the deep N-type diffusion layer 26 and the N-type diffusion layer 30 are diffused and spread deep into the support substrate 10. At this time, the impurities introduced into the region forming the cathode of the diode 64 are connected to each other by thermal diffusion to form the N-type diffusion layer 30 (FIG. 13A).

At an acceleration energy of 60 keV, 5E
As a result of performing a simulation in the case of implanting 13 cm ⁻² of phosphorus ions, the depth of the N-type diffusion layer 30 finally formed was about 3.7 μm. Then, the polysilicon film 44 is processed by the photolithography technique to form the gate electrode 48 of the integrated circuit element (FIG. 13).
(B)).

Next, P-type impurities are introduced into the formation region of the diode 64 and the P-type MOS transistor formation region to simultaneously form the P-type diffusion layer 32 as the anode diffusion layer and the source / drain diffusion layer 50 of the integrated circuit element. Yes (Fig. 14
(A)). As a result of simulation for when injected in ^5E15cm-2 and BF ₂ ions at an acceleration energy of 20 keV, the depth of the P-type diffusion layer 32 to be finally formed was about 0.2 microns. Therefore, N
The depth of the type diffusion layer 30 is sufficiently deeper than that of the P type diffusion layer, and is formed by the N type diffusion layer 30 and the P type diffusion layer 32 even when a power supply voltage is applied to the P type diffusion layer 32. Due to the depletion layer, the N-type diffusion layer 30 does not pinch off, and a leak current does not always flow in the substrate direction.

Then, an N-type impurity is introduced into the formation region of the diode 66 and the formation region of the N-type MOS transistor,
The shallow N-type diffusion layer 28 which is a cathode diffusion layer and the source / drain diffusion layer 52 of the integrated circuit element are formed at the same time.
Further, a shallow N-type layer 34 is also formed in the N-type diffusion layer 30 (FIG. 14B). After that, the interlayer insulating film 36 is formed by CVD.
Then, the contact hole 56 is opened (FIG. 15A).

Next, for example, tungsten is deposited as a metal film to be the wiring layer 38 and processed by using the photolithography technique to form the wiring layer 38 (FIG. 15B). In this way, the semiconductor device shown in FIG. 1 can be manufactured. As described above, according to the present embodiment, in the semiconductor device having the SOI structure, the two diodes 64 and 66 are formed as the protection elements on the support substrate, and a large current generated by static electricity or the like is released to reduce the current. It is possible to suppress the deterioration and the breakage of the semiconductor device due to it.

Further, when a negative ESD surge voltage is applied to the input / output pad, the diode 66 is in a forward bias state, so that an excessive voltage can be released to the support substrate 10. On the other hand, when a positive ESD surge voltage is applied to the input / output pad, the diode 64 is in a forward bias state, so that an excessive voltage can be released to the power supply line.

Since the cathode diffusion layer of the diode 66 is formed by the deep N-type diffusion layer 26 and the shallow N-type diffusion layer 28, there is no steep impurity concentration gradient, and the cathode diffusion layer and the support substrate 10 prevent It is possible to avoid concentration of an electric field at the junction when discharging is performed by the formed PN junction. In addition, in the above example, the protective element was formed in the supporting substrate. This is to improve the discharge effect of the protective element. Therefore, when the discharge effect cannot be sufficiently obtained when the protective element is formed in the SOI layer, the present invention is effective especially in a semiconductor device using an SOI substrate having an SOI layer of about 300 nm or less.

[0068]

As described above, according to the present invention, in a semiconductor device having an SOI structure, by forming an N-type MOS transistor and a P-type MOS transistor as protection elements on a supporting substrate, a large amount of static electricity is generated. Since the current can be released in the direction of the semiconductor substrate, it is possible to suppress the deterioration or destruction of the semiconductor device due to the current.

Further, when a negative ESD surge voltage is applied to the input / output pad, the drain diffusion layer of the N-type MOS transistor is in a forward bias state, so that an excessive voltage can be released to the supporting substrate, Positive ESD on the pad
When a surge voltage is applied, the drain diffusion layer of the P-type MOS transistor is in a forward bias state, so that an excessive voltage can be released to the power supply line.

The source of the N-type MOS transistor /
Since the drain diffusion layer is formed by the deep N-type diffusion layer and the shallow N-type diffusion layer, there is no sharp impurity concentration gradient, and discharge is performed by the PN junction formed by the source / drain diffusion layer and the supporting substrate. It is possible to avoid the concentration of the electric field at the junction when being exposed. In addition, P-type MOS
When a power supply voltage is applied to the source / drain diffusion layer of the transistor, the width of the depletion layer formed between the N-type diffusion layer directly below and the P-type source / drain diffusion layer is equal to the depth of the N-type diffusion layer. And the depth difference between the P-type source / drain diffusion layer and the P-type source / drain diffusion layer are smaller than each other. Can be prevented.

Further, by making the depth of the N-type diffusion layer deeper than the depth of the P-type diffusion layer by at least 100 nm or more, the effect is more remarkable. Further, in a semiconductor device having an SOI structure, by forming two diodes as protection elements on a supporting substrate, a large current generated by static electricity or the like can be released in the direction of the semiconductor substrate. It is possible to suppress deterioration and destruction of the.

Further, when a negative ESD surge voltage is applied to the input / output pad, one of the diodes is in a forward bias state, so that an excessive voltage can be released to the supporting substrate. Further, when a positive ESD surge voltage is applied to the input / output pad, the other diode is in a forward bias state, so that an excessive voltage can be released to the power supply line.

Further, since the cathode diffusion layer of one diode is formed by the deep N-type diffusion layer and the shallow N-type diffusion layer, there is no sharp impurity concentration gradient and it is formed by the cathode diffusion layer and the supporting substrate. It is possible to avoid concentration of an electric field at the junction when discharging is performed by the PN junction. In addition, when a power supply voltage is applied to the anode diffusion layer, the width of the depletion layer formed between the N-type diffusion layer immediately below and the anode diffusion layer is equal to the depth of the N-type diffusion layer and the anode diffusion layer. Since it is smaller than the depth difference,
The depletion layer formed by the N-type diffusion layer and the anode diffusion layer can prevent a leak current from flowing in the substrate direction.

By making the depth of the N-type diffusion layer deeper than the depth of the P-type diffusion layer by at least 100 nm or more, the effect is more remarkable. Further, since the protective element is formed in the supporting substrate in order to enhance the discharge effect of the protective element, it is difficult to obtain a sufficient discharge effect at about 300n.
Even in a semiconductor device formed on an SOI layer of m or less,
The discharge effect can be enhanced.

Since the N-type diffusion layer is formed before the gate oxidation step, it diffuses deeply into the supporting substrate as the gate oxidation is heat-treated. As a result, the N-type diffusion layer becomes P-type M
It can be used as a substitute well for forming an OS transistor. Further, since the substitute well thus formed does not require a long-time heat treatment for forming the well, the substitute well is formed without significantly increasing the manufacturing process or processing time of the semiconductor device using the SOI substrate. be able to.

[Brief description of drawings]

FIG. 1 is a diagram illustrating a semiconductor device according to a first embodiment of the present invention.

FIG. 2 is a measurement circuit diagram used in testing the semiconductor device according to the first embodiment of the present invention.

FIG. 3 is a process sectional view (1) showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 4 is a process sectional view (2) showing the method for manufacturing the semiconductor device according to the first embodiment of the invention.

FIG. 5 is a process sectional view (3) showing the method for manufacturing the semiconductor device according to the first embodiment of the invention.

FIG. 6 is a process sectional view (4) showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 7 is a process sectional view (5) showing the method for manufacturing the semiconductor device according to the first embodiment of the present invention.

FIG. 8 is a process sectional view (6) showing the method for manufacturing the semiconductor device according to the first embodiment of the invention.

FIG. 9 is a diagram illustrating a semiconductor device according to a second embodiment of the present invention.

FIG. 10 is a process sectional view (1) showing the method for manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 11 is a process sectional view (2) illustrating the method for manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 12 is a process sectional view (3) showing the method for manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 13 is a process sectional view (4) showing the method for manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 14 is a process sectional view (5) showing the method for manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 15 is a process sectional view (6) showing the method for manufacturing the semiconductor device according to the second embodiment of the present invention.

FIG. 16 is a diagram illustrating a structure of a conventional semiconductor device.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Support substrate 12 ... Insulating film 14 ... SOI layer 16 ... Element isolation film 18 ... N-type MOS transistor 20 ... P-type MOS transistor 22 ... N-type MOS transistor 24 ... P-type MOS transistor 26 ... Deep N-type diffusion layer 28 ... Shallow N type diffusion layer 30 ... N type diffusion layer 32 ... P type diffusion layer 34 ... Shallow N type diffusion layer 36 ... Interlayer insulating film 38 ... Wiring layer 40 ... Input / output pad 42 ... Oxide film 44 ... Silicon nitride film 46 ... Gate Oxide film 48 ... Polysilicon film 50 ... Source / drain diffusion layer 52 ... Source / drain diffusion layer 56 ... Contact hole 60 ... Variable power source 62 ... Capacitor 64 ... Diode 66 ... Diode 68 ... Semiconductor integrated circuit element 70 ... Gate electrode 72 ... Gate oxide film 74 ... N well

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Office reference number FI Technical indication location H01L 21/822 27/12 Z 29/78 29/786 H01L 29/78 301 K 613 Z

Claims (11)

[Claims] 1. A P-type semiconductor substrate, an insulating film formed on the P-type semiconductor substrate, a semiconductor layer formed on the insulating film, and a semiconductor element formed on the semiconductor layer.
In a semiconductor device having a protection element for protecting the semiconductor element, the protection element is provided inside a first N-type source diffusion layer formed on the semiconductor substrate and the first N-type source diffusion layer. The first
Of the second N-type source diffusion layer shallower than the N-type source diffusion layer, the first N-type drain diffusion layer formed on the semiconductor substrate, and the first N-type drain diffusion layer. The insulating film on the semiconductor substrate between the source region and the drain region, the drain region being provided inside and including the second N-type drain diffusion layer shallower than the first N-type drain diffusion layer A gate insulating film made of
An N-type MOS transistor having a gate electrode made of the semiconductor layer on the gate insulating film, an N-type diffusion layer formed on the semiconductor substrate, and an N-type diffusion layer provided inside the N-type diffusion layer Between the source region formed of a shallow P-type source diffusion layer, the drain region formed inside the N-type diffusion layer and formed of a P-type drain diffusion layer shallower than the N-type diffusion layer, and between the source region and the drain region. 2. A semiconductor device comprising: a P-type MOS transistor having a gate insulating film made of the insulating film on the semiconductor substrate and a gate electrode made of the semiconductor layer on the gate insulating film. 2. The semiconductor device according to claim 1, wherein when a power supply voltage is applied to the P-type source diffusion layer or the P-type drain diffusion layer, the N-type diffusion layer and the P-type source diffusion layer or The width of the depletion layer formed between the P-type drain diffusion layer and the P-type drain diffusion layer is smaller than the difference between the depth of the N-type diffusion layer and the depth of the P-type source diffusion layer or the P-type drain diffusion layer. Thus, the depth of the N-type diffusion layer and the depth of the P-type source diffusion layer or the P-type drain diffusion layer are controlled. 3. The semiconductor device according to claim 1, wherein the depth of the N-type diffusion layer is at least 100 more than the depth of the P-type source diffusion layer or the P-type drain diffusion layer.
A semiconductor device characterized by being deeper than nm. 4. A P-type semiconductor substrate, an insulating film formed on the P-type semiconductor substrate, a semiconductor layer formed on the insulating film, and a semiconductor element formed on the semiconductor layer,
In a semiconductor device having a protection element for protecting the semiconductor element, the protection element is provided inside a first N-type cathode diffusion layer formed on the semiconductor substrate and the first N-type cathode diffusion layer. A first diode having a cathode formed of a second N-type cathode diffusion layer shallower than the first N-type cathode diffusion layer and an anode formed of the semiconductor substrate; and a third diode formed on the semiconductor substrate. A cathode comprising an N-type cathode diffusion layer and an anode comprising a P-type anode diffusion layer provided inside the third N-type cathode diffusion layer and shallower than the third N-type cathode diffusion layer. A semiconductor device having two diodes. 5. The semiconductor device according to claim 4, wherein when a power supply voltage is applied to the P-type anode diffusion layer, it is between the third N-type cathode diffusion layer and the P-type anode diffusion layer. The width of the depletion layer formed is smaller than the difference between the depth of the third N-type cathode diffusion layer and the depth of the P-type anode diffusion layer, so that the third N-type cathode diffusion layer is formed. A semiconductor device in which the depth and the depth of the P-type anode diffusion layer are controlled. 6. The semiconductor device according to claim 4, wherein the depth of the second N-type diffusion layer is at least 100 nm or more deeper than the depth of the first P-type diffusion layer. apparatus. 7. The semiconductor device according to claim 1, wherein the semiconductor layer has a film thickness of 300 nm or less. 8. A P-type semiconductor substrate, an insulating film formed on the P-type semiconductor substrate, a semiconductor layer formed on the insulating film, and a semiconductor element formed on the semiconductor layer.
A method of manufacturing a semiconductor device having a protection element for protecting the semiconductor element, comprising: patterning the insulating film and the semiconductor layer to form an N-type MOS transistor forming the protection element.
A first gate electrode made of the semiconductor layer is formed in the region of 2 and a second gate electrode made of the semiconductor layer is formed in the second region of the P-type MOS transistor forming the protection element. A step of forming a gate electrode, and a step of introducing an N-type impurity into the first region and the second region by using the first gate electrode and the second gate electrode as a mask And a step of thermally oxidizing the semiconductor substrate into which the N-type impurity has been introduced to form a gate oxide film in the semiconductor element region, and a first N-type source diffusion layer and a first N-type source diffusion layer in the first region. Forming an N-type drain diffusion layer in the second region, forming a gate oxide film in the second region, and introducing a P-type impurity into the second region using the second gate electrode as a mask, P type in the N type diffusion layer Forming a P-type drain diffusion layer and a P-type drain diffusion layer, and at the same time forming a P-type region of the semiconductor device region; and a P-type impurity introduction step using the first gate electrode as a mask. Impurities are introduced to form a second N-type source diffusion layer in the first N-type source diffusion layer and a second N-type drain diffusion layer in the first N-type drain diffusion layer, and at the same time, An N-type impurity introduction step of forming an N-type region of the semiconductor element region, the second gate electrode, the P-type source diffusion layer, and the P-type source diffusion layer.
-Type drain diffusion layer, P-type MOS transistor, the first gate electrode, the first N-type source diffusion layer, the second N-type source diffusion layer, and the first N-type drain diffusion layer A method of manufacturing a semiconductor device, comprising: forming a protection element having an N-type MOS transistor having the second N-type drain diffusion layer. 9. The method of manufacturing a semiconductor device according to claim 8, wherein in the first N-type impurity introduction step, when a power supply voltage is applied to the P-type source diffusion layer or the P-type drain diffusion layer, The width of the depletion layer formed between the N-type diffusion layer and the P-type source diffusion layer or the P-type drain diffusion layer is equal to the depth of the N-type diffusion layer and the P-type source diffusion layer or the A method of manufacturing a semiconductor device, comprising introducing an N-type impurity into the first region and the second region so as to be smaller than a difference in depth of the P-type drain diffusion layer. 10. A P-type semiconductor substrate, an insulating film formed on the P-type semiconductor substrate, a semiconductor layer formed on the insulating film, a semiconductor element formed on the semiconductor layer, and A method of manufacturing a semiconductor device having a protection element for protecting a semiconductor element, comprising: a first region for patterning the insulating film and the semiconductor layer to form a first diode constituting the protection element; and the protection element. An opening forming step of forming an opening reaching the semiconductor substrate in a second region forming the second diode forming the second diode, and introducing an N-type impurity into the first region and the second region. A first N-type impurity introduction step, and the semiconductor substrate into which the N-type impurity has been introduced is thermally oxidized to form a gate oxide film in the semiconductor element region, and a first N-type impurity is formed in the first region. Type cathode A gate oxide film forming step of forming a diffusion layer, a second N-type cathode diffusion layer in the second region, and introducing a P-type impurity into the second region to form the third N-type cathode diffusion layer. Forming a P-type anode diffusion layer therein and simultaneously forming a P-type region of the semiconductor element region; and introducing an N-type impurity into the first region, the first N-type cathode Forming a second N-type cathode diffusion layer in the diffusion layer and at the same time forming an N-type region of the semiconductor element region, and introducing an N-type impurity, the first N-type cathode diffusion layer and the first N-type cathode diffusion layer. Second diode having an N-type cathode diffusion layer, a first diode having an anode made of the semiconductor substrate, a cathode made of a third N-type cathode diffusion layer formed on the semiconductor substrate, and the P-type From the anode diffusion layer The method of manufacturing a semiconductor device characterized by forming a protective element and a second diode having an anode that. 11. The method of manufacturing a semiconductor device according to claim 10, wherein in the first N-type impurity introduction step, the third N-type cathode is applied when a power supply voltage is applied to the P-type anode diffusion layer. The width of the depletion layer formed between the diffusion layer and the P-type anode diffusion layer is smaller than the difference between the depth of the third N-type cathode diffusion layer and the depth of the P-type anode diffusion layer. As described above, a method of manufacturing a semiconductor device, characterized in that N-type impurities are introduced into the first region and the second region.