JPH07335871A - Insulated gate semiconductor device and its manufacturing method - Google Patents

Abstract

PURPOSE:To provide structure of an insulated gate semiconductor device which can coexist with a polycrystalline silicon diode and does not cause breakdown voltage deterioration when process is reduced. CONSTITUTION:An N-type diffusion layer 8a for a low ON resistor and an N-type diffusion layer 8b for increasing the drain breakdown voltage are formed in the surface region of an N-type epitaxial layer 2 on an N<+> substrate 1 for a drain, without using a mask, in a self-alignment manner to a P-type diffusion layer 6a just under a LOCOS oxide film 7 in a field part. Contact 30 between an aluminum gate electrode 15c constituting a gate finger and a polycrystalline silicon gate layer 10a, and a polycrystalline silicon diode (which is not shown in Figure) are formed on the oxide film 7. The impurity concentration of the P-type diffusion layer 6a is set lower than that of a P-type diffusion layer 11a for a channel. The P-type diffusion layer 11a and an N-type diffusion layer 12a for a source are formed by diffusion self-alignment using the polycrystalline silicon gate 10a as a mask.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a large output vertical MOSF.
ET (hereinafter referred to as vertical power MOSFET) and I
The present invention relates to an insulated gate semiconductor device such as a GBT (Insulated gate bipolar transistor) and a method for manufacturing the same, and in particular, an insulated gate capable of simplifying process steps without lowering breakdown voltage and reliability and reducing manufacturing cost. Type semiconductor device and its manufacturing method.

[0002]

2. Description of the Related Art Conventionally, in a vertical power MOSFET, in order to reduce the resistance of a polycrystalline silicon gate, a gate electrode structure in which an aluminum electrode wiring is extended from a gate pad to make contact with the polycrystalline silicon, so-called "gate finger". Is provided. As a vertical power MOSFET provided with this gate finger, for example, Japanese Patent Application Laid-Open No. 2-3
The structure shown in FIG. 15 disclosed in Japanese Patent No. 5780 is known. 15A is a plan view of the vertical power MOSFET, and FIG. 15B is a sectional structural view taken along the line AA ′ of FIG. In FIG. 15, power MOSFE
If T is an n-channel, for example, reference numeral 21 is a gate electrode (gate finger), 22 is an n-type drain region, 2
3 is a p-type diffusion layer (hereinafter referred to as p-well), 24 is a gate oxide film, 25 is polycrystalline silicon, 26 is a channel diffusion layer, 27 is an n-type source region, 28 is a drain electrode,
Reference numeral 29 indicates a source electrode.

In this vertical power MOSFET, the p-well 23 formed on the silicon surface directly under the gate finger is provided to prevent deterioration of the drain-source breakdown voltage. In order to expand the safe operation area, p formed immediately below the gate finger 21 as shown in the sectional structure of FIG.
Well 23 and channel diffusion layer 2 of MOSFET cell
It is disclosed that the distance x from the MOSFET 6 is made smaller than the distance between cells of the MOSFET or arranged at equal intervals. In order to realize this structure, power MOS
By performing a well-known photolithography process (hereinafter abbreviated as photo process) and an impurity introduction and diffusion process before forming the gate oxide film 24, separately from the channel formation region 26 formed in the cell portion of the FET. A p well 23 is formed.

[0004]

However, in the above-mentioned conventional vertical power MOSFET, the p just below the gate finger 21 is formed to secure the breakdown voltage between the drain and the source and to expand the backward safe operation area. The well 23 must be formed before the gate oxide film is formed, and thus there is a drawback that a photo process is required to form the p well.

Further, when the gate finger 21 is formed, if the contact between the polycrystalline silicon layer 25 and the aluminum electrode is made on the gate oxide film 24, the gate-source breakdown voltage yield is lowered. Was not considered.

Further, in the process of forming the channel diffusion layer 26 of the conventional vertical power MOSFET, although the polycrystalline silicon layer 25 is used as a mask for ion implantation in the active region, the conductivity is opposite to that of the drain region in the scribe line region. A resist mask must be used to prevent the introduction of impurities of a certain shape, which requires a photo-process, resulting in a high manufacturing cost.

Therefore, an object of the present invention is to coexist with a polycrystalline silicon diode having stable characteristics without deterioration of drain-source breakdown voltage and gate-source breakdown voltage even if the number of process steps is reduced and simplified. It is an object of the present invention to provide an insulated gate type semiconductor device and a manufacturing method thereof.

[0008]

In order to achieve the above object, an insulated gate semiconductor device according to the present invention is a semiconductor layer of a first conductivity type which is a drain, that is, in FIG.
The first impurity region of the second conductivity type provided in the surface region of the n-type epitaxial layer 2, that is, the p-type diffusion layer 1 for channel
1a and a second impurity region of the second conductivity type, that is, a p-type diffusion layer 6a, and a third impurity region of the first conductivity type that is a source provided in the channel p-type diffusion layer 11a, that is, an n-type diffusion layer for the source. 12a, and a polycrystalline silicon gate layer 10a provided on the channel p-type diffusion layer 11a via a first insulating layer serving as a gate insulating film, that is, a gate oxide film 9a, and a metal serving as a source electrode and a gate electrode. A p-type diffusion layer 6 in an insulated gate semiconductor device comprising a source electrode 15a made of aluminum (hereinafter abbreviated as aluminum) and a gate electrode 15c made of aluminum.
The surface impurity concentration of a is set to the channel p-type diffusion layer 11a.
Of the second insulating layer, that is, a LOCOS (LOCal Oxidation of Silicon) oxide film 7 thicker than the gate oxide film 9a is provided on the p-type diffusion layer 6a. 10a,
The contact 30 connecting the polycrystalline silicon gate layer and the gate electrode 15c is connected to the LOCOS oxide film 7.
It is characterized by being provided above.

Further, in the above insulated gate semiconductor device, the first impurity region 11a of the second conductivity type and the second impurity region 11a
As shown in FIG. 1, the conductivity type second impurity region 6a is
It is preferable if they are separated by the fourth impurity region of the first conductivity type, that is, the n-type diffusion layer 8a.

A semiconductor layer of the first conductivity type serving as a drain, that is, in FIG. 6, a first impurity region of the second conductivity type provided on the surface of the n-type epitaxial layer 2, that is, a p-type diffusion layer for a channel. 11a and the second impurity region, that is, the p-type diffusion layer 6a, the third impurity region of the first conductivity type that is the source, which is provided in the channel p-type diffusion layer 11a, that is, the source n-type diffusion layer 12a, and A polycrystalline silicon gate layer 10a provided on the p-type diffusion layer 11a for a channel via a first insulating layer to be a gate insulating film, that is, a gate oxide film 9a, and a metal layer to be a source electrode and a gate electrode, that is, an aluminum source. In an insulated gate type semiconductor device including an electrode 15a and an aluminum gate electrode 15c, a first electrode that is thicker than the gate oxide film 9a on the p-type diffusion layer 6a. Insulating layer or LOCOS oxide film 7
And providing the polycrystalline silicon gate layer 10a on the LOCOS oxide film 7, and providing a contact 30 connecting the polycrystalline silicon gate layer 10a and the gate electrode 15c on the LOCOS oxide film 7, and A floating field ring (hereinafter abbreviated as FFR) using the fifth impurity region of the second conductivity type, that is, the p-type diffusion layer 6b formed in the same step as the p-type diffusion layer 6a is formed on the n-type epitaxial layer around the active region. It is possible to obtain an insulated gate type semiconductor device having a structure provided inside 2.

Alternatively, as shown in FIG. 7, the FFR provided in the n-type epitaxial layer 2 around the active region of the insulated gate semiconductor device is formed in the same step as the channel p-type diffusion layer 11a. The sixth impurity region of the second conductivity type, that is, the p-type diffusion layer 11c may be used.

In any one of the above-mentioned insulated gate semiconductor devices, it is preferable that a polycrystalline silicon diode 50 as shown in FIG. 14 is further provided on the second insulating layer, that is, the LOCOS oxide film 7.

Further, the first insulating layer and the polycrystalline silicon gate layer, that is, the gate oxide film 9 in FIG.
c and the polycrystalline silicon gate layer 10d may be further provided in the scribe line formation region.

Further, it is preferable that the polycrystalline silicon layer on the scribe line formation region is set to the same potential as that of the first conductivity type semiconductor layer serving as the drain.

In the method of manufacturing an insulated gate semiconductor device according to the present invention for manufacturing any of the above insulated gate semiconductor devices, as shown in FIG. 2A, the semiconductor layer of the first conductivity type, that is, Using the nitride film 4 formed on the surface of the n-type epitaxial layer 2 as a mask, impurities are introduced into the second impurity region of the second conductivity type, that is, the p-type diffusion layer 6a, and then the nitride film 4 is used as a mask. At least a step of performing the selective oxidation to form the second insulating layer, that is, the LOCOS oxide film 7 is characterized.

Alternatively, in the method of manufacturing an insulated gate semiconductor device according to the present invention, as shown in FIGS. 2A to 2C, the semiconductor layer of the first conductivity type, that is, the n-type epitaxial layer 2 is formed. Using the nitride film 4 formed on the surface as a mask, impurities are introduced into the second impurity region of the second conductivity type, that is, the p-type diffusion layer 6a, and then selective oxidation is performed using the nitride film 4 as a mask. Second insulating layer, L
An OCOS oxide film 7 is formed, and then the LOCOS oxide film 7 is used as a mask to separate the first impurity region of the second conductivity type, that is, the channel p-type diffusion layer 11a and the p-type diffusion layer 6a from each other. A step of forming the fourth impurity region of conductivity type, that is, the n-type diffusion layer 8a may be included.

In the method of manufacturing an insulated gate semiconductor device according to the present invention, as shown in FIG. 9, first, the second conductivity type is first formed on the entire surface of the semiconductor layer of the first conductivity type, that is, the n-type epitaxial layer 2. -Shaped second impurity region, ie, p
Forming the second diffusion layer 6a, then forming the second insulating layer, that is, the oxide film 7, and using the oxide film 7 as a mask to cancel the p-type diffusion layer 6a. The method may include the step of introducing an impurity into the region, that is, the n-type diffusion layer 8a to form the n-type diffusion layer 8a, and then forming the first insulating layer, that is, the gate oxide film 9a to be a gate insulating film.

[0018]

According to the insulated gate semiconductor device of the present invention, as shown in FIG. 1, the insulating film immediately below the gate electrode 15c forming the gate finger, that is, the oxide film 7 is thickened to make the aluminum electrode of the gate finger. Contact 30 for electrically connecting 15c and polycrystalline silicon 10a
Is provided on the thick oxide film 7, it is possible to avoid a gate breakdown voltage defect such as a gate leak due to mechanical and electrical stress between the aluminum electrode 15c and the polycrystalline silicon 10a. Then, the p-type diffusion layer 6 directly below the gate finger
By setting the surface impurity concentration of a to a lower impurity concentration than the channel p-type diffusion layer 11a, the p-type diffusion layer 6a functions as a low-concentration offset region, and the drain breakdown voltage is improved.

Further, in the above insulated gate semiconductor device, the first impurity region 11a of the second conductivity type and the second impurity region 11a
As shown in FIG. 1, the conductivity type second impurity region 6a is
By having a structure separated by the fourth impurity region of the first conductivity type, that is, the n-type diffusion layer 8a, low on-resistance can be achieved.

Further, the FFR provided in the n-type epitaxial layer 2 around the active region is, as shown in FIG. 6, the fifth impurity region of the second conductivity type formed in the same step as the p-type diffusion layer 6a, that is, By using the p-type diffusion layer 6b, a photomask for forming the LOCOS oxide film 7 can be used, a photomask for adding the FFR can be eliminated, and the FFR can be self-aligned directly under the LOCOS oxide film 7. Can be formed as desired.

Alternatively, the FFR provided in the n-type epitaxial layer 2 around the active region is, as shown in FIG. 7, a sixth impurity of the second conductivity type formed in the same step as the p-type diffusion layer 11a for a channel. Region or p-type diffusion layer 11
By using c, a photomask for p-type ion implantation for the channel can be used to prevent the p-type diffusion layer for the channel from entering the scribe line formation region, so a photomask for adding FFR is not required. Can be

In any of the insulated gate semiconductor devices described above, the polycrystalline silicon diode 50 provided on the second insulating layer, that is, the LOCOS oxide film 7 operates more stably than that provided on the gate insulating film. The polycrystalline silicon diode 50 shown in FIG.
Is connected between the source electrode 15a and the gate electrode 15c to function as a gate protection diode.

Further, as shown in FIG. 10, by further providing the gate oxide film 9c and the polycrystalline silicon gate layer 10d in the scribe line formation region, the channel p-type diffusion layer is prevented from entering the scribe line formation region. It is possible to eliminate the need for a photomask for preventing the formation of the p-type diffusion layer for the channel.

Further, by setting the potential of the polycrystalline silicon layer on the scribe line forming region to the same potential as that of the first conductivity type semiconductor layer serving as the drain, the drain.
When a voltage is applied between the sources, it suppresses the depletion layer from extending from the active region toward the chip termination,
Prevents deterioration of breakdown voltage between sources.

In the method of manufacturing an insulated gate semiconductor device according to the present invention for manufacturing any of the above insulated gate semiconductor devices, as shown in FIG. 2A, the semiconductor layer of the first conductivity type, that is, Using the nitride film 4 formed on the surface of the n-type epitaxial layer 2 as a mask, impurities are introduced into the second impurity region of the second conductivity type, that is, the p-type diffusion layer 6a, and then the nitride film 4 is used as a mask. By including at least the step of performing the selective oxidation, the second insulating layer, that is, the LOCOS oxide film 7 is formed into the p-type diffusion layer 6a.
Can be formed in a self-aligned manner.

Alternatively, as shown in FIGS. 2 (a) to 2 (c), the nitride film 4 formed on the surface of the semiconductor layer of the first conductivity type, that is, the n-type epitaxial layer 2 is used as a mask for the second layer. Second conductivity type impurity region, that is, p-type diffusion layer 6a
Of the second insulating layer, i.e., LOCO.
An S oxide film 7 is formed, and then the LOCOS oxide film 7 is used as a mask to form a fourth impurity region of the first conductivity type, that is, n.
Since the n-type diffusion layer 8a includes at least the step of forming the n-type diffusion layer 8a, the n-type diffusion layer 8a can self-align with the first impurity region of the second conductivity type, that is, the p-type diffusion layer for the channel, without requiring an additional photomask. 11a and the p-type diffusion layer 6a can be formed so as to be separated from each other.

Further, as shown in FIG. 9, first, the first
A second impurity region of the second conductivity type, that is, the p-type diffusion layer 6a is formed on the entire surface of the semiconductor layer of the conductivity type, that is, the n-type epitaxial layer 2, and then the second insulating layer, that is, the oxide film 7 is formed.
And the p-type diffusion layer 6 is formed using the oxide film 7 as a mask.
a step of forming a fourth insulating region of the first conductivity type, that is, an n-type diffusion layer 8a by introducing impurities so as to cancel a, and then forming the first insulating layer, that is, a gate oxide film 9a to be a gate insulating film. With the above, the oxide film 7, the p-type diffusion layer 6a, and the n-type diffusion layer 8a can be formed in a self-aligned manner.

[0028]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Some preferred embodiments of an insulated gate semiconductor device and a method of manufacturing the same according to the present invention will be described in detail below with reference to the drawings.

<Embodiment 1> FIG. 1 is a diagram showing an embodiment of an insulated gate semiconductor device according to the present invention, in which an n-channel vertical power MOSFET is shown. FIG. 1A is a plan view showing a main part of a vertical power MOSFET. For convenience of explanation, an aluminum electrode is made transparent and only a contour is shown and a surface protective film is omitted.
(B) is a cross-sectional structural view of a portion indicated by a line AA 'on the plan view. 2 is a sectional structural view of a main step showing a method of manufacturing the vertical power MOSFET shown in FIG. 1A, and FIG. 3 is a plan view of the entire chip. In FIG. 1, the left end is the chip end where the scribe line is formed, and the right is the active region of the vertical power MOSFET.

First, the structure of the power MOSFET according to the present invention will be described with reference to FIG. In FIG. 1 (b), reference numeral 1 n ⁺ indicates a substrate, on the n ⁺ substrate 1 n-type epitaxial layer 2 of the required thickness is formed, the drain electrode 17 is formed on the back surface. Active area 10
A thick oxide film 7 is formed on the n-type epitaxial layer 2 of the field portion 110 between the 0 and the chip termination portion 120, and the gate electrode 10 of polycrystalline silicon is formed on the oxide film 7.
It has a structure in which a, an insulating layer 14, and an aluminum gate electrode 15c are sequentially stacked. In addition, immediately below the oxide film 7,
A p-type diffusion layer 6a having a surface impurity concentration lower than that of the channel p-type diffusion layer 11a is formed. As shown in the plan view of FIG. 1A, this polycrystalline silicon gate electrode 10a
And the aluminum gate electrode 15c are electrically connected to each other through a plurality of contact holes 30 provided in the insulating layer 14 to form a gate finger. The polycrystalline silicon in the gate finger portion and the polycrystalline silicon in the active region 100 are electrically connected via the polycrystalline silicon between the regions 42 of the p-type diffusion layer 13a provided in plural.

In the active region 100, as shown in the plan view, a large number of alternating rectangular windows 40 of the polycrystalline silicon gate electrode 10a are provided (the shape is not limited to a rectangle but may be a circle or a polygon). Good)), so-called DSA (Diffused Self Aligned)
-Channel p-type diffusion layer 1 so as to form a MOS structure
1a and the source n-type diffusion layer 12a are n
It is formed in the diffusion layer 8a. At the center of each rectangular window 40 of the polycrystalline silicon gate electrode 10a, a high concentration p-type diffusion layer 13 is formed in order to make an ohmic connection between the channel p-type diffusion layer 11a and the aluminum source electrode 15a.
a is formed. The source electrode 15a made of aluminum has contact holes 34 and regions 42 provided in the rectangular window 40.
The contact hole 32 provided therein electrically connects the source n-type diffusion layer 12a and the p-type diffusion layer 13a.

As shown in the sectional view, the chip termination portion 120 has a high height for making ohmic contact with the n-type diffusion layer 8b on the surface of the n-type epitaxial layer 2 and the aluminum drain field plate electrode 15b on the scribe line region. A concentration n-type diffusion layer 12b is formed, and an aluminum drain field plate electrode 15b is formed on the n-type diffusion layer 8b via a gate oxide film 9b and an insulating layer 14. Further, the uppermost layer is covered with the surface protective film 16 except for the scribe line forming region and the pad region (not shown).

The structure of the vertical power MOSFET described above is a plan structure and a sectional structure in which the aa 'line portion shown in the chip plan view of FIG. 3 is enlarged, and two source pads SPAD and SPAD are provided on the chip. A gate pad GPAD is provided. These pad portions are portions where the aluminum electrodes 15a and 15c are exposed by removing the surface protective film 14. In addition, the cross-sectional structure of the gate finger portion indicated by the line bb 'on the chip is a structure in which the right side portion from the center of the gate electrode layer 15c in FIG.

The vertical power MOSF configured as above
A method of manufacturing the ET will be briefly described with reference to FIG. 2 by taking a vertical power MOSFET having a breakdown voltage of 60 V as an example. In FIG. 2A, an n-type epitaxial layer 2 having a thickness of 1 Ω · cm is formed to a thickness of 10 μm on an n ⁺ substrate 1 having a high concentration of, for example, 0.002 to 0.02 Ω · cm doped with arsenic or antimony. After forming the surface oxide film 3 that prevents the surface from being damaged by ion implantation, the nitride film 4 is deposited. In the photo process, the surface oxide film 3 and the nitride film 4 are etched using the photoresist 5 as a mask, and, for example, boron ions are added to 50 by using the nitride film 4 and the photoresist 5 as a mask.
Ion implantation is performed under the conditions of keV and 1 to 5 × 10 ¹² cm ⁻² to form the low concentration p-type diffusion layer 6a.

Next, after removing the photoresist 5, FIG.
(B), selective oxidation is performed using the nitride film 4 as a mask to form a LOCOS oxide film 7 having a thickness of about 900 nm. Then, after removing the nitride film 4, phosphorus ion implantation is performed with, for example, 1 using the LOCOS oxide film 7 as a mask.
25 keV, about 1.5 × 10 ¹² cm ⁻² , and heat treatment is performed to simultaneously form n-type diffusion layers 8a and 8b having a diffusion depth of about 2 μm. Next, the surface oxide film 3 is removed, and new oxidation is performed to form gate oxide films 9a and 9b having a thickness of 50 nm.

Next, polycrystalline silicon is deposited to a thickness of 350 nm by a well-known CVD method and patterned by a photo step to form a polycrystalline silicon layer 10a for a gate, and then the photoresist 18 on the chip end portion 120 and field portion 110 sides. Is used as a mask and the active region side is masked with the polycrystalline silicon layer 10a as a mask, and boron ions of 50 ke are used.
Ion implantation under the condition of V, 5 × 10 ¹³ cm ^-2 ,
Thereafter, heat treatment is performed to form the p-type diffusion layer 11a for the channel, and the structure shown in FIG. 2C is obtained. After that, by performing a normal power MOSFET process such as formation of an n-type diffusion layer 12a serving as a source using the polycrystalline silicon layer 10a as a mask, formation of an insulating layer 14, and opening of contact holes, The sectional structure shown in b) can be obtained.

The gate of the vertical power MOSFET
When a protection diode 50 for preventing electrostatic breakdown of the gate is formed between the sources as in the equivalent circuit shown in FIG. 14C, it is shown in the plan view of FIG. 14A and the sectional view of FIG. As described above (however, the aluminum electrode pattern 15a is shown by a chain double-dashed line), the polycrystalline silicon layer 10a on the LOCOS oxide film 7 is formed, for example, by CVD (Chemical Vapor Depositi).
After depositing a 2 μm oxide film by the on) method, patterning is performed by a photo process to deposit phosphorus to form an n-type polycrystalline silicon region, and then the oxide film is removed and boron ion implantation is performed to form a p-type polycrystalline silicon region. To form a series connected diode array. This diode array is covered with an insulating layer 14, and a contact hole 52 is provided at the center. The outermost contour of the pattern of the diode array is shown in FIG.
As shown in (b), since it is directly connected to the polycrystalline silicon gate electrode 10a in the active region, the source electrode 15 is connected through the contact hole 52 provided in the central portion.
The aluminum photo process may be performed using a photo mask having a pattern formed so as to be connected to a. Further, if the n-type diffusion layer and the p-type diffusion layer for the diode 50 are also used as the n-type diffusion layer 12a and the p-type diffusion layer 11a of the vertical power MOSFET, respectively, the number of steps can be reduced.

Alternatively, the protection diode 50 for preventing electrostatic breakdown may be formed in a pattern arrangement as shown in FIG. 16A is a plan view, and FIG. 16B is an enlarged cross-sectional view of a portion indicated by line AA ′ in the plan view. In the figure, the aluminum electrode pattern is shown by a chain double-dashed line. The manufacturing method is the same as in the case of FIG. 14, but the electrode extraction is different. The pattern of the polycrystalline silicon 10e is formed in a rectangular ring shape, but the lower side on the paper surface is omitted in the plan view. In the innermost n-type polycrystalline silicon region of the rectangular ring-shaped polycrystalline silicon 10e, the contact hole 53 with the aluminum gate electrode 15c is formed in a ring shape, and the polycrystalline silicon 10e formed in the rectangular ring shape is formed. Outermost n
In the polycrystalline silicon region, as shown in the figure, an L-shaped contact hole 52 for connecting to the aluminum source electrode 15a is provided. By arranging the patterns in this way, the aluminum electrode 15c at the center of the rectangular ring-shaped protection diode 50 can be used as a gate pad. Further, in the configuration of FIG. 14, the active region is reduced by the amount used as the protection diode, whereas in the configuration of FIG. 16, the gate finger region is reduced, and the active region is not reduced.

Further, in the sectional structure shown in FIG.
Since the p-type diffusion layer 6a has a lower impurity concentration than the n-type diffusion layer 8a, the p-type diffusion layer 6a and the p-type diffusion layer 11a are separated by the n-type diffusion layer 8a. When the impurity concentration of the diffusion layer 6a is higher, the p-type diffusion layer 6a and the p-type diffusion layer 11a have a connected structure.

As described above, the vertical power M of this embodiment
The OSFET has about 9 contact holes 30 between the aluminum gate electrode layer 15c and the polycrystalline silicon gate electrode layer 10a.
It is formed on a thick LOCOS oxide film 7 of 00 nm and
Immediately below the OCOS oxide film 7, p of the conventional example shown in FIG.
Instead of the well diffusion layer, the p-type diffusion layer 12a for the channel
The p-type diffusion layer 6a having a surface impurity concentration lower than that of the above is formed in a self-aligned manner. Therefore, a photomask for the p-well becomes unnecessary. Since the p-type diffusion layer 6a functions as a low concentration offset region, the drain breakdown voltage can be improved.

In order to prevent the p-type diffusion layer from being formed at the end of the chip and degrading the drain breakdown voltage, the LOCOS oxide film 7 is not formed near the scribe line formation region. Therefore, although the thickness of the field oxide film becomes thin in the vicinity of the chip end portion 120, new knowledge has been obtained that deterioration of breakdown voltage due to this does not pose a problem.

Further, since the aluminum contact 30 of the gate finger can be formed on the thick field oxide film 7 independently of the gate oxide film 9a, even if the thickness of the gate oxide film 9a is reduced to 50 nm or less, the mechanical and mechanical properties of the aluminum contact portion are reduced. It is possible to avoid gate breakdown voltage failure such as gate leakage due to electrical stress.

Further, according to the manufacturing method of the present embodiment, the n-type diffusion layer 8 for reducing the on-resistance of the vertical power MOSFET.
a and the n-type diffusion layer 8b that suppresses the extension of the depletion layer to the chip end portion and improves the drain-source breakdown voltage are self-aligned with the region where the LOCOS oxide film 7 is not formed without requiring an additional mask. Can be formed.

Further, the polycrystalline silicon diode 50 for preventing electrostatic breakdown of the gate oxide film of the power MOSFET is formed on the LOCOS oxide film 7 thicker than the gate oxide film 9a. Since the diffusion layer 6a having a conductivity opposite to that of the drain layer can be formed directly under the LOCOS oxide film 7, it is possible to suppress the breakdown voltage variation and the leak current increase of the polycrystalline silicon diode due to the variation of the drain voltage.

In this embodiment, the n-type diffusion layers 8a and 8b are p-type.
The case where it is formed deeper than the shape diffusion layer 11a is shown.
When it is formed shallower than the p-type diffusion layer 11a, the effect of reducing the on-resistance is small, but there is an effect of suppressing deterioration of the drain-source breakdown voltage.

<Embodiment 2> Another embodiment of the insulated gate semiconductor device according to the present invention will be described with reference to FIG. Figure 4
FIG. 6 is a cross-sectional view showing a structure when the present invention is applied to an n-channel vertical power MOSFET. In FIG. 4, the same components as those of the first embodiment shown in FIG. 1 are designated by the same reference numerals for convenience of description, and detailed description thereof will be omitted. That is, in this embodiment, as shown in FIG.
The vertical power MOSFET shown in FIG. 6 differs from the first embodiment in that the n-type diffusion layers 8a and 8b are omitted.

Therefore, in the first embodiment described above, the LOC
The steps of phosphorus ion implantation and heat treatment of the n-type diffusion layers 8a and 8b which are formed in a self-aligned manner using the OS oxide film 7 as a mask are eliminated, and the steps can be simplified. In addition, the n-type diffusion layer 8
This embodiment is the same as the first embodiment except that the on-resistance is reduced by a and the drain / source breakdown voltage is improved by suppressing the extension of the depletion layer to the chip termination portion by using the n-type diffusion layer 8b. Of course, it has the effect of.

<Embodiment 3> Another embodiment of the insulated gate semiconductor device according to the present invention will be described with reference to FIG.
FIG. 5 shows the present invention in which an n-channel vertical power MOSFET is used.
It is sectional drawing which shows the structure at the time of applying to. Note that FIG.
In FIG. 1, the same components as those of the first embodiment shown in FIG. 1 are designated by the same reference numerals for convenience of description, and detailed description thereof will be omitted. That is, in this embodiment,
At the end of the chip, the LOCOS oxide film 7 and the p-type diffusion layer 6a are connected to the drain field plate electrode 15b.
Under the scribe line area
The polycrystalline silicon layer 10b extending from the end side of the diffusion layer 8b to the oxide film 7 immediately below the drain field plate electrode 15b is provided, and the polycrystalline silicon layer 10 is provided.
This is different from the first embodiment in that the b and the field plate electrode 15b are connected by a contact hole 36 provided in the insulating layer 14. This need only be changed in the mask pattern, so there is no need to add any new steps to the manufacturing steps in FIG.

With this structure, in the vertical power MOSFET of this embodiment, when the voltage is applied between the drain and the source, the drain voltage is also applied to the polycrystalline silicon layer 10b. The effect of suppressing the depletion layer from reaching the terminal portion can be enhanced.
Further, since the field portion is covered with the thick oxide film 7 and the insulating layer 14, the leakage current is further reduced and the surface stability is further improved as compared with the case of FIG. 1 in which the gate oxide film 9b and the insulating layer 14 are covered. . Of course, it has the same effect as the embodiment of FIG.

<Embodiment 4> Still another embodiment of the insulated gate semiconductor device according to the present invention will be described with reference to FIG.
FIG. 6 shows the present invention in which an n-channel vertical power MOSFET is used.
It is sectional drawing which shows the structure at the time of applying to. Note that FIG.
In FIG. 1, the same components as those of the first embodiment shown in FIG. 1 are designated by the same reference numerals for convenience of description, and detailed description thereof will be omitted. That is, in this embodiment,
The p-type diffusion layer 6a immediately below the LOCOS oxide film 7 in the gate finger portion has a higher impurity concentration and a deeper diffusion depth than the channel p-type diffusion layer 11a, and the gate finger portion is closer to the chip end portion side. Gate electrode 15 extended to the bottom
The difference from the first embodiment is that an FFR using a p-type diffusion layer 6b formed in the same step as the p-type diffusion layer 6a is provided immediately below the oxide film 7 of c.

In the case of the vertical power MOSFET of the present embodiment thus constructed, the p-type diffusion layers 6a and 6b are not completely depleted and can be suppressed to be equal to the source potential. L polycrystalline silicon diode
The influence of the drain voltage fluctuation when formed on the OCOS oxide film 7 can be made smaller than that in the case of FIG. In addition, the vertical power MOSFET with FFR of this embodiment
In this case, since the p-type diffusion layer 6b formed in the same step as the p-type diffusion layer 6a is used, the p-type diffusion layer 6b can be formed directly below the LOCOS oxide film 7 in a self-aligned manner, and therefore an additional mask for FFR is not required. By adopting the structure with the FFR, it is possible to realize the vertical power MOSFET without lowering the breakdown voltage even if the impurity concentration of the p-type diffusion layer 6a is increased as compared with the above-described embodiments. In this embodiment, the thick LOCOS oxide film 7 cannot be used as the field oxide film at the end of the chip, but the thickness is thin, but this is the same as in the embodiment of FIG. The deterioration of breakdown voltage is not a problem. Therefore, also in this embodiment, the same effect as that of FIG. 1 can be obtained.

<Embodiment 5> Another embodiment of the insulated gate semiconductor device according to the present invention will be described with reference to FIG. FIG. 7 shows the present invention in which an n-channel vertical power MOSF is used.
It is sectional drawing which shows the structure at the time of applying to ET. In addition,
In FIG. 7, the same components as those of the fourth embodiment shown in FIG. 6 are designated by the same reference numerals for convenience of description, and detailed description thereof will be omitted. That is, in the present embodiment, p directly below the LOCOS oxide film 7 in the gate finger portion.
The fourth embodiment is that the diffusion layer 6a has a higher impurity concentration and a deeper diffusion depth than the channel p-type diffusion layer 11a.
Except that the p-type diffusion layer 11b formed in the same step as the channel p-type diffusion layer 11a at the end of the LOCOS oxide film 7 and the gate electrode 15c extending from the gate finger portion to the chip termination portion side. It differs from the fourth embodiment in that an FFR using a p-type diffusion layer 11c formed in the same step as the channel p-type diffusion layer 11a is provided immediately below the gate oxide film 9b. The p-type diffusion layer 11b is provided so as to be in contact with the p-type diffusion layer 6a so as to relax the electric field strength on the surface of the p-type diffusion layer 6a, and a predetermined distance from the p-type diffusion layer 11c of FFR. It is provided to specify the distance.

The channel p-type diffusion layer 11a has a power MO.
It is formed by using the polycrystalline silicon gate layer 10a of the SFET as a mask. However, if the p-type diffusion layer enters the scribe line region, the breakdown voltage between the drain and the source is deteriorated. Therefore, as shown in FIG. 18 is used as a mask. Therefore, the p-type diffusion layer 11 for FFR
There is no need to add a new mask to form c. By adopting the structure with FFR, the p-type diffusion layer 6
Even if the impurity concentration of a is increased, the vertical power MOSFET can be realized without lowering the breakdown voltage. Also in this embodiment,
The same effect as that of the embodiment shown in FIG. 6 can be obtained.

<Embodiment 6> Another embodiment of the insulated gate semiconductor device according to the present invention will be described with reference to FIGS. FIG. 8 shows the present invention in which an n-channel vertical power MOS is used.
9 is a cross-sectional view showing the structure when applied to an FET, and FIG.
FIG. 9 is a sectional structural view of a main step showing a manufacturing method for realizing the structure shown in FIG. 8. 8 and 9, the same components as those of the first embodiment shown in FIG. 1 are designated by the same reference numerals for convenience of description, and detailed description thereof will be omitted. That is, in this embodiment, the thick LOCOS oxide film 7 formed by the selective oxidation method is not used as the thick field oxide film, but the thick insulating layer 7a obtained by the surface oxidation or the CVD method is patterned and used by the etching process. , Different from the first embodiment.

With this configuration, the LOCO
Since the step of forming the nitride film 4 required when forming the S oxide film 7 can be omitted, it is advantageous in terms of manufacturing cost and has the same effect as the embodiment of FIG.

Here, the manufacturing method of the n-channel vertical power MOSFET of this embodiment will be briefly described with reference to FIG. 9 by taking a breakdown voltage of 60 V as an example. First, for example, 0.002-0.02 Ω · doped with arsenic or antimony
After the n-type epitaxial layer 2 of 1 Ω · cm is formed to a thickness of 10 μm on the n ⁺ substrate 1 having a high concentration of about cm, for example, boron ions are ionized under the conditions of 50 keV and 1 to 5 × 10 ¹² cm ^−2. Implantation is performed to form a low-concentration p-type diffusion layer 6a on the surface of the n-type epitaxial layer 2 without a photomask. Next, the surface is oxidized or the CVD method is performed to obtain about 900
The insulating layer 7a having a thickness of 7 nm is formed and is etched by a photo process to obtain the structure shown in FIG.

Next, with the insulating layer 7a as a mask, phosphorus ion implantation is performed, for example, at 125 keV, 1.5 × 10 ^12.
The heat treatment is performed for about cm ⁻² and heat treatment is performed to simultaneously form the n-type diffusion layers 8a and 8b having a diffusion depth of about 2 μm. After that, gate oxidation is performed to form a thin gate oxide film 9a having a thickness of about 50 nm.
To form. Here, by setting the impurity concentration of the n-type diffusion layers 8a and 8b to a high concentration so as to cancel the p-type diffusion layer 6a, the p-type diffusion layer 6a is formed on the surface of the n-type epitaxial layer 2 where the thick oxide film 7a exists. On the surface of the n-type epitaxial layer 2 where there is no thick oxide film 7a.
8b can be formed in a self-aligned manner, and FIG.
The structure shown in is obtained. When implanting phosphorus ions to form the n-type diffusion layers 8a and 8b, a thin oxide film is formed to prevent damage, ion implantation is performed through this thin oxide film, and then the thin oxide film is removed. Then, the gate oxide film 9b may be newly formed.

Next, similarly to the step of FIG. 2C, polycrystalline silicon is deposited to a thickness of 350 nm by the well-known CVD method,
After patterning by a photo process to form the polycrystalline silicon layer 10a for the gate, the photoresist 18 is used as a mask on the side of the chip end portion 120 and the field portion 110,
On the active region side, using the polycrystalline silicon layer 10a as a mask, boron ions are ion-implanted under the conditions of about 50 keV and 5 × 10 ¹³ cm ^-2 , and then heat treatment is performed to form a p-type diffusion layer 11a for a channel. Then, the structure shown in FIG. 9C is obtained. After that, a normal power MOSFET process such as formation of an n-type diffusion layer 12a serving as a source using the polycrystalline silicon layer 10a as a mask, formation of an insulating layer 14, and opening of a contact hole is performed, so that FIG.
The cross-sectional structure shown in can be obtained.

<Embodiment 7> Referring to FIGS. 10 and 11,
Another embodiment of the insulated gate semiconductor device according to the present invention will be described. FIG. 10 is a cross-sectional view showing the structure when the present invention is applied to an n-channel vertical power MOSFET, and FIG. 10A is a plan view showing the main part of the vertical power MOSFET. The aluminum electrode is transparent and only the outline is shown and the surface protective film is omitted, and (b) is a sectional structural view of a portion taken along the line AA ′ on the plan view. Further, FIG. 11 is a sectional structural view of a main step showing a manufacturing method for realizing the structure shown in FIG. In addition, in FIG. 10 and FIG.
The same components as those of the first embodiment shown in
For convenience of description, the same reference numerals are given and detailed description thereof is omitted. That is, in the present embodiment, the chip termination portion 1
The difference from the first embodiment is that the polycrystalline silicon layer 10d is provided on the scribe line region at 20.

In the first embodiment, as shown in FIG. 2C, the photoresist for the ion implantation for the channel is formed so that the p-type diffusion layer 11a for the channel does not enter the scribe line in the chip end portion 120. A photo mask for 18 was used. On the other hand, in this embodiment, the p-channel structure is provided by the polycrystalline silicon layer 10d provided in the scribe region.
Since the shape diffusion layer 11a does not enter the drain region of the chip termination portion 120, the photomask for the photoresist 18 is not required, and one photomask can be saved.
This is advantageous in terms of reduction of manufacturing cost. The other effects are similar to those of the first embodiment.

As can be seen from the structure shown in FIG. 10B, the polycrystalline silicon layer 10d has a floating potential in this embodiment. However, since it is capacitively coupled to the drain region 8b through the thin gate oxide film 9a, when a voltage is applied between the drain and the source, the chip termination portion 120 is applied from the active region 100 side.
This has the effect of suppressing the extension of the depletion layer in the direction.

If a bonding pad is provided on the polycrystalline silicon layer 10d and this bonding pad is connected to a lead frame having a drain potential when assembling into a package, when the voltage is applied between the drain and the source, Since the effect of suppressing the extension of the depletion layer in the chip termination direction is further enhanced, deterioration of the drain-source breakdown voltage is less likely to occur.

Now, a method of manufacturing the n-channel vertical power MOSFET of this embodiment will be briefly described with reference to FIG. 11 by taking a breakdown voltage of 60 V as an example. In FIG. 11A, arsenic or antimony doped, for example, 0.
After the n-type epitaxial layer 2 of 1 Ω · cm is formed to a thickness of 10 μm on the n ⁺ substrate 1 having a high concentration of about 002 to 0.02 Ω · cm, and the surface oxide film 3 for preventing the surface damage due to the ion implantation is formed, The nitride film layer 4 is deposited. The surface oxide film 3 and the nitride film layer 4 are etched using the photoresist 5 as a mask in the photo process, and the nitride film layer 4 and the photoresist 5 are etched.
Is used as a mask, and, for example, boron ions at 50 keV,
Ions are implanted under the condition of about 1 to 5 × 10 ¹² cm ⁻² to form the low concentration p-type diffusion layer 6a.

Next, after removing the photoresist 5, selective oxidation is performed using the nitride film 4 as a mask to a thickness of about 900 nm.
LOCOS oxide film 7 is formed. Then, after removing the nitride film 4, phosphorus ion implantation is performed with the LOCOS oxide film 7 as a mask at, for example, 125 keV and 1.5 × 10 5.
^The heat treatment is performed for about ¹² cm ⁻² and heat treatment is performed to simultaneously form the n-type diffusion layers 8a and 8b having a diffusion depth of about 2 μm. The n-type diffusion layer 8a is for reducing the ON resistance, and the n-type diffusion layer 8b is for preventing the depletion layer extending from the active region 100 side from reaching the chip termination. Next, the surface oxide film 3 is removed, and new oxidation is performed to form gate oxide films 9a and 9c with a thickness of 50 nm.
The structure shown in (b) of is obtained.

Next, polycrystalline silicon is deposited to a thickness of 350 nm by a well-known CVD method, and patterned by a photo process to form a polycrystalline silicon layer 10a for a gate in the active region 100 and the field portion 110 and a chip terminal portion 120.
After the polycrystalline silicon layer 10d is formed on the polysilicon, the polycrystalline silicon layers 10a and 10d and the LOCO are formed without using a photoresist.
Using the S oxide film 7 as a mask, boron ions are 50 ke
Ion implantation under the condition of V, 5 × 10 ¹³ cm ^-2 ,
After that, heat treatment is performed to form the p-type diffusion layer 11a for the channel, and the structure shown in FIG. 11C is obtained. At this time, since the polycrystalline silicon layer 10d is provided in the scribe line forming region, the power MOS around the chip is formed.
The channel diffusion layer 11a is not diffused in the drain region of the FET. After that, the n-type diffusion layer 12a serving as a source using the polycrystalline silicon layer 10a as a mask is formed, the insulating layer 14 is formed, and contact holes are formed. The sectional structure shown in b) can be obtained.

<Embodiment 8> Another embodiment of the insulated gate semiconductor device according to the present invention will be described with reference to FIG. FIG. 12 shows an n-channel vertical power MOS according to the present invention.
It is sectional drawing which shows the structure at the time of applying to FET. Note that, in FIG. 12, the same components as those of the seventh embodiment shown in FIG. 10 are denoted by the same reference numerals for convenience of description, and detailed description thereof will be omitted. That is, in this embodiment, the p-type diffusion layer 6a immediately below the LOCOS oxide film 7 in the gate finger portion is replaced by the channel p-type diffusion layer 11a.
P-type diffusion layer 11b formed in the same step as the channel p-type diffusion layer 11a at the end of the LOCOS oxide film 7 in the gate finger portion.
And three F from the end of the gate electrode 15c of the gate finger portion to the end of the chip using the p-type diffusion layer 11c formed in the same step as the channel p-type diffusion layer 11a.
The difference from Example 7 is that FR is provided. The p-type diffusion layer 11b is provided so as to be in contact with the p-type diffusion layer 6a so as to relax the electric field strength on the surface of the p-type diffusion layer 6a, and the distance from the p-type diffusion layer 11c of the adjacent FFR is set. It is provided to regulate the distance. For channel p
The diffusion depth of the diffusion layer 11a depends on the impurity concentration and the LOCOS.
It can be set appropriately by controlling the formation time of the oxide film 7 or the diffusion time thereafter.

With this structure, the channel diffusion layer 11a can be formed without a mask as in the case of the seventh embodiment shown in FIG. 10, and even if the concentration of the p-type diffusion layer 6a is high, the p-type diffusion layer 11c can be used to form the layer. The decrease in breakdown voltage can be suppressed by the individual FFRs.

Since a photoresist cannot be used to form this FFR, four floating polycrystalline silicon layers 10c and 10d are used as masks.
In this embodiment, in order to prevent charge injection into the polycrystalline silicon layers 10c and 10d in the floating state, it is desirable to increase the number of FFRs and set the voltage between the FFRs to about 20V, which is lower than the gate breakdown voltage. Also in this embodiment, it is preferable that the polycrystalline silicon layer 10d at the end of the chip is provided with a bonding pad and is connected to a lead frame having a drain potential at the time of incorporation into the package rather than floating.

In the vertical power MOSFET of this embodiment,
When voltage is applied between the drain and source, FF
Since a voltage is applied uniformly between R, the breakdown voltage between the drain and source can be improved. Others have the same effects as the embodiment of FIG.

<Embodiment 9> Still another embodiment of the insulated gate semiconductor device according to the present invention will be described with reference to FIG. FIG. 13 shows an n-channel vertical power MOS according to the present invention.
It is sectional drawing which shows the structure at the time of applying to FET. Note that, in FIG. 13, the same components as those of the eighth embodiment shown in FIG. 12 are denoted by the same reference numerals for convenience of description, and detailed description thereof will be omitted. That is, this embodiment is different from the eighth embodiment in that the three FFRs are configured by using the p-type diffusion layer 6a.

With this structure, like the eighth embodiment, this embodiment can form the channel diffusion layer 11a without a mask and lowers the breakdown voltage even when the concentration of the p-type diffusion layer 6a is high. Vertical power MOSFE without
T can be formed.

Although the n-channel vertical power MOSFET has been described in the above embodiments, a p-channel vertical power MOSFET can be obtained by making the components of each conductivity type the components of opposite conductivity types. Of course.

Although the preferred embodiments of the insulated gate semiconductor device according to the present invention have been described above by taking the vertical power MOSFET as an example, the present invention is not limited to the above embodiments and deviates from the spirit of the present invention. It goes without saying that various design changes can be made within the range not covered. For example, n ⁺
A p ⁺ substrate is used instead of the substrate 1, and an n-type buffer layer and an n-type base region (the buffer layer has a higher concentration than the base layer) are formed on the p ⁺ substrate instead of the n-type epitaxial layer. Forms similar diffusion layers 6a, 8a, 10a, etc.,
The electrode 17 is a collector electrode, the electrode 15a is an emitter electrode,
If the electrode 15c is used as a gate electrode, it can be applied to an IGBT, and the present invention can be similarly applied to other insulated gate semiconductor devices.

[0074]

As is apparent from the above description, according to the present invention, the number of process steps can be reduced and the breakdown voltage between the drain and the source and the breakdown voltage between the gate and the source are not deteriorated, and the manufacturing cost can be reduced. An advantageous insulated gate semiconductor device can be obtained.

The insulated gate semiconductor device according to the present invention is thicker than the gate oxide film as compared with the conventional structure shown in FIG. 15 in which the gate electrode and polycrystalline silicon are connected on the gate oxide film. By connecting the gate electrode and the polycrystalline silicon on the field oxide film, it is possible to avoid a gate breakdown voltage defect such as a gate leak due to mechanical and electrical stress in the aluminum contact portion.

Further, in the insulated gate semiconductor device according to the present invention, even if the field oxide film thickness at the chip end portion is smaller than the field oxide film thickness at the peripheral portion of the active region, it is unlikely to be affected by breakdown voltage deterioration. Based on new knowledge, the field oxide film thickness at the chip termination portion is made thinner than the field oxide film thickness at the peripheral portion of the active region. Therefore, according to the method of manufacturing the insulated gate semiconductor device of the present invention, the drain-type
A low-concentration offset layer and a floating field ring are formed to increase the withstand voltage between the sources.
It can be formed using the oxide film or the polycrystalline silicon layer for the gate electrode as a mask. Therefore, it is possible to save the photoresist mask for the P well diffusion layer, which has been conventionally required.

Further, by adopting a structure in which the scribe region is covered with a polycrystalline silicon layer, impurities for the channel diffusion layer do not enter the scribe region, so that a conventionally required channel diffusion layer is formed. The photoresist mask can be saved.

Also in the insulated gate type semiconductor device according to the present invention, a LOCOS oxide film thicker than the gate oxide film can be formed under the polycrystalline silicon layer, and a diffusion layer having a conductivity opposite to that of the drain layer can be formed immediately below the LOCOS oxide film. Since a layer can be formed, LO
Even if a contact portion between the polycrystalline silicon layer for the gate electrode and the aluminum layer for the gate electrode or a polycrystalline silicon diode for electrostatic breakdown protection is formed on the COS oxide film, the gate-source breakdown voltage failure or the drain voltage fluctuation may occur. It is possible to suppress the characteristic variation of the polycrystalline silicon diode.

[Brief description of drawings]

1A and 1B are views showing a first embodiment of an insulated gate semiconductor device according to the present invention, in which FIG. 1A is a plan view of relevant parts, and FIG. 1B is a line AA ′ in the plan view. It is a sectional view of a part.

FIG. 2 is a cross-sectional view showing the main steps of the method of manufacturing the insulated gate semiconductor device according to the present invention in FIG. 1 in step order.

3 is a plan view schematically showing an entire chip of the insulated gate semiconductor device according to the present invention in FIG. 1. FIG.

FIG. 4 is a sectional view showing a second embodiment of the insulated gate semiconductor device according to the present invention.

FIG. 5 is a cross-sectional view showing a third embodiment of the insulated gate semiconductor device according to the present invention.

FIG. 6 is a cross-sectional view showing a fourth embodiment of an insulated gate semiconductor device according to the present invention.

FIG. 7 is a cross-sectional view showing a fifth embodiment of an insulated gate semiconductor device according to the present invention.

FIG. 8 is a sectional view showing a sixth embodiment of the insulated gate semiconductor device according to the present invention.

FIG. 9 is a cross-sectional view showing the main steps of the method of manufacturing the insulated gate semiconductor device according to the present invention in FIG. 8 in step order.

FIG. 10 is a seventh insulated gate semiconductor device according to the present invention.
Is a diagram showing an embodiment of the present invention, (a) is a plan view of the main part, (b)
[FIG. 4] is a cross-sectional view of a portion indicated by a line AA ′ in the plan view.

FIG. 11 is a cross-sectional view showing the main steps of the method for manufacturing the insulated gate semiconductor device according to the present invention in FIG. 10 in step order.

FIG. 12 is an eighth insulated gate semiconductor device according to the present invention.
It is sectional drawing which shows the Example of.

FIG. 13 is a ninth insulated gate semiconductor device according to the present invention.
It is sectional drawing which shows the Example of.

FIG. 14 is a diagram showing an example of a polycrystalline silicon diode that can be provided on an insulated gate semiconductor device according to the present invention, in which (a) is a plan view and (b) is A- in the plan view.
A sectional view taken along the line A ', and (c) is an equivalent circuit diagram.

15A and 15B are diagrams showing a conventional insulated gate semiconductor device, in which FIG. 15A is a plan view and FIG. 15B is a sectional view.

FIG. 16 is a diagram showing another example of a polycrystalline silicon diode that can be provided on an insulated gate semiconductor device according to the present invention, where (a) is a plan view and (b) is a plan view. −
It is sectional drawing in the A'line.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 ... High concentration n-type semiconductor substrate 2 ... N-type epitaxial layer 3 ... Surface oxide film 4 ... Nitride film 5,18 ... Photoresist 6a, 6b ... P-type diffusion layer 7 ... LOCOS oxide film 7a, 14 ... Insulating layer 8a, 8b ... n-type diffusion layers 9a, 9b, 9c ... gate oxide films 10a, 10b, 10c ... polycrystalline silicon layers 10d, 10e ... polycrystalline silicon layers 11a, 11b, 11c ... channel p-type diffusion layers 12a, 12b ... high concentration n-type diffusion layers 13a, 13b ... high-concentration p-type regions 15a, 15b, 15c ... metal electrode layer 16 ... surface protective film 17 ... metal electrode layer (drain electrode) 30, 32, 34, 36 ... contact hole 40 ... polycrystal Rectangular window part of silicon gate electrode 42 ... High-concentration p-type diffusion layer region 50 ... Protective diodes 52, 53 ... Contact hole 100 ... Active region 110 ... Feel Part 120 ... chip end

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Tetsuro Iijima 5-20-1 Kamimizuhonmachi, Kodaira-shi, Tokyo Hitachi, Ltd. Semiconductor Division

Claims (10)

[Claims] 1. A first impurity region and a second impurity region of a second conductivity type provided in a surface region of a semiconductor layer of the first conductivity type which becomes a drain, and a first impurity region of the second conductivity type which becomes a channel region. A third impurity region of the first conductivity type, which serves as a source, is provided in the impurity region, and a first insulating layer serving as a gate insulating film is formed on the first impurity region of the second conductivity type via a first insulating layer. In an insulated gate semiconductor device including a crystalline silicon gate layer and a metal layer serving as a source electrode and a gate electrode, the surface impurity concentration of the second impurity region of the second conductivity type is set to the first impurity region of the second conductivity type. And a second insulating layer thicker than the first insulating layer on the second impurity region of the second conductivity type, the polycrystalline silicon gate layer, and the polycrystalline silicon gate. Layers and the An insulated gate semiconductor device, wherein a contact for connecting to a metal layer to be a gate electrode is provided on the second insulating layer. 2. The insulated gate type according to claim 1, wherein the first impurity region of the second conductivity type and the second impurity region of the second conductivity type are separated by a fourth impurity region of the first conductivity type. Semiconductor device. 3. A first impurity region and a second impurity region of a second conductivity type which are provided on the surface of a semiconductor layer of the first conductivity type which serves as a drain, and a first impurity region of the second conductivity type which serves as a channel region.
A third impurity region of the first conductivity type, which serves as a source, is provided in the impurity region, and a first insulating layer serving as a gate insulating film is formed on the first impurity region of the second conductivity type via a first insulating layer. In an insulated gate semiconductor device comprising a crystalline silicon gate layer and a metal layer serving as a source electrode and a gate electrode, a second insulating layer thicker than the first insulating layer on the second impurity region of the second conductivity type, The polycrystalline silicon gate layer is provided on the second insulating layer, and a contact connecting the polycrystalline silicon gate layer and the metal layer to be the gate electrode is provided on the second insulating layer, and the second insulating layer is provided. The fifth of the second conductivity type formed in the same step as the second impurity region of the conductivity type
An insulated gate type semiconductor device, wherein a floating field ring using an impurity region is provided in the semiconductor layer of the first conductivity type around the active region. 4. A first impurity region and a second impurity region of a second conductivity type provided on the surface of a semiconductor layer of the first conductivity type which becomes a drain, and a first impurity region of the second conductivity type which becomes a channel region.
A third impurity region of the first conductivity type, which serves as a source, is provided in the impurity region, and a first insulating layer serving as a gate insulating film is formed on the first impurity region of the second conductivity type via a first insulating layer. In an insulated gate semiconductor device comprising a crystalline silicon gate layer and a metal layer serving as a source electrode and a gate electrode, a second insulating layer thicker than the first insulating layer on the second impurity region of the second conductivity type, The polycrystalline silicon gate layer is provided on the second insulating layer, and a contact connecting the polycrystalline silicon gate layer and the metal layer to be the gate electrode is provided on the second insulating film layer, and the contact is provided. A floating field ring using a second impurity type sixth impurity region formed in the same step as the second conductivity type first impurity region is provided in the first conductivity type semiconductor layer around the active region. An insulated gate semiconductor device characterized by: 5. The insulated gate semiconductor device according to claim 1, further comprising a polycrystalline silicon diode provided on the second insulating layer. 6. The insulated gate semiconductor device according to claim 1, wherein the first insulating layer and the polycrystalline silicon gate layer are further provided in a scribe line formation region. 7. The semiconductor device according to claim 6, wherein the polycrystalline silicon layer on the scribe line formation region is set to the same potential as that of the first conductivity type semiconductor layer serving as the drain. 8. A first impurity region and a second impurity region of a second conductivity type provided on the surface of a semiconductor layer of the first conductivity type to be a drain, and a first impurity region of the second conductivity type to be a channel region.
A third impurity region of the first conductivity type, which serves as a source, is provided in the impurity region, and a first insulating layer serving as a gate insulating film is formed on the first impurity region of the second conductivity type via a first insulating layer. A second insulating layer, which is made of a crystalline silicon gate layer and a metal layer serving as a source electrode and a gate electrode, and is thicker than the first insulating layer on the second impurity region of the second conductivity type;
In the method for manufacturing an insulated gate semiconductor device, the polycrystalline silicon gate layer and a contact connecting the polycrystalline silicon gate layer and a metal layer to be the gate electrode are provided on the second insulating layer. The nitride film formed on the surface of the semiconductor layer of the first conductivity type is used as a mask to introduce impurities into the second impurity region of the second conductivity type, and then the selective oxidation is further performed using the nitride film as a mask. A method of manufacturing an insulated gate semiconductor device, comprising at least a step of forming the second insulating layer. 9. A first impurity region and a second impurity region of a second conductivity type provided on the surface of a semiconductor layer of the first conductivity type which becomes a drain, and a first impurity type of the second conductivity type which becomes a channel region.
A third impurity region of the first conductivity type, which serves as a source, is provided in the impurity region, and a first insulating layer serving as a gate insulating film is formed on the first impurity region of the second conductivity type via a first insulating layer. A second insulating layer, which is made of a crystalline silicon gate layer and a metal layer serving as a source electrode and a gate electrode, and is thicker than the first insulating layer on the second impurity region of the second conductivity type;
In the method for manufacturing an insulated gate semiconductor device, the polycrystalline silicon gate layer and a contact connecting the polycrystalline silicon gate layer and a metal layer to be the gate electrode are provided on the second insulating layer. Using the nitride film formed on the surface of the semiconductor layer of the first conductivity type as a mask, impurities are introduced into the second impurity region of the second conductivity type, and then selective oxidation is further performed using the nitride film as a mask. A method of manufacturing an insulated gate semiconductor device, comprising: forming a second insulating layer, and then forming a fourth impurity region of the first conductivity type by using the second insulating layer as a mask. 10. A first impurity region of a second conductivity type and a second impurity region provided on the surface of a semiconductor layer of the first conductivity type, which serves as a drain.
An impurity region, a third impurity region of the first conductivity type serving as a source, which is provided in the first impurity region of the second conductivity type serving as a channel region, and a first impurity region of the second conductivity type; The polycrystalline silicon gate layer provided via a first insulating layer serving as a gate insulating film and a metal layer serving as a source electrode and a gate electrode are provided on the second impurity region of the second conductivity type. A second insulating layer thicker than the insulating layer is provided, and the polycrystalline silicon gate layer and a contact connecting the polycrystalline silicon gate layer and the metal layer to be the gate electrode are provided on the second insulating layer. In the method of manufacturing an insulated gate semiconductor device, first, a second impurity region of a second conductivity type is formed on the entire surface of the semiconductor layer of the first conductivity type, then the second insulation layer is formed, and then the second insulating layer is formed. 2 With the insulating layer as a mask, At least forming a first insulating layer to be a gate insulating film after forming a fourth impurity region of the first conductivity type by introducing impurities so as to cancel the second impurity region of the second conductivity type; A method for manufacturing an insulated gate semiconductor device, comprising: