JPH1050933A - Input protective circuit - Google Patents

Abstract

PROBLEM TO BE SOLVED: To simultaneously form a transistor for an internal circuit and a transistor for an input protective circuit with a quick snap-back breakdown. SOLUTION: A cross gate electrode 6b is formed and source/drain impurity diffusion layers on both sides of the gate electrode 6b are made low concentration impurity diffusion layers 18b, 19b and high concentration impurity diffusion layers 4b, 9b so as to facilitate generation of an electric field concentration by means of a B-point where the gate electrode 6b is crossing inspite of a transistor for an input protective circuit of an LDD structure. Thereby, formation of a transistor for input protection with quick snap-back brakedown becomes possible as well as formation of an impurity diffusion layer of a transistor for an input protective circuit becomes possible by the same process with an ion implantation process for forming an impurity diffusion of a peripheral transistor provided with the LDD structure.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an input protection circuit, and more particularly to an input protection circuit for protecting an internal circuit, which is a main functional part, from an external surge such as static electricity applied to an input terminal. It is something.

[0002]

2. Description of the Related Art An example of a conventional input protection circuit will be described below. FIG. 3 is an equivalent circuit showing an example of a conventional input protection circuit, and FIG. 4 is a plan view of the conventional input protection circuit.

In FIG. 4, an input bonding pad 2
An input wire (not shown) is bonded to 6, and is connected to a drain diffusion layer 35 of an element active region 29 via a metal wiring layer 28 via contacts 24 and 27.

Further, the gate electrode 30 of the MOS transistor in the element active region 29 is connected via a contact 31 to a metal wiring layer 32 at the ground potential. The source diffusion layer 33 of the MOS transistor is connected to the metal wiring layer 32 via the contacts 25 and 34.

Then, a contact D (metal wiring layer 3) shown in FIG.
The peak voltage of the external surge applied from the input terminal is reduced by the time constant τ = C * R determined by the parasitic capacitance C existing in 5) and the resistance value R of the impurity diffusion resistor 36, and the MOS transistor 29 By using snap breakdown to release the surge charge and reduce the voltage at the contact D, the input circuit 37 is configured to prevent the gate oxide film and the like of the transistor from being destroyed.

In order to improve the integration of a MOS integrated circuit, it is inevitable to make the MOS transistor finer. On the other hand, as the miniaturization is advanced, the channel length is shortened, so that the hot electron effect becomes remarkable, and there is a problem that the reliability of the MOS transistor is reduced.

For this reason, recently, an LDD (Lightly Doped Drain) structure is used to reduce the electric field concentration at the end of the gate electrode. However, if the MOS transistor 29 used as an input protection element has an LDD structure as shown in FIG. 3, the operation of snapback breakdown caused by a leakage current generated due to the electric field concentration at the gate electrode end becomes slow.

Therefore, the external surge applied from the input terminal does not escape from the MOS transistor 29, and causes the gate oxide film and the like of the transistor of the input circuit 37 to be destroyed. In order to prevent such a problem from occurring, conventionally, only the impurity diffusion layer region of the MOS transistor of the input protection element having a fast snapback breakdown operation has a single drain structure.

[0009]

For this reason, conventionally, an ion implantation process for forming an impurity diffusion layer region of a MOS transistor having an LDD structure of an internal circuit and a MOS transistor having a single drain structure of an input protection element is separately performed. I needed to.

Therefore, in the conventional semiconductor device, when an input protection circuit having a transistor having a single drain structure and an MOS transistor having an LDD structure as an internal circuit are formed simultaneously, it is difficult to simplify the manufacturing process. There was a problem.

An object of the present invention is to provide an input protection circuit capable of simplifying a manufacturing process of a semiconductor device including an internal circuit and an input protection circuit.

[0012]

According to the input protection circuit of the present invention, in an element active region, at least two gate electrodes intersect at a certain point and at least four impurity diffusion layer regions sandwich the gate electrode. In addition, the two gate electrodes are connected in the element active region, and in the element active region, a low-concentration impurity diffusion layer and a high-concentration impurity diffusion layer are formed in an impurity diffusion layer region formed across the gate electrode. Is provided.

[0013]

Since the present invention comprises the above technical means, it is possible to increase the electric field at the gate electrode end at the intersection by intersecting two or more gate electrodes in the element active region. Leakage current flows from the impurity diffusion layer region to the substrate connected to the ground potential, and even if the input protection transistor has the LDD structure, the snapback breakdown operation is accelerated. Through the input protection circuit to GND. Therefore, when the input protection circuit of the present invention is used, it is possible to simultaneously perform the ion implantation process for forming the impurity diffusion layer regions of the MOS transistor of the internal circuit and the MOS transistor of the input protection circuit.

[0014]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the input protection circuit according to the present invention will be described below with reference to the drawings. FIG. 1 is a plan view of an input protection circuit according to an embodiment of the present invention, and FIG. 2 is a manufacturing process diagram showing a manufacturing process of a transistor of a peripheral circuit and a transistor of the input protection circuit. The left part of FIG. 2 shows a manufacturing process of a transistor of a peripheral circuit, and the right part of FIG. 2 shows a manufacturing process of a transistor of an input protection circuit.

The line AA 'in FIG. 1 shows a manufacturing process of the input protection circuit on the right side of FIG. As shown in FIG. 1, for example, a 100 μm square input bonding pad 1 is connected to a drain impurity diffusion layer 4 b of an input protection transistor formation region 3 through a 2.0 μm diameter contact 2 b.
And the metal wiring layer 5.

The gate electrode 6b crosses at a point B on the impurity diffusion layer region surrounded by the field oxide film 15. The high-concentration impurity diffusion layer 9b as the drain region is connected to the metal wiring layer 8b at the ground potential through the contact hole 10b, and the high-concentration impurity diffusion layer 4b as the source region is connected to the metal through the contact hole 2b. It is connected to the wiring layer 5b.

That is, the input protection transistor forming region 3 which can be connected to the input bonding pad 1 which is the input terminal of the device body to be protected and which is partitioned by the field oxide film 15 formed on the P-type silicon substrate 40
And a MOS transistor having a source region and a drain region provided in the input protection transistor formation region 3, wherein at least two or more gate electrodes 6
b intersect at a certain point on the input protection transistor formation region 3, and at least four impurity diffusion layer regions 4b, 9
b.

Further, only one section of the impurity diffusion layer 4b is connected to the input bonding pad 1, and
The divided impurity diffusion layer 9b is formed of the metal wiring layer 8b at the ground potential.
Is connected to Similarly, the gate electrode 6b is connected to the metal wiring layer 8b at the ground potential via the contact hole 7.

Next, a method of manufacturing the input protection circuit according to the present embodiment will be described with reference to FIGS. First, FIG.
As shown in FIG. 5, a field oxide film 15 is formed by a LOCOS method so as to surround a formation region 30 of a peripheral transistor and a formation region 3 of an input protection transistor on a P-type silicon substrate 40.

Thereafter, as shown in FIG. 2B, gate oxide films 16a and 16b having a thickness of 170 ° are formed on the P-type silicon substrate 40 by a thermal oxidation method. Thereafter, a polycrystalline silicon film (not shown) containing impurities is deposited on the gate oxide films 16a and 16b by a CVD method.

By patterning a polycrystalline silicon film (not shown) by a photolithography technique and an etching technique, a gate made of a polycrystalline silicon film (not shown) is formed in a peripheral transistor formation region 30 on a P-type silicon substrate 40. In addition to forming the electrode 6a, a cross-shaped gate electrode 6b made of a polycrystalline silicon film as shown in FIG. 1 is formed in the formation region 3 of the input protection transistor.

Thereafter, these gate electrodes 6a, 6b
Is used as a mask, phosphorus (P) is ion-implanted into the P-type silicon substrate 40 on both sides of the gate electrodes 6a and 6b at an acceleration voltage of 80 keV and a dose of about 2.0E13 (/ cm ² ) to form the gate electrodes 6a and 6b. Low concentration impurity diffusion layer 1 in which phosphorus is distributed at a low concentration in P type silicon substrates 40 on both sides of
8a, 18b, 19a and 19b are formed respectively.

Thereafter, the gate electrode 6 is formed by CVD.
After a silicon oxide film is formed on the P-type silicon substrate 40 including the silicon oxide films a and 6b, the silicon oxide film is anisotropically etched to form a sidewall oxide film 20 made of the silicon oxide film on the side wall of the gate electrode 6a. Is formed, and sidewall oxide films 21 made of a silicon oxide film are formed on the side walls of the gate electrode 6b.

Thereafter, P on both sides of the gate electrodes 6a, 6b
(As) is accelerated on the silicon substrate 40 at an acceleration voltage of 70 ke.
v, a high-concentration impurity diffusion layer 4a, 9a in which arsenic serving as a source / drain is distributed at a high concentration in a peripheral transistor formation region by ion-implanting to a dose of about 1.0E16 (/ cm ² ); High concentration impurity diffusion layer 4 serving as a drain in the input protection transistor formation region
b and a high-concentration impurity diffusion layer 9b serving as a source are respectively formed.

Next, as shown in FIG. 2C, an interlayer insulating film 41 is formed on the P-type silicon substrate 40 including the gate electrodes 6a and 6b. Next, contact holes 2a, 2b, 1 are formed in interlayer insulating film 41 and gate oxide films 16a, 16b.
0a and 10b are formed respectively. These contact holes 2a and 2b reach the high-concentration impurity diffusion layers 4a and 4b, and the contact holes 10a and 10b are formed to reach the high-concentration impurity diffusion layers 9a and 9b.

Further, as shown in FIG. 1, a contact hole 7 reaching the gate electrode 6b formed over the field oxide film 15 is formed in the interlayer insulating film 41. Next, at least the contact holes 2a, 2b, 10a,
A metal film such as aluminum is deposited on the interlayer insulating film 41 so as to cover the inner surface of 10b.

Thereafter, by patterning this metal film by photolithography and etching, metal wiring layers 5a and 5b connected to impurity diffusion layers 4a and 4b via contact holes 2a and 2b are formed.
And metal wiring layers 8a and 8b connected to the impurity diffusion layers 9a and 9b via the contact holes 10a and 10b, respectively.

The metal wiring layer 8b connected to the impurity diffusion layer 9b via the contact hole 10b and the gate electrode 6b via the contact hole 7 is connected to the ground potential (GND) as shown in FIG. The wiring 5b is
Connected to input bonding 1 on m sides. The metal wiring 5b connecting the input bonding pad 1 and the impurity diffusion layer 4b is a part of a wiring connected to an internal circuit.

Through the above manufacturing steps, the input protection transistor including the peripheral transistor and the transistor whose gate electrode 6b crosses in the element active region of the P-type silicon substrate 40 is completed.

In the present embodiment, the gate electrode 6b is formed as a cross-shaped gate electrode. However, the gate electrode 6b may have a corner or an acute-angled object. In addition, triangle,
A polygonal gate electrode such as a quadrangle or a pentagon, a star-shaped gate electrode 6b, or a radiation-shaped gate electrode 6b may be formed.

Similarly, when forming the gate electrode 6b, if the input protection transistor can be formed so as to have the LDD structure, it becomes possible to simultaneously form the peripheral transistors having the LDD structure.

As described above, in the transistor of the input protection circuit according to the present invention, in the element active region, at least two gate electrodes cross at a certain point, and the two gate electrodes are connected. At least on both sides of the two gate electrodes, a low concentration impurity diffusion layer and a high concentration impurity diffusion layer are provided.

As a result, even in the input protection circuit including the transistor having the LDD structure, the electric field concentration is increased at the intersection of the gate electrodes, so that the leak current can flow well into the impurity diffusion layer connected to the ground potential. become. This makes it possible to realize an input protection circuit in which the snap-back breakdown operation becomes faster,
The ion implantation process for forming the impurity diffusion layers of the peripheral transistor having the D structure and the input protection transistor can be performed simultaneously.

[0034]

According to the present invention, as described above, according to the present invention, an ion implantation step for forming an impurity diffusion layer region of a MOS transistor of an internal circuit having an LDD structure and a transistor for an input protection circuit is performed simultaneously. As a result, the manufacturing process of the semiconductor device having the transistor for the input protection circuit having a fast snapback breakdown can be simplified, and the manufacturing cost can be reduced.

[Brief description of the drawings]

FIG. 1 is a partial plan view of a semiconductor input protection circuit according to an embodiment of the present invention.

FIG. 2 is a partial cross-sectional view showing an example of a semiconductor input protection circuit according to the embodiment.

FIG. 3 is an equivalent circuit diagram showing an example of a conventional semiconductor input protection circuit.

FIG. 4 is a partial plan view showing an example of a conventional semiconductor input protection circuit.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 1 Input bonding pad 2b Contact hole 3 Input protection transistor formation region 4b High concentration impurity diffusion layer 5b Metal wiring layer 6b Gate electrode 7 Contact hole 8b Metal wiring layer 9b High concentration impurity diffusion layer 10b Contact hole 15 Field oxide film 18b Low-concentration impurity diffusion layer 19b Low-concentration impurity diffusion layer 30 Peripheral transistor formation region 40 P-type silicon substrate

Claims (1)

[Claims] In an element active region, at least two gate electrodes intersect at a certain point, and at least four impurity diffusion layer regions are divided with at least the gate electrode interposed therebetween. In the device active region, a low-concentration impurity diffusion layer and a high-concentration impurity diffusion layer are provided in an impurity diffusion layer region formed with the gate electrode interposed therebetween. Input protection circuit.