JP2007294765A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a means of lowering the breakdown voltage of an SCR element used for the ESD protective circuit of a semiconductor device of SOI structure. <P>SOLUTION: The semiconductor device is equipped with a p-type silicon substrate, a buried insulating layer formed on the p-type silicon substrate, an SOI layer formed on the buried insulating layer, an n-well layer formed by diffusing n-type impurities into the p-type silicon substrate, a first p-type diffusion layer and a first n-type diffusion layer formed in the n-well layer, a second p-type diffusion layer and a second n-type diffusion layer formed in the p-type silicon substrate separating from the n-well layer, an anode electrode to the first p-type diffusion layer penetrating through the SOI layer and the buried insulating layer, an n-well electrode reaching to the first n-type diffusion layer, a cathode electrode to the second diffusion layer, and a substrate electrode reaching to the second p-type diffusion layer. Furthermore, a conductive diffusion layer formed by diffusing conductive impurities is provided in the SOI layer located between the anode electrode and the cathode electrode. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

  The present invention relates to a semiconductor device having an SOI (Silicon On Insulator) structure having an ESD (Electro Static Discharge) protection element using an SCR (Silicon Controlled Rectifier) element that protects an internal circuit, and a manufacturing method thereof.

  Generally, in a semiconductor device, when a high voltage (referred to as a surge voltage) exceeding the breakdown voltage is applied to a signal terminal electrically connected to an internal circuit from the outside due to static electricity or a lightning strike, an excessive current is applied to the internal circuit. In order to prevent current from flowing, an ESD protection circuit is inserted between the signal terminal and the internal circuit to bypass the large current caused by the surge voltage, and the current flowing in the internal circuit is reduced to the rated current or less to reduce the current from the large current to the internal circuit. It has been done to protect.

As an ESD protection circuit, a MOSFET (Metal Oxide Semiconductor) Effect Transistor (PN), a PN diode, or an SCR element is generally used. However, the SCR element has a relatively small area, a small holding voltage, and a small on-resistance. Is widely used because of its high ESD protection function.
On the other hand, along with the recent increase in the speed and density of semiconductor devices, semiconductor elements such as MOSFETs (referred to as internal elements) used in internal circuits have become finer, and MOSFET gate lengths have been shortened. Semiconductor devices having an SOI structure that suppresses the short channel effect associated with miniaturization have become mainstream. Along with such miniaturization, the breakdown voltage of the internal elements constituting the internal circuit tends to decrease, and it is expected that the breakdown voltage of the SCR elements provided in the SOI structure semiconductor device is lowered.

  In order to lower the breakdown voltage of the SCR element, a conventional semiconductor device has a P-type diffusion layer and an N-type diffusion layer formed on an N well layer and a P well layer formed on a bulk substrate made of silicon, respectively. An SCR element is formed, and a gate electrode is formed on the gate insulating film formed between the N-type diffusion layer of the N-well layer and the N-type diffusion layer of the P-well layer to form an nMOS element. A control circuit consisting of a capacitor and a resistor is provided between the gate electrode and the signal terminal, and the SCR element functions by using a breakdown generated in the nMOS element as a trigger when a surge current is applied to the signal terminal. It is protected from breakdown due to voltage (for example, see Patent Document 1).

  Further, when an LVTSCR (Low Voltage Triggering SCR) in which a MOSFET is combined with an SCR element is formed on a bulk substrate, an impurity profile of the MOSFET is extracted from the snapback characteristics of the MOSFET, and the dimensions of the SCR element are correspondingly extracted. In some cases, the breakdown voltage of the SCR element is reduced (see, for example, Patent Document 2).

In the case of such an ESD protection circuit using an SCR element formed on a bulk substrate, the bulk substrate on which the internal element is formed is heated by heat generation of the SCR element when a large current due to a surge voltage is bypassed. There is a concern that the thermal effect may affect the internal elements.
In order to prevent such a thermal effect, the conventional semiconductor device forms an SOI structure by stacking a buried insulating layer and an SOI layer on a silicon substrate, and forms a diffusion layer on the silicon substrate below the buried insulating layer. Then, on the P-type silicon substrate in which the P-type impurity is diffused by using a technique (for example, refer to Patent Document 3) for forming a conductive plug penetrating the SOI layer and the buried insulating layer on the diffusion layer. The first P-type diffusion layer is formed on the surface layer of the N-well layer formed by diffusing N-type impurities in the P-type silicon substrate below the buried insulating layer of the SOI structure semiconductor substrate in which the buried insulating layer and the SOI layer are stacked. And a first N-type diffusion layer, and a second P-type diffusion layer and a second N-type diffusion layer are formed on the surface layer of the P-type silicon substrate in the vicinity of the N-well layer. On each diffusion layer formed on the substrate, an SOI layer and A conductive plug that penetrates the buried insulating layer and reaches each type of diffusion layer is formed to function as an SCR element to efficiently dissipate heat generated when a large current due to surge voltage is bypassed (for example, a patent) Reference 4).
JP-A-10-92951 (page 4, paragraph 0009 to page 5, paragraph 0015, FIG. 1) JP 2005-251874 A (paragraph 0029-0031 on the sixth page and paragraphs 0044-0046 on the eighth page, FIG. 2) JP-A-10-321868 (5th page paragraph 0028-6th page paragraph 0039, FIG. 2) JP 2002-270687 (3rd page paragraph 0008 and 6th page paragraph 0027-7th page paragraph 0032, FIG. 8)

  However, in the technique of the above-mentioned conventional patent document 4, although the SCR element is formed on the P-type silicon substrate and the heat generated by the bypassed large current is efficiently dissipated, as described above, the destruction of the internal element When the breakdown voltage is low, it is necessary to flow a large current through the SCR element before the internal element breaks down, and the breakdown voltage of the SCR element must be sufficiently lowered in a semiconductor device using an SOI structure semiconductor substrate. It becomes a challenge.

  In this case, when the ESD protection circuit is formed using the nMOS element as in Patent Document 1, a channel is formed in the channel region of the nMOS element constituting the ESD protection circuit in the normal operation (for example, 1.5 V). In order to prevent leakage current, the threshold voltage must be higher than the rated voltage of the internal element, and the SOI layer must be thick (for example, about 0.1 μm). If the SOI layer is thickened to prevent leakage current, the short channel effect is not sufficiently suppressed, and the internal circuit cannot be densified.

For this reason, when a control circuit for controlling the gate voltage of the nMOS element of the ESD protection circuit is provided, a space for providing a capacitor and a resistor constituting the control circuit must be secured, and there is a problem that the semiconductor device is increased in size. .
The present invention has been made to solve the above problems, and an object of the present invention is to provide means for reducing the breakdown voltage of an SCR element used in an ESD protection circuit of a semiconductor device having an SOI structure.

  In order to solve the above problems, the present invention provides a P-type silicon substrate, a buried insulating layer formed on the P-type silicon substrate, an SOI layer formed on the buried insulating layer, and the P-type silicon. An N well layer formed by diffusing an N type impurity in the substrate, a first P type diffusion layer and a first N type diffusion layer formed in the N well layer, and spaced apart from the N well layer; The second P-type diffusion layer and the second N-type diffusion layer formed on the P-type silicon substrate, and the anode electrode that penetrates the SOI layer and the buried insulating layer and reaches the first P-type diffusion layer A semiconductor device comprising: an N well electrode reaching the first N type diffusion layer; a cathode electrode reaching the second N type diffusion layer; and a substrate electrode reaching the second P type diffusion layer. , SOI between the anode electrode and the cathode electrode To, is characterized by providing a conductive impurity is formed by diffusing a conductive diffusion layer.

  As a result, the present invention can guide surge voltage to the conductive diffusion layer and inject charge into the depletion layer formed in the P-type silicon substrate under the buried insulating layer, and invert the depletion layer under the buried insulating layer. The SCR element can be operated with a low breakdown voltage triggered by the application of a surge voltage, and the internal circuit is bypassed and a large current due to the surge voltage is passed through the P-type silicon substrate to heat the SOI layer. The effect can be reduced, and the internal circuit can be protected from the surge voltage.

  Embodiments of a semiconductor device and a manufacturing method thereof according to the present invention will be described below with reference to the drawings.

FIG. 1 is an explanatory view showing a cross section of the semiconductor device of the embodiment, and FIGS. 2 and 3 are explanatory views showing a method of manufacturing the semiconductor device of the embodiment.
FIG. 1 shows a cross section in the vicinity of one SCR element formed in a semiconductor device. Also, the broken line shown in FIG. 1 shows the connection state of each electrode. In FIG. 1, reference numeral 1 denotes a semiconductor substrate having an SOI structure, which is made of boron (B) or aluminum (Al) at a relatively low concentration in relatively thick silicon. A film thickness of 0 made of an insulating material such as silicon oxide (SiO ₂ ) on a silicon substrate 2 (referred to as P-type silicon substrate 2) in which a P-type conductive impurity (referred to as P-type impurity) is uniformly diffused. A buried insulating layer 3 having a thickness of about 2 μm is laminated, and an SOI layer 4 in which a relatively low concentration P-type impurity is uniformly diffused is laminated on thin silicon having a thickness of about 0.05 μm. In the SOI layer 4, internal elements constituting the internal circuit of the semiconductor device are formed.

  Reference numeral 5 denotes an nMOS element as an internal element, a gate electrode 7 made of polysilicon or the like disposed opposite to the SOI layer 4 via a gate insulating film 6 made of silicon oxide or the like formed on the SOI layer 4, and a gate electrode The side wall 8 made of silicon oxide or the like formed on both side surfaces of the gate electrode 7 and N-type conductive impurities (referred to as N-type impurities) such as relatively high concentration phosphorus (P) or arsenic (As) on both sides of the gate electrode 7. .) Is formed by a source electrode 11 and a drain electrode 12 formed of a conductive material such as tungsten (W) on the source layer 9 and the drain layer 10. The SOI layer 4 in which a low-concentration P-type impurity is diffused under the gate electrode 7 sandwiched between the source layer 9 and the drain layer 10 is used as the channel region 13 of the nMOS element 5. And ability, when the rated voltage is applied to the gate electrode 7, the channel formed in the channel region 13 has a function of controlling the current flowing between the source layer 9 and the drain layer 10.

A signal terminal 15 is a terminal for transmitting and receiving signals between the internal circuit and the outside, and is connected to the drain electrode 12 of the nMOS element 5 as an internal element. The source electrode 11 and the gate electrode 7 of the nMOS element 5 are electrically connected to predetermined portions of the internal circuit, respectively.
Reference numeral 20 denotes an SCR element, which includes an N well layer 21 formed by partially diffusing a low concentration N type impurity in a P type silicon substrate 2 in which a low concentration P type impurity is diffused, A first P-type diffusion layer 22 formed by diffusing high-concentration P-type impurities in the surface layer; a first N-type diffusion layer 23 formed by diffusing high-concentration N-type impurities; and P-type silicon A second P-type diffusion layer 24 formed by diffusing high-concentration P-type impurities in a surface layer that is separated from the N-well layer 21 of the substrate 2 and in the vicinity thereof, and formed by diffusing high-concentration N-type impurities. The second N-type diffusion layer 25, the SOI layer 4 and the buried insulating layer 3, and the first and second P-type diffusion layers 22 and 24 and the first and second N-type diffusion layers 23, Four electrode insulating films 27 made of silicon oxide or the like reaching 25 are lined up on the inner peripheral surface. An anode electrode 32 reaching the first P-type diffusion layer 22 formed by embedding a conductive material in the pole hole 28, an N-well electrode 33 reaching the first N-type diffusion layer 23, and a second P-type diffusion A substrate electrode 34 reaching the layer 24, a cathode electrode 35 reaching the second N-type diffusion layer 25, and a high-concentration N-type impurity are diffused in the SOI layer 4 between the anode electrode 32 and the cathode electrode 35. The conductive diffusion layer 37 is formed, and a control electrode 38 formed of a conductive material immediately above the conductive diffusion layer 37 and the like.

  The first P-type diffusion layer 22, the first N-type diffusion layer 23 and the conductive diffusion layer 37 of the SCR element 20 are directly connected to the signal terminal 15 via the anode electrode 32, the N-well electrode 33 and the control electrode 38. The second P-type diffusion layer 24 and the second N-type diffusion layer 25 are connected to the ground (VSS) or the power supply voltage (VDD) via the cathode electrode 35 and the substrate electrode 34. Thereby, the SCR element 20 functions as an ESD protection element of the present embodiment.

A method for manufacturing the semiconductor device of this example will be described below in accordance with the process indicated by P in FIGS.
P1 (FIG. 2), a semiconductor wafer 40 comprising a semiconductor substrate 1 laminated on a P-type silicon substrate 2 with a buried insulating layer 3 and an SOI layer 4 in which a low-concentration P-type impurity is diffused is prepared. 4, an SCR formation region 41 and an internal circuit formation region 42 are set, and a formation region of the N well layer 21 (referred to as an N well formation region 43) is set in the SCR formation region 41.

Then, a thin protective oxide film 44 made of silicon oxide is formed on the SOI layer 4 of the semiconductor wafer 40 by a thermal oxidation method or the like.
P2 (FIG. 2), a resist mask 46 covering the region excluding the N well formation region 43 is formed on the protective oxide film 44 by photolithography, and using this as a mask, the peak of the implantation ion distribution is the upper surface of the P-type silicon substrate 2, In other words, an N well layer 21 is formed on the P type silicon substrate 2 by ion-implanting a low concentration N type impurity with an implantation energy below the interface with the buried insulating layer 3.

Since the SOI layer 4 in this embodiment has a film thickness of 0.05 μm and the buried insulating layer 3 has a film thickness of 0.2 μm, an implantation energy that causes the peak of the implanted ion distribution to be larger than 0.25 μm from the upper surface of the SOI layer 4 is used. .
After removing the resist mask 46 formed in P3 (FIG. 2) and step P2, the protective oxide film 44 is removed, and a silicon oxide film 47 for forming the gate insulating film 6 on the SOI layer 4 by a thermal oxidation method or the like is formed. A polysilicon layer is formed on the polysilicon layer by a CVD (Chemical Vapor Deposition) method, and a resist mask 46 (not shown) covering the formation region of the gate electrode 7 is formed on the polysilicon layer by photolithography. The polysilicon layer is etched by anisotropic etching as a mask to expose the silicon oxide film 47, and the gate electrode 7 of the nMOS element 5 is formed.

  The resist mask 46 formed in P4 (FIG. 2) and process P3 is removed, and the electrode hole 28 on the N well layer 21 and the electrode hole 28 on the P-type silicon substrate 2 in the SCR formation region 41 are formed by photolithography. A resist mask 46 having an opening is formed, and using this as a mask, the silicon oxide film 47, the SOI layer 4 and the buried insulating layer 3 are etched by anisotropic etching, penetrating the SOI layer 4 and the buried insulating layer 3, and N A total of four electrode holes 28 are formed, two each reaching the well layer 21 and the P-type silicon substrate 2.

Then, the resist mask 46 for forming the electrode hole 28 is removed, and a thick silicon film made of silicon oxide for forming the sidewall 8 on the gate electrode 7 and the SOI layer 4 by thermal oxidation. An oxide film 48 is formed.
At this time, the silicon oxide film 48 is also formed on the inner peripheral surface and the bottom surface of the electrode hole 28.
P5 (FIG. 3), after the formation of the silicon oxide film 48, the silicon oxide film 48 and the silicon oxide film 47 are etched by anisotropic etching to form the upper surface of the gate electrode 7, the upper surface of the SOI layer 4, and the electrode hole 28. The bottom surface, that is, the top surface of the N well layer 21 and the top surface of the P-type silicon substrate 2 are exposed.

As a result, the gate insulating film 6 is formed between the gate electrode 7 and the SOI layer 4, the sidewalls 8 are formed on both sides of the gate electrode 7, and the inner peripheral surface of the electrode hole 28 is lined with the electrode insulating film 27. The
Next, a resist mask 46 covering one of the electrode holes 28 on the N well layer 21 in the SCR formation region 41 and one of the electrode holes 28 on the P-type silicon substrate 2 is formed by photolithography, and this is used as a mask. High-concentration N-type impurities are ionized on the upper surface of the exposed SOI layer 4 and the N-well layer 21 and the P-type silicon substrate 2 exposed at the bottom of the electrode hole 28 not covered by the resist mask 46. The source layer 9 and the drain layer 10 of the nMOS element 5 are formed in the SOI layer 4 on both sides of the gate electrode 7, and the first N type diffusion layer 23 is formed on the surface layer of the N well layer 21. A second N-type diffusion layer 25 is formed on the surface layer of the substrate 2.

At this time, a high-concentration N-type impurity is simultaneously ion-implanted into the SOI layer 4 located above the interface between the N-well layer 21 and the P-type silicon substrate 2 to form a conductive diffusion layer 37.
P6 (FIG. 3), the resist mask 46 formed in step P5 is removed, and the electrode hole 28 that has been blocked in step P5 on the N well layer 21 in the SCR formation region 41 and on the P-type silicon substrate 2 by photolithography. A resist mask 46 having an opening is formed on the N well layer 21 and the P-type silicon substrate 2 exposed at the bottom of the electrode hole 28 in which the resist mask 46 is opened. A type impurity is ion-implanted to form a first P-type diffusion layer 22 in the surface layer of the N well layer 21 and a second P-type diffusion layer 24 in the surface layer of the P-type silicon substrate 2.

This step is preferably performed simultaneously with the formation of a source layer and a drain layer of a pMOS element (not shown) formed in another part of the semiconductor wafer 40.
After the formation of P7 (FIG. 3), the first and second P-type diffusion layers 24 and 26, the first and second N-type diffusion layers 23 and 25, and the conductive diffusion layer 37, the resist mask 46 is removed, and sputtering is performed. A conductive layer made of a conductive material is formed on the SOI layer 4 and inside the electrode insulating film 27 in the electrode hole 28 by a method or the like.

  Then, the source electrode 11 and drain electrode 12 in the internal circuit formation region 42 and the anode electrode 32 and N well electrode 33 in the SCR formation region 41, the substrate electrode 34, the cathode electrode 35, and the control electrode 38 are covered by photolithography. A resist mask 46 (not shown) is formed, and using this as a mask, the conductive layer is etched to form the source electrode 11 on the source layer 9 and the drain electrode 12 on the drain layer 10, and the SOI layer 4 and the buried insulating layer. 3, an anode electrode 32 reaching the first P-type diffusion layer 22, an N-well electrode 33 reaching the first N-type diffusion layer 23, a substrate electrode 34 reaching the second P-type diffusion layer 24, a second Of the cathode electrode 35 reaching the N-type diffusion layer 25 and the conductive diffusion layer 37 between the anode electrode 32 and the cathode electrode 35, To form a very 38.

Next, the resist mask 46 formed in the process P7 is removed, and the SCR element 20 of this embodiment shown in FIG. 1 is formed.
Thereafter, an interlayer insulating film that covers the SOI layer 4, contact plugs that electrically connect each electrode to the interlayer insulating film, a wiring pattern that is electrically connected to the contact plugs, signal terminals 15 and the like are formed, and this embodiment is performed. A semiconductor device having an ESD protection circuit having the example SCR element 20 is manufactured.

In this case, the ESD protection circuit using the SCR element 20 of this embodiment is connected as shown in FIG.
That is, between the power supply voltage (VDD) and the ground (VSS), the SCR element 20 of this embodiment is an ESD protection element that is non-conductive when the voltage is in a normal operation and is conductive only when it is protected from a surge voltage. As shown in FIG. 5, the anode electrode 32, the N well electrode 33, and the control electrode 38 on the conductive diffusion layer 37 are connected to the power supply voltage (VDD), and the cathode electrode 35 and the substrate electrode 34 are Connected to ground (VSS).

As shown in FIG. 4, between the signal terminal 15 and the power supply voltage (VDD), a first diode 61 is arranged with its anode side connected to the signal terminal 15, and the signal terminal 15 and the ground ( (VSS), a second diode 62 is arranged with its cathode side connected to the signal terminal 15.
The ESD protection circuit configured as described above operates as follows.

When a surge voltage, for example, a positive surge voltage is applied to the signal terminal 15, the first diode 61 is forward biased and the second diode 62 is reverse biased. The current flows from the diode 61 side to the ground (VSS) side through a path indicated by a thick solid line in FIG.
That is, the surge current that has passed through the first diode 61 is guided to the SCR element 20 by the power supply voltage line, and the first P-type diffusion layer 22 and the via the anode electrode 32, the N well electrode 33, and the control electrode 38. When a positive surge voltage is applied to the first N type diffusion layer 23 and the conductive diffusion layer 37, the first N type diffusion layer 23 and the first P type diffusion layer 22 formed in the N well layer 21 Are at the same positive potential, and the first N-type diffusion layer 23 and the N-well layer 21 and the first P-type diffusion layer 22 are reversely biased. Hole outflow is suppressed at the PN junction with the mold diffusion layer 22.

  At this time, the surge voltage guided to the control electrode 38 increases the potential of the conductive diffusion layer 37 between the anode electrode 32 and the cathode electrode 35, and the N well layer 21 below the buried insulating layer 3 and the second N Charge is injected into a depletion layer formed in the P-type silicon substrate 2 between the P-type diffusion layer 25 and the depletion layer under the buried insulating layer 3 is easily inverted, so that the N well layer 21 and the second well layer 21 can be reversed with a low breakdown voltage. The balance of inhibition of PN junction with the first P-type diffusion layer 22 is lost, and the first P-type diffusion layer 22, the N-well layer 21, the P-type silicon substrate 2, and the second N-type diffusion layer 25 are passed through. A breakdown occurs in which an abrupt current flows between the anode electrode 32 and the cathode electrode 35, resulting in a small on-resistance and a large current flowing through the SCR element 20 with a small holding voltage. VSS) That.

When a negative surge voltage is applied to the signal terminal 15, the second diode 62 is forward-biased and the first diode 61 is reverse-biased, so that the surge current is from the second diode 62 side. The current flows along the path indicated by the thick broken line in FIG. 4 to the power supply voltage (VDD) side.
That is, the surge current that has passed through the second diode 62 is guided to the SCR element 20 by the ground wire, and the second P-type diffusion layer 24 and the second N-type diffusion layer through the cathode electrode 35 and the substrate electrode 34. When a negative surge voltage is applied to 25, the first P-type diffusion layer 22, the first N-type diffusion layer 23 and the conductive diffusion layer 37 connected to the power supply voltage (VDD) are relatively positive. When the positive surge voltage is applied, the state becomes relatively equivalent to the case where the positive surge voltage is applied, and a breakdown occurs in the SCR element 20 by the same operation as described above, and the current is transmitted through the power supply voltage line. To the power supply voltage (VDD) side.

This protects the internal circuit from positive and negative surge voltages.
FIG. 6 shows the result of the simulation calculation of the breakdown voltage of the SCR element 20 of this example that performs such an operation.
The simulation calculation is performed in the connection state shown in FIG. 1, and the horizontal axis shown in FIG. 6 indicates the positive voltage applied to the anode electrode 32, the N-well electrode 33, and the control electrode 38 on the conductive diffusion layer 37. The vertical axis indicates the current flowing between the anode electrode 32 and the cathode electrode 35.

6 indicates the voltage-current characteristics when the conductive diffusion layer 37 of this embodiment is not formed, and the ◯ mark indicates the voltage in the case of the SCR element 20 of the present embodiment where the conductive diffusion layer 37 is formed. Current characteristics are shown.
As shown in FIG. 6, the breakdown voltage in the case of the SCR element 20 of this embodiment (circles shown in FIG. 6) is about 20V, and the breakdown voltage in the case where the conductive diffusion layer 37 is not formed is about 460V. It is greatly reduced compared to.

  In this case, in order to prevent a leakage current during normal operation, it is necessary to make the breakdown voltage higher than the rated voltage of the internal element. Therefore, if the breakdown voltage is too high, N of the conductive diffusion layer 37 The breakdown voltage is lowered by increasing the type impurity concentration. If the breakdown voltage is too low, the N type impurity concentration of the conductive diffusion layer 37 is decreased, or a P type impurity is implanted into the conductive diffusion layer 37 to cause a break. The breakdown voltage is increased, and the breakdown voltage is set to a voltage higher than the rated voltage of the internal circuit and lower than the breakdown voltage (usually about twice the rated voltage).

FIG. 7 shows a case where a high concentration P-type impurity is implanted into the conductive diffusion layer 37 of the SCR element 20 of this embodiment and the pMOS element 50.
In FIG. 7, a pMOS element 50 as an internal element includes an SOI layer 4 in which low-concentration N-type impurities are diffused, a gate insulating film 6, a gate electrode 7, sidewalls 8, gates similar to the nMOS element 5 described above. Source layer 51 and drain layer 52 formed by diffusing relatively high-concentration P-type impurities on both sides of electrode 7, and source electrode 11 and drain electrode 12 formed on source layer 51 and drain layer 52 in the same manner as described above. The SOI layer 4 in which a low-concentration N-type impurity is diffused under the gate electrode 7 sandwiched between the source layer 51 and the drain layer 52 functions as the channel region 53 of the pMOS element 50, and the gate electrode 7, the current flowing between the source layer 51 and the drain layer 52 is controlled by the channel formed in the channel region 53 when a rated voltage is applied. It has a function of.

The conductive diffusion layer 37 of the SCR element 20 shown in FIG. 7 is formed by diffusing high-concentration P-type impurities, and a control electrode 38 is formed immediately above.
In this case, as shown by a broken line in FIG. 7, the signal terminal 15 is connected to the drain electrode 12 and the gate electrode 7 of the pMOS element 50 as the internal element, and in the same manner as described above, the first terminal of the SCR element 20 is connected. The second P-type diffusion layer 24 and the second N-type diffusion layer 25 are connected directly to the P-type diffusion layer 22, the first N-type diffusion layer 23, and the conductive diffusion layer 37. VDD).

The source electrode 11 of the pMOS element 50 is electrically connected to a predetermined part of the internal circuit.
In this case, the implantation of P-type impurities into the conductive diffusion layer 37 forms the source layer 51 and the drain layer 52 of the pMOS element 50 and the first and second P-type diffusion layers 22 and 24 of the SCR element 20. Sometimes (a step corresponding to the step P5) is performed, and in the step corresponding to the step P6, N-type impurities are ion-implanted to form the first and second N-type diffusion layers 23 and 25 of the SCR element 20. It is formed.

Note that the order of the steps P5 and P6 may be changed. The same applies to the process corresponding to the process P5 and the process corresponding to the process P6.
In addition, the breakdown voltage is adjusted by changing the P-type impurity concentration of the conductive diffusion layer 37 or changing the type of impurities to N-type impurities as described above.
In this case, the connection with the signal terminal 15 is directly connected to the anode electrode 32, the N-well electrode 33, and the control electrode 38 of the SCR element 20 in the case shown in FIG. When the first stage of the input circuit or the final stage of the output circuit is the nMOS element 5, as shown in FIG. 1, it is connected to the drain electrode 12 of the nMOS element 5, and the first stage of the input circuit or the final stage of the output circuit is In the case of the pMOS element 50, it is connected to the drain electrode 12 and the gate electrode 7 of the pMOS element 50 as shown in FIG.

That is, even when the breakdown voltage is adjusted by changing the impurity concentration or the kind of the impurity in the conductive diffusion layer 37, it is not necessary to change the connection state in the SCR element 20.
As described above, the SCR element 20 of the present embodiment includes the N-type well layer 21 and the first and second P-type diffusion layers 22 and 24, the first and second P-type silicon substrates 2 under the buried insulating layer 3. 2 N-type diffusion layers 23 and 25 are formed, and an anode electrode 32, an N-well electrode 33, a cathode electrode 35, and a substrate electrode 34 that penetrate through the SOI layer 4 and the buried insulating layer 3 and reach these diffusion layers are formed. Since the surge voltage is guided to the conductive diffusion layer 37 formed in the SOI layer 4 between the anode electrode 32 and the cathode electrode 35, the surge voltage is applied to the P-type silicon substrate 2 below the buried insulating layer 3. Charges can be injected into the depletion layer to be formed, the depletion layer under the buried insulating layer 3 is easily inverted, and the SCR element 20 is made to have a low breakdown voltage triggered by application of a surge voltage to the signal terminal 15. It is possible to cause breakdown by bypassing the internal circuit and allowing a large current due to the surge voltage to flow through the P-type silicon substrate 2, reducing the thermal effect on the SOI layer 4 and making the internal circuit surge voltage. In addition, the thin SOI layer 4 can increase the density of the internal circuit.

Further, since the control electrode 38 is directly connected to the signal terminal 15, it is not necessary to secure a space for providing the control circuit, and the semiconductor device including the ESD protection circuit having the SCR element 20 can be downsized.
Furthermore, since the P-type silicon substrate 2 and the conductive diffusion layer 37 are opposed to each other through the relatively thick buried insulating layer 3, even if a high voltage due to a surge is applied to the control electrode 38, the buried insulating layer 3 does not break down. Never happen.

  Further, an electrode insulating film 27 of the electrode hole 28 is formed by using a process of forming the nMOS element 5 as an internal element and the third wall 8 of the pMOS element 50, and the source layer 9, the drain layer 10, and the source layer are formed. 51. Since the first and second N-type diffusion layers 23 and 25 and the first and second P-type diffusion layers 22 and 24 are formed using an ion implantation process for forming the drain layer 52, the SCR element Thus, the number and the number of resist masks 46 in the manufacturing process of the semiconductor device having the ESD protection circuit having 20 can be reduced, and the manufacturing efficiency of the semiconductor device can be improved.

In this case, the impurity concentration implanted into the conductive diffusion layer 37 is the same as the concentration of the first and second N-type diffusion layers 23 and 25 or the concentration of the first and second P-type diffusion layers 22 and 24. If so, they can be formed simultaneously in the ion implantation step, and the manufacturing efficiency of the semiconductor device can be further improved.
Furthermore, although the number of resist masks 46 in the ion implantation process of the above processes P5 and P6 is increased by one, the impurity concentration implanted into the conductive diffusion layer 27 is changed to the first and second N-type diffusion layers 23, If the concentration is other than the impurity concentration of 25, or the concentration other than the impurity concentration of the first and second P-type diffusion layers 22 and 24, the breakdown voltage can be easily adjusted by changing the impurity concentration or the type of impurity. The breakdown voltage of the SCR element 20 can be optimized by setting the breakdown voltage higher than the rated voltage of the internal circuit and lower than the breakdown voltage.

  As described above, in this embodiment, the N-well layer of the SCR element, the first and second P-type diffusion layers, the first and second N-type diffusion layers are formed on the P-type silicon substrate below the buried insulating layer. An anode electrode, an N-well electrode, a cathode electrode, and a substrate electrode that penetrate through the SOI layer and the buried insulating layer and reach each diffusion layer are formed, and a conductive diffusion layer is formed on the SOI layer between the anode electrode and the cathode electrode. Thus, a surge voltage can be guided to the conductive diffusion layer to inject charges into the depletion layer formed in the P-type silicon substrate under the buried insulating layer, and the depletion layer under the buried insulating layer can be injected. The SCR element can be operated with a low breakdown voltage triggered by the application of a surge voltage, and a large current caused by the surge voltage is bypassed by bypassing the internal circuit. It is possible to reduce the thermal influence on the SOI layer by flowing, thereby protecting the internal circuit from a surge voltage.

In addition, since the surge voltage applied to the signal terminal is applied to the conductive diffusion layer, there is no need to provide an auxiliary circuit such as a control circuit, and the semiconductor device having the ESD protection circuit having the SCR element can be downsized. Can be achieved.
Further, by changing the impurity concentration implanted into the conductive diffusion layer to a concentration other than the impurity concentrations of the first and second N-type diffusion layers and the first and second P-type diffusion layers, The breakdown voltage can be easily adjusted by changing the type of impurities, and the breakdown voltage of the SCR element can be optimized.

  1 and 2, the first P type diffusion layer and the first N type diffusion layer of the N well layer, and the second P type of the P type silicon substrate in the vicinity spaced apart from the N well layer are used. The arrangement of the diffusion layer and the second N-type diffusion layer is illustrated in order N-P-N-P. However, the arrangement is not limited to the above, and the P-type in the vicinity separated from the N-well layers on both sides of the N-well layer. Any arrangement may be employed, such as arranging the second P-type diffusion layer and the second N-type diffusion layer on the silicon substrate. In short, a conductive diffusion layer is formed in the SOI layer between the anode electrode formed on the first P-type diffusion layer of the N-well layer and the cathode electrode formed on the second N-type diffusion layer of the P-type silicon substrate. All you need is enough.

Explanatory drawing which shows the cross section of the semiconductor device of an Example Explanatory drawing which shows the manufacturing method of the semiconductor device of an Example Explanatory drawing which shows the manufacturing method of the semiconductor device of an Example Explanatory drawing which shows the structural example of the ESD protection circuit of an Example. Explanatory drawing which shows the connection state of the SCR protection element of the ESD protection circuit of an Example The graph which shows the simulation result of the voltage-current characteristic of the SCR element of an Example Explanatory drawing which shows the cross section of the semiconductor device of an Example

Explanation of symbols

DESCRIPTION OF SYMBOLS 1 Semiconductor substrate 2 P-type silicon substrate 3 Embedded insulating layer 4 SOI layer 5 nMOS element 6 Gate insulating film 7 Gate electrode 8 Side wall 9, 51 Source layer 10, 52 Drain layer 11 Source electrode 12 Drain electrode 13, 53 Channel region 15 Signal terminal 20 SCR element 21 N well layer 22 First P type diffusion layer 23 First N type diffusion layer 24 Second P type diffusion layer 25 Second N type diffusion layer 27 Electrode insulating film 28 Electrode hole 32 Anode Electrode 33 N well electrode 34 Substrate electrode 35 Cathode electrode 37 Conductive diffusion layer 38 Control electrode 40 Semiconductor wafer 41 SCR formation region 42 Internal circuit formation region 43 N well formation region 44 Protective oxide film 46 Resist mask 47, 48 Silicon oxide film 50 pMOS Element 61 First diode 62 Second diode

Claims (6)

A P-type silicon substrate;
A buried insulating layer formed on the P-type silicon substrate;
An SOI layer formed on the buried insulating layer;
An N well layer formed by diffusing N type impurities in the P type silicon substrate;
A first P-type diffusion layer and a first N-type diffusion layer formed in the N well layer;
A second P-type diffusion layer and a second N-type diffusion layer formed on the P-type silicon substrate and spaced apart from the N-well layer;
An anode electrode that penetrates the SOI layer and the buried insulating layer and reaches the first P-type diffusion layer, an N-well electrode that reaches the first N-type diffusion layer, and a second N-type diffusion layer In a semiconductor device comprising a cathode electrode reaching and a substrate electrode reaching the second P-type diffusion layer,
A semiconductor device comprising a conductive diffusion layer formed by diffusing a conductive impurity in an SOI layer between the anode electrode and the cathode electrode. In claim 1,
The conductive impurity diffused in the conductive diffusion layer is an N-type impurity,
A semiconductor device characterized in that the concentration of the N-type impurity diffused in the conductive diffusion layer is the same as the impurity concentration of the first and second N-type diffusion layers. In claim 1,
The conductive impurity diffused in the conductive diffusion layer is an N-type impurity,
A semiconductor device characterized in that the concentration of the N-type impurity diffused in the conductive diffusion layer is a concentration other than the impurity concentration of the first and second N-type diffusion layers. In claim 1,
The conductive impurity injected into the conductive diffusion layer is a P-type impurity,
A semiconductor device characterized in that the concentration of the P-type impurity diffused in the conductive diffusion layer is the same as the impurity concentration of the first and second P-type diffusion layers. In claim 1,
The conductive impurity injected into the conductive diffusion layer is a P-type impurity,
A semiconductor device characterized in that the concentration of the P-type impurity diffused in the conductive diffusion layer is a concentration other than the impurity concentration of the first and second P-type diffusion layers. In any one of Claims 1 thru | or 5,
Providing a signal terminal electrically connected to an internal circuit formed in the SOI layer;
A semiconductor device, wherein a surge voltage applied to the signal terminal is applied to the conductive diffusion layer.