JPH05235266A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPH05235266A JPH05235266A JP3653892A JP3653892A JPH05235266A JP H05235266 A JPH05235266 A JP H05235266A JP 3653892 A JP3653892 A JP 3653892A JP 3653892 A JP3653892 A JP 3653892A JP H05235266 A JPH05235266 A JP H05235266A
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- Prior art keywords
- integrated circuit
- circuit device
- semiconductor integrated
- lower electrode
- capacitance element
- Prior art date
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Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は半導体集積回路装置に係
わり、特にスイッチドキャパシタフィルタ（以後、ＳＣ
Ｆ、という）、Ｃ−Ｒ型のＡ／Ｄ変換器、Ｃ−Ｒ型のＤ
／Ａ変換器、などの容量素子を含む半導体集積回路装置
に関する。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a switched capacitor filter (hereinafter referred to as SC
F), C-R type A / D converter, C-R type D
The present invention relates to a semiconductor integrated circuit device including a capacitive element such as an A / A converter.
【０００２】[0002]
【従来の技術】半導体集積回路装置はトランジスタ素子
や容量素子の集合体である。又、それらを含む機能ブロ
ックの集合体でもある。ここで、半導体集積回路装置の
一例としてのＳＣＦを説明する。2. Description of the Related Art A semiconductor integrated circuit device is an assembly of transistor elements and capacitive elements. It is also an aggregate of functional blocks including them. Here, the SCF as an example of the semiconductor integrated circuit device will be described.
【０００３】図４の回路図に示されたＳＣＦで使用され
る帰還容量素子Ｃ２と入力容量素子Ｃ１とが構成されて
いる、従来の半導体集積回路装置の平面図と断面図を図
３の（Ａ）と（Ｂ）に示す。FIG. 3 shows a plan view and a sectional view of a conventional semiconductor integrated circuit device in which a feedback capacitance element C2 and an input capacitance element C1 used in the SCF shown in the circuit diagram of FIG. 4 are configured. Shown in A) and (B).
【０００４】Ｐ型半導体基板９にＮ型ウエル領域８が形
成され、このＮ型ウエル領域８の上面にシリコン酸化膜
から成る絶縁膜１７を介してＰ型のポリシリコン層２，
１２が容量素子の下部電極として形成され、その上にそ
れぞれ誘電体としての絶縁膜７を介して複数の単位上部
電極１が形成されている。入力容量素子Ｃ１は取り出し
部６で上部電極配線３によって接続された４個の単位上
部電極１と下部電極２との重なり部分が容量となる。す
なわち、単位上部電極１と下部電極２との重なり部分で
構成される単位容量素子Ｃ0 が４個並列に接続された容
量素子である。同様に、帰還容量素子Ｃ２は、２個の単
位上部電極１が上部電極配線１３によって接続されてい
るから、下部電極１２との重なり部分で構成される単位
容量素子Ｃ0 が２個並列に接続された容量素子である。An N type well region 8 is formed on a P type semiconductor substrate 9, and a P type polysilicon layer 2 is formed on the upper surface of the N type well region 8 with an insulating film 17 made of a silicon oxide film interposed therebetween.
12 is formed as a lower electrode of the capacitive element, and a plurality of unit upper electrodes 1 are formed thereon with an insulating film 7 serving as a dielectric interposed therebetween. In the input capacitance element C1, the overlapping portion of the four unit upper electrodes 1 and the lower electrode 2 connected by the upper electrode wiring 3 in the extraction portion 6 becomes the capacitance. That is, it is a capacitive element in which four unit capacitive elements C 0 configured by the overlapping portion of the unit upper electrode 1 and the lower electrode 2 are connected in parallel. Similarly, in the feedback capacitance element C2, since the two unit upper electrodes 1 are connected by the upper electrode wiring 13, two unit capacitance elements C 0 formed in the overlapping portion with the lower electrode 12 are connected in parallel. Is a capacitive element.
【０００５】Ｎ型ウエル領域８は取り出し部１０で接続
されたウエル電極配線１１により接地電位（０Ｖ）とな
っている。一方、入力容量素子Ｃ１の下部電極としての
ポリシリコン層２は取り出し部５で接続された下部電極
配線４によって入力信号端子に接続され（図４）、帰還
容量素子Ｃ２の下部電極としてのポリシリコン層１２は
取り出し部５で接続された下部電極配線１４によって出
力信号端子に接続されている（図４）。 又、図４に示
す様に、入力容量素子Ｃ１および帰還容量素子Ｃ２の上
部電極はその配線３，１３によってそれぞれスイッチ、
すなわち半導体集積回路装置内に形成されたトランジス
タによる半導体スイッチを通してＡＭＰの一方の入力端
子に接続されている。尚、図４において、白三角印
（▽）は基準電圧端子を示している。The N-type well region 8 has a ground potential (0 V) due to the well electrode wiring 11 connected at the take-out portion 10. On the other hand, the polysilicon layer 2 as the lower electrode of the input capacitance element C1 is connected to the input signal terminal by the lower electrode wiring 4 connected at the extraction portion 5 (FIG. 4), and the polysilicon layer 2 as the lower electrode of the feedback capacitance element C2 is connected. The layer 12 is connected to the output signal terminal by the lower electrode wiring 14 connected at the extraction portion 5 (FIG. 4). Further, as shown in FIG. 4, the upper electrodes of the input capacitance element C1 and the feedback capacitance element C2 are switched by the wirings 3 and 13, respectively.
That is, it is connected to one input terminal of the AMP through a semiconductor switch formed by a transistor formed in the semiconductor integrated circuit device. In addition, in FIG. 4, a white triangle mark (∇) indicates a reference voltage terminal.
【０００６】[0006]
【発明が解決しようとする課題】上述した従来の半導体
集積回路装置は図３（Ｂ）に示す様に、下部電極２およ
び１２とＮ型ウエル領域８との間の絶縁膜１７を誘電体
膜としたＭＯＳ容量Ｃ５およびＣ６が寄生容量としてそ
れぞれ形成される。したがって従来はこの寄生容量によ
るＮ型ウエル領域８からのノイズのまわり込みを防ぐた
めに、Ｎ型ウエル領域８を低電圧電源（例えば、接地電
位）に接続していた。しかしながら、寄生容量Ｃ５と寄
生容量Ｃ６（例えば、下部電極の面積が５００μｍ2 の
場合、約０．０２ｐＦ）とが同一のＮウエル領域上に形
成され、ウエル領域には抵抗Ｒ１が存在し、この抵抗Ｒ
１（例えば、下部電極間の距離が１０μｍの場合、５ｋ
Ω）を通る系により、出力側からのノイズが入力側にま
わり込んでしまい、ノイズ特性が悪くなるという欠点が
あった。In the conventional semiconductor integrated circuit device described above, as shown in FIG. 3B, the insulating film 17 between the lower electrodes 2 and 12 and the N-type well region 8 is formed into a dielectric film. The MOS capacitors C5 and C6 are formed as parasitic capacitors. Therefore, conventionally, the N-type well region 8 is connected to a low-voltage power supply (for example, ground potential) in order to prevent the noise from flowing from the N-type well region 8 due to the parasitic capacitance. However, the parasitic capacitance C5 and the parasitic capacitance C6 (for example, about 0.02 pF when the area of the lower electrode is 500 μm 2 ) are formed on the same N well region, and the resistor R1 exists in the well region. Resistance R
1 (for example, if the distance between the lower electrodes is 10 μm, 5 k
Due to the system passing through (Ω), noise from the output side sneak into the input side, and the noise characteristics deteriorate.
【０００７】[0007]
【課題を解決するための手段】本発明の特徴は、複数の
容量素子を含む機能ブロックを有する半導体集積回路装
置において、前記機能ブロック内に共通の接続点をもつ
第１および第２の容量素子が一導電型の半導体基板にた
がいに分離された逆導電型の第１および第２のウエル領
域上にそれぞれ形成されている半導体集積回路装置にあ
る。この第１および第２の容量素子はそれぞれ単位容量
素子を並列接続して構成することができる。A feature of the present invention is that in a semiconductor integrated circuit device having a functional block including a plurality of capacitive elements, first and second capacitive elements having a common connection point in the functional block. In a semiconductor integrated circuit device formed on a first conductivity type semiconductor substrate and on opposite first conductivity type well regions separated from each other on a first conductivity type semiconductor substrate. Each of the first and second capacitance elements can be configured by connecting unit capacitance elements in parallel.
【０００８】[0008]
【実施例】次に本発明について図面を参照して説明す
る。半導体集積回路装置の一例である図４の回路図に関
する本発明の一実施例としての図１（Ａ），（Ｂ）は、
ＳＣＦの入力容量素子Ｃ１と帰還容量素子Ｃ２とが構成
されている半導体集積回路装置の平面図と断面図であ
る。尚、図１（Ａ），（Ｂ）において図３（Ａ），
（Ｂ）と同一もしくは類似の箇所は同じ符号で示してい
る。The present invention will be described below with reference to the drawings. 1A and 1B as one embodiment of the present invention relating to the circuit diagram of FIG. 4 which is an example of a semiconductor integrated circuit device,
FIG. 3 is a plan view and a sectional view of a semiconductor integrated circuit device in which an input capacitance element C1 and a feedback capacitance element C2 of an SCF are configured. In addition, in FIG. 1 (A), (B), FIG.
Portions that are the same as or similar to those in (B) are denoted by the same reference numerals.
【０００９】Ｐ型半導体基板９に第１および第２のＮウ
エル領域１８，２８がそれぞれ形成され、これらのＮ型
ウエル領域１８，２８の上面にシリコン酸化膜から成る
絶縁膜１７を介してＰ型のポリシリコン層２，１２が容
量素子の下部電極として形成され、その上にそれぞれ誘
電体としての絶縁膜７を介してポリシリコンからなる複
数の単位上部電極１が形成されている。入力容量素子Ｃ
１は取り出し部６で上部電極配線３によって接続された
４個の単位上部電極１と下部電極２との重なり部分が容
量となる。すなわち、単位上部電極１と下部電極２との
重なり部分で構成される単位容量素子Ｃ0 が４個並列に
接続された容量素子である。同様に、帰還容量素子Ｃ２
は、２個の単位上部電極１が上部電極配線１３によって
接続されているから、下部電極１２との重なり部分で構
成される単位容量素子Ｃ0 が２個並列に接続された容量
素子である。First and second N well regions 18 and 28 are formed on the P type semiconductor substrate 9, and P is formed on the upper surfaces of these N well regions 18 and 28 with an insulating film 17 made of a silicon oxide film interposed therebetween. Type polysilicon layers 2 and 12 are formed as lower electrodes of the capacitive element, and a plurality of unit upper electrodes 1 made of polysilicon are formed on the lower polysilicon electrodes 2 and 12 with an insulating film 7 serving as a dielectric interposed therebetween. Input capacitance element C
Reference numeral 1 denotes a take-out portion 6, and the overlapping portion of the four unit upper electrodes 1 and the lower electrode 2 connected by the upper electrode wiring 3 serves as a capacitance. That is, it is a capacitive element in which four unit capacitive elements C 0 configured by the overlapping portion of the unit upper electrode 1 and the lower electrode 2 are connected in parallel. Similarly, the feedback capacitance element C2
Is a capacitor element in which two unit upper electrodes 1 are connected by the upper electrode wiring 13 and thus two unit capacitor elements C 0 formed in an overlapping portion with the lower electrode 12 are connected in parallel.
【００１０】それぞれのＮ型ウエル領域１８，２８は、
取り出し部１０で接続されたウエル電極配線１１により
接地電位（０Ｖ）となっている。一方、入力容量素子Ｃ
１の下部電極としてのポリシリコン層２は取り出し部５
で接続された下部電極配線４によって入力信号端子に接
続され（図４）、帰還容量素子Ｃ２の下部電極としての
ポリシリコン層１２は取り出し部５で接続された下部電
極配線１４によって出力信号端子に接続されている（図
４）。 又、図４に示す様に、入力容量素子Ｃ１および
帰還容量素子Ｃ２の上部電極はその配線３，１３によっ
てそれぞれスイッチ、すなわち半導体集積回路装置内に
形成されたトランジスタによる半導体スイッチを通して
ＡＭＰの一方の入力端子に接続されている。図３と同様
に、入力容量素子Ｃ１の下部電極２とＮ型ウエル領域１
８との間には寄生容量Ｃ５（例えば、下部電極の面積が
５００μｍ2 の場合、約０．０２ｐＦ）が形成され、帰
還容量素子Ｃ２の下部電極１２とＮ型ウエル領域２８と
の間には寄生容量Ｃ６（例えば、下部電極の面積が５０
０μｍ2 の場合、約０．０２ｐＦ）が形成される。The respective N-type well regions 18 and 28 are
The well electrode wiring 11 connected at the extraction portion 10 provides the ground potential (0 V). On the other hand, the input capacitance element C
The polysilicon layer 2 serving as the lower electrode of
Is connected to the input signal terminal by the lower electrode wiring 4 connected by (FIG. 4), and the polysilicon layer 12 as the lower electrode of the feedback capacitance element C2 is connected to the output signal terminal by the lower electrode wiring 14 connected at the extraction portion 5. Connected (Fig. 4). Also, as shown in FIG. 4, the upper electrodes of the input capacitance element C1 and the feedback capacitance element C2 are switched by wirings 3 and 13, respectively, that is, one of the AMPs through a semiconductor switch made of a transistor formed in the semiconductor integrated circuit device. It is connected to the input terminal. Similar to FIG. 3, the lower electrode 2 and the N-type well region 1 of the input capacitor C1 are
8, a parasitic capacitance C5 (for example, about 0.02 pF when the area of the lower electrode is 500 μm 2 ) is formed, and between the lower electrode 12 of the feedback capacitance element C2 and the N-type well region 28. The parasitic capacitance C6 (for example, the area of the lower electrode is 50
At 0 μm 2 , about 0.02 pF) is formed.
【００１１】しかしながら本発明では、入力容量素子Ｃ
１の下部電極２をＰ型半導体基板（サブ基板）９からシ
ールドするためのＮ型ウエル領域１８と帰還容量素子Ｃ
２の下部電極１２をＰ型半導体基板（サブ基板）９から
シールドするためのＮ型ウエル領域２８とは分離されて
いる。このようにシールド用のＮ型ウエル領域をたがい
に分離すことにより、寄生容量Ｃ５と寄生容量Ｃ６は同
一のウエル領域上に存在しなくなり、これにより直接の
寄生抵抗で接続されることがなく、出力側のノイズが入
力側へまわり込まなくなり、ノイズ特性が良くなる。However, in the present invention, the input capacitance element C
N type well region 18 for shielding the lower electrode 2 of 1 from the P type semiconductor substrate (sub substrate) 9 and the feedback capacitance element C
The second lower electrode 12 is isolated from the N-type well region 28 for shielding the P-type semiconductor substrate (sub-substrate) 9 from the second lower electrode 12. By thus separating the N-type well region for shielding from each other, the parasitic capacitance C5 and the parasitic capacitance C6 do not exist on the same well region, so that they are not directly connected by the parasitic resistance. Noise on the output side will not sneak into the input side, improving the noise characteristics.
【００１２】以上は例としてＳＣＦについて説明した
が、これに限られることはなく、Ｃ−Ｒ型のＡ／Ｄ変換
器、Ｃ−Ｒ型のＤ／Ａ変換器などでも、同様の効果が得
られる。Although the SCF has been described above as an example, the present invention is not limited to this, and a similar effect can be obtained with a CR type A / D converter or a CR type D / A converter. Be done.
【００１３】図２（Ａ），（Ｂ）は、ＳＣＦの入力容量
素子Ｃ１と帰還容量素子Ｃ２とが構成されている半導体
集積回路装置の本発明の他の実施例を示す平面図と断面
図である。尚、図２（Ａ），（Ｂ）において図１
（Ａ），（Ｂ）と同一もしくは類似の箇所は同じ符号で
示している。入力容量素子Ｃ１下のＮウエル領域１８と
帰還容量素子Ｃ２下のＮウエル領域２８との間のＰ型半
導体基板（サブ基板）９の部分に基板（サブ基板）電極
取り出し部１５を設け、ここに接続する基板電極配線１
６を接地端子に接続する。この場合、図２（Ｂ）に示す
様に、寄生容量Ｃ７，Ｃ８が生じてもウエル領域間の基
板部分を電極取り出し部１５により低インピーダンスの
電源に接続しているため、寄生容量Ｃ７，Ｃ８を通じて
出力のノイズが入力へまわり込まなくなり、図１の実施
例よりさらにノイズ特性が改善できる。2A and 2B are a plan view and a sectional view showing another embodiment of the present invention of a semiconductor integrated circuit device in which an input capacitance element C1 of an SCF and a feedback capacitance element C2 are formed. Is. In addition, in FIG. 2 (A), (B)
Portions that are the same as or similar to those in (A) and (B) are denoted by the same reference numerals. A substrate (sub-substrate) electrode lead-out portion 15 is provided in a portion of the P-type semiconductor substrate (sub-substrate) 9 between the N-well region 18 under the input capacitance element C1 and the N-well region 28 under the feedback capacitance element C2. Substrate electrode wiring 1 to be connected to
Connect 6 to the ground terminal. In this case, as shown in FIG. 2B, even if parasitic capacitances C7 and C8 occur, the substrate portion between the well regions is connected to the low impedance power source by the electrode lead-out portion 15, so that the parasitic capacitances C7 and C8 are connected. Therefore, the noise of the output does not sneak into the input, and the noise characteristic can be further improved as compared with the embodiment of FIG.
【００１４】[0014]
【発明の効果】以上説明したように本発明は、入力容量
素子Ｃ１の下部電極２をＰ型半導体基板９からシールド
するためのＮ型ウエル領域１８と帰還容量素子Ｃ２の下
部電極１２をＰ型半導体基板９からシールドするための
Ｎ型ウエル領域２８とを分離することにより、図４の回
路図に示す寄生容量Ｃ５，Ｃ６および寄生抵抗Ｒ１を通
る系をなくすことが出来る。従って、出力ノイズが入力
にまわり込まなくなり、ノイズ特性が改善される。As described above, according to the present invention, the N-type well region 18 for shielding the lower electrode 2 of the input capacitance element C1 from the P-type semiconductor substrate 9 and the lower electrode 12 of the feedback capacitance element C2 are P-type. By separating the N-type well region 28 for shielding from the semiconductor substrate 9, the system passing through the parasitic capacitances C5 and C6 and the parasitic resistance R1 shown in the circuit diagram of FIG. 4 can be eliminated. Therefore, the output noise does not sneak into the input, and the noise characteristic is improved.
【図１】本発明の一実施例を示す図であり、（Ａ）は平
面図、（Ｂ）は（Ａ）のＡ−Ａ部の断面図である。1A and 1B are views showing an embodiment of the present invention, FIG. 1A is a plan view, and FIG. 1B is a sectional view taken along the line AA of FIG.
【図２】本発明の他の実施例を示す図であり、（Ａ）は
平面図、（Ｂ）は（Ａ）のＡ−Ａ部の断面図である。2A and 2B are views showing another embodiment of the present invention, in which FIG. 2A is a plan view and FIG. 2B is a sectional view taken along the line AA in FIG. 2A.
【図３】従来技術を示す図であり、（Ａ）は平面図、
（Ｂ）は（Ａ）のＡ−Ａ部の断面図である。FIG. 3 is a diagram showing a conventional technique, (A) is a plan view,
(B) is a cross-sectional view of an AA portion of (A).
【図４】ＳＣＦの回路図である。FIG. 4 is a circuit diagram of an SCF.
１ 上部電極 ２，１２ 下部電極 ３，１３ 上部電極の配線 ４，１４ 下部電極の配線 ５ 下部電極取り出し部 ６ 上部電極取り出し部 ７ 容量素子の誘電体膜としての絶縁膜 ８，１８，２８ Ｎ型ウエル領域 ９ Ｐ型半導体基板（サブ基板） １０ ウエル電極取り出し部 １１ ウエル電極配線 １５ 基板電極取り出し部 １６ 基板電極配線 １７ 絶縁膜 1 Upper Electrode 2,12 Lower Electrode 3,13 Upper Electrode Wiring 4,14 Lower Electrode Wiring 5 Lower Electrode Extraction Part 6 Upper Electrode Extraction Part 7 Insulating Film as Dielectric Film of Capacitor 8,18,28 N Type Well region 9 P-type semiconductor substrate (sub-substrate) 10 Well electrode lead-out portion 11 Well electrode wiring 15 Substrate electrode lead-out portion 16 Substrate electrode wiring 17 Insulating film
Claims (2)
する半導体集積回路装置において、前記機能ブロック内
に共通の接続点をもつ第１および第２の容量素子が一導
電型の半導体基板にたがいに分離された逆導電型の第１
および第２のウエル領域上にそれぞれ形成されているこ
とを特徴とする半導体集積回路装置。1. In a semiconductor integrated circuit device having a functional block including a plurality of capacitive elements, the first and second capacitive elements having a common connection point in the functional block are formed on a semiconductor substrate of one conductivity type. Separated reverse conductivity type first
And a semiconductor integrated circuit device formed on the second well region, respectively.
れ単位容量素子を並列接続して構成されていることを特
徴とする請求項１に記載の半導体集積回路装置。2. The semiconductor integrated circuit device according to claim 1, wherein the first and second capacitance elements are each configured by connecting unit capacitance elements in parallel.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3653892A JP2752832B2 (en) | 1992-02-24 | 1992-02-24 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP3653892A JP2752832B2 (en) | 1992-02-24 | 1992-02-24 | Semiconductor integrated circuit device |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH05235266A true JPH05235266A (en) | 1993-09-10 |
| JP2752832B2 JP2752832B2 (en) | 1998-05-18 |
Family
ID=12472564
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP3653892A Expired - Lifetime JP2752832B2 (en) | 1992-02-24 | 1992-02-24 | Semiconductor integrated circuit device |
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| Country | Link |
|---|---|
| JP (1) | JP2752832B2 (en) |
Cited By (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07106524A (en) * | 1993-10-07 | 1995-04-21 | Nec Corp | Semiconductor integrated circuit device |
| WO1996006460A1 (en) * | 1994-08-19 | 1996-02-29 | Hitachi, Ltd. | Semiconductor device |
| WO1998012750A1 (en) * | 1996-09-20 | 1998-03-26 | Hitachi, Ltd. | Semiconductor integrated circuit device |
| US5773872A (en) * | 1995-10-25 | 1998-06-30 | Nec Corporation | Semiconductor device having an integrated differential circuit with an improved common-mode rejection ratio (CMRR) |
| US5892266A (en) * | 1996-05-30 | 1999-04-06 | Sumitomo Metal Industries, Ltd. | Layout structure of capacitive element(s) and interconnections in a semiconductor |
| WO2004021439A1 (en) * | 2002-08-30 | 2004-03-11 | Matsushita Electric Industrial Co., Ltd. | Mim capacitor |
| US6777775B2 (en) | 2001-07-04 | 2004-08-17 | Matsushita Electric Industrial Co., Ltd. | Semiconductor integrated circuit, D-A converter device, and A-D converter device |
| WO2017159283A1 (en) * | 2016-03-18 | 2017-09-21 | 株式会社村田製作所 | Capacitive element |
-
1992
- 1992-02-24 JP JP3653892A patent/JP2752832B2/en not_active Expired - Lifetime
Cited By (12)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH07106524A (en) * | 1993-10-07 | 1995-04-21 | Nec Corp | Semiconductor integrated circuit device |
| WO1996006460A1 (en) * | 1994-08-19 | 1996-02-29 | Hitachi, Ltd. | Semiconductor device |
| US5773872A (en) * | 1995-10-25 | 1998-06-30 | Nec Corporation | Semiconductor device having an integrated differential circuit with an improved common-mode rejection ratio (CMRR) |
| US5892266A (en) * | 1996-05-30 | 1999-04-06 | Sumitomo Metal Industries, Ltd. | Layout structure of capacitive element(s) and interconnections in a semiconductor |
| WO1998012750A1 (en) * | 1996-09-20 | 1998-03-26 | Hitachi, Ltd. | Semiconductor integrated circuit device |
| US6777775B2 (en) | 2001-07-04 | 2004-08-17 | Matsushita Electric Industrial Co., Ltd. | Semiconductor integrated circuit, D-A converter device, and A-D converter device |
| US7777293B2 (en) | 2001-07-04 | 2010-08-17 | Panasonic Corporation | Semiconductor integrated circuit, D-A converter device, and A-D converter device |
| WO2004021439A1 (en) * | 2002-08-30 | 2004-03-11 | Matsushita Electric Industrial Co., Ltd. | Mim capacitor |
| US7030443B2 (en) | 2002-08-30 | 2006-04-18 | Matsushita Electric Industrial Co., Ltd. | MIM capacitor |
| WO2017159283A1 (en) * | 2016-03-18 | 2017-09-21 | 株式会社村田製作所 | Capacitive element |
| JPWO2017159283A1 (en) * | 2016-03-18 | 2018-10-11 | 株式会社村田製作所 | Capacitance element |
| US10916378B2 (en) | 2016-03-18 | 2021-02-09 | Murata Manufacturing Co., Ltd. | Capacitance element having capacitance forming units arranged and electrically connected in series |
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| Publication number | Publication date |
|---|---|
| JP2752832B2 (en) | 1998-05-18 |
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