JPS6348186B2 - - Google Patents
Info
- Publication number
- JPS6348186B2 JPS6348186B2 JP58169788A JP16978883A JPS6348186B2 JP S6348186 B2 JPS6348186 B2 JP S6348186B2 JP 58169788 A JP58169788 A JP 58169788A JP 16978883 A JP16978883 A JP 16978883A JP S6348186 B2 JPS6348186 B2 JP S6348186B2
- Authority
- JP
- Japan
- Prior art keywords
- upper electrode
- unit capacitance
- capacitance element
- semiconductor integrated
- group
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 claims description 8
- 239000000463 material Substances 0.000 claims description 3
- 238000005530 etching Methods 0.000 description 6
- 230000000694 effects Effects 0.000 description 4
- 238000010586 diagram Methods 0.000 description 3
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 2
- 229910052782 aluminium Inorganic materials 0.000 description 2
- 238000000034 method Methods 0.000 description 2
- 238000004965 Hartree-Fock calculation Methods 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000003990 capacitor Substances 0.000 description 1
- 239000004020 conductor Substances 0.000 description 1
- 230000003247 decreasing effect Effects 0.000 description 1
- 230000006698 induction Effects 0.000 description 1
- 230000003071 parasitic effect Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
- H01L27/10—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration
- H01L27/101—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including a plurality of individual components in a repetitive configuration including resistors or capacitors only
Description
【発明の詳細な説明】
本発明は半導体集積回路、特に比精度の良い容
量素子を有する半導体集積回路に関する。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor integrated circuit, and particularly to a semiconductor integrated circuit having a capacitive element with high relative accuracy.
アナログ集積回路に使用されるフイルター回路
には、第１図に示すようなS.C.F.（スイツチド
キヤパシタ フイルタ（Switched Capacitor
Filter））回路が多く使われており、この回路の
周波数特性は容量C1，C2の比精度によつて決定
される。 Filter circuits used in analog integrated circuits include SCFs (switched filter circuits) as shown in Figure 1.
Switched Capacitor Filter
Filter)) circuits are often used, and the frequency characteristics of these circuits are determined by the ratio accuracy of capacitances C 1 and C 2 .
従来の半導体集積回路においては、容量の精度
を高めるために、第２図ａ，ｂのような単位容量
素子を複数個設け、これを第３図に示すように一
定間隔をおいて配置し、必要とする容量に応じて
接続個数を調整することが行なわれていた。 In conventional semiconductor integrated circuits, in order to improve the precision of capacitance, a plurality of unit capacitance elements as shown in FIGS. 2a and 2b are provided, and these are arranged at regular intervals as shown in FIG. The number of connections was adjusted according to the required capacity.
第１図において、S1〜S2は電子スイツチで、Ａ
は増幅器である。 In Figure 1, S 1 to S 2 are electronic switches, and A
is an amplifier.
第２図ａ，ｂは従来から公知の単位容量素子の
一例の平面図と断面図で、それぞれ導電材料で形
成された上部電極１と下部電極２の間に絶縁層３
を挾んで容量を構成する。４は上部電極に接続す
るためのコンタクト部、５は接続用アルミ配線部
である。下部電極２は複数個の単位容量素子群に
対して共通であつても差支えなく、従つて下部電
極に対する外部への接続手段は省略してある。 FIGS. 2a and 2b are a plan view and a cross-sectional view of an example of a conventionally known unit capacitance element, in which an insulating layer 3 is interposed between an upper electrode 1 and a lower electrode 2 formed of a conductive material, respectively.
to configure the capacity. 4 is a contact portion for connecting to the upper electrode, and 5 is an aluminum wiring portion for connection. The lower electrode 2 may be common to a plurality of unit capacitance element groups, and therefore, means for connecting the lower electrode to the outside is omitted.
第３図は、従来から公知の単位容量素子群の一
例を示したもので、図では、６個をほぼ一定間隔
をおいて長方形に並べてある。 FIG. 3 shows an example of a conventionally known unit capacitance element group, and in the figure, six units are arranged in a rectangular shape at approximately constant intervals.
しかしながら、従来のこの配列には欠点があ
る。すなわち、各単位容量素子の上部電極１をエ
ツチングにて形成する場合、たとえその写真マス
クを各上部電極パターンごとに同一の寸法に設計
しておいても、エツチングプロセスによつて単位
容量素子群の外側が、より多くエツチングされる
傾向があり、第４図に示すように各上部電極の形
状が同一にならない欠点があつた。第４図におい
て６で示した部分はエツチングにより上部電極１
が挾められた部分で、説明のためにやや誇張して
書いてある。 However, this conventional arrangement has drawbacks. That is, when forming the upper electrode 1 of each unit capacitance element by etching, even if the photo mask is designed to have the same dimensions for each upper electrode pattern, the etching process will cause the formation of the unit capacitance element group. There was a tendency for the outer side to be etched more, and as shown in FIG. 4, there was a drawback that the shapes of the upper electrodes were not the same. The part indicated by 6 in Fig. 4 is etched into the upper electrode 1.
This is the part where the words are intertwined, and are slightly exaggerated for the sake of explanation.
従つて、接続する単位容量素子の数を増減して
も、それに比例して全静電容量を変化させること
ができなかつた。 Therefore, even if the number of connected unit capacitance elements is increased or decreased, the total capacitance cannot be changed in proportion.
本発明はこのような欠点を除去しエツチングに
よる差をなくしたものである。 The present invention eliminates these drawbacks and eliminates the difference caused by etching.
本発明によると一定間隔をおいて配置された複
数個の単位容量素子群を含む半導体集積回路にお
いて、前記単位容量素子群を形成する上部電極群
の周辺を前記上部電極と同一の材料、同一の加工
条件で形成され、かつ前記一定間隔と実質的に等
しい間隔を保つて設けられた枠状パターンで囲む
ことを特徴とする半導体集積回路が得られる。 According to the present invention, in a semiconductor integrated circuit including a plurality of unit capacitance element groups arranged at regular intervals, the periphery of the upper electrode group forming the unit capacitance element group is made of the same material as the upper electrode. A semiconductor integrated circuit is obtained, which is formed under processing conditions and is surrounded by a frame-like pattern provided at substantially equal intervals to the above-mentioned constant interval.
すなわち一定間隔を保つて配置された各単位容
量素子の集りの結果として成る上部電極群の周辺
に、それら電極群を構成するのと同じ材料と同じ
プロセスを用いて枠状パターンを設け、上部電極
群における外側効果（外側がエツチングされ易
い）をなくすものである。さらにこの枠状パター
ンをインピーダンスの低いラインに接続すること
により、他との寄生容量を低減させ、シールド効
果によつて雑音の誘導を減少させることができ
る。 In other words, a frame-like pattern is provided around the upper electrode group, which is the result of a collection of unit capacitance elements arranged at regular intervals, using the same material and the same process as those that constitute the electrode group, and the upper electrode This eliminates the outside effect (the outside is easily etched) in the group. Furthermore, by connecting this frame pattern to a line with low impedance, parasitic capacitance with others can be reduced, and noise induction can be reduced due to the shielding effect.
第５図は本発明の一実施例の上面図であり、７
は本発明において付加した枠状パターンで、上部
電極１の集まりである上部電極群の周囲に間隔ａ
で配置されている。間隔ａは、各単位容量素子の
上部電極１相互間の間隔ａと等しく選ばれてい
る。 FIG. 5 is a top view of one embodiment of the present invention, and 7
is a frame-like pattern added in the present invention, with an interval a around the upper electrode group, which is a collection of upper electrodes 1.
It is located in The distance a is selected to be equal to the distance a between the upper electrodes 1 of each unit capacitance element.
第５図に示した構成例によれば、上部電極群の
各電極パターンはエツチング効果に対して平等で
あり、従来にあつたようなエツチング差は除去で
きる。 According to the configuration example shown in FIG. 5, each electrode pattern of the upper electrode group has the same etching effect, and the etching difference that occurs in the prior art can be eliminated.
以上、本発明を一実施例である第５図によつて
説明したが、枠状パターンは完全に閉じている必
要はなく、途中で切れていたり、低インピーダン
スラインへの接続が複数個の位置で行なわれても
良いし、又枠状パターン内の上部電極群は単体で
あつても良いことは言うまでもない。 The present invention has been explained above with reference to FIG. 5, which is an embodiment, but the frame pattern does not need to be completely closed, and may be cut in the middle or connected to the low impedance line at multiple positions. It goes without saying that the upper electrode group within the frame pattern may be a single unit.
本発明によると、以上説明したように、上部電
極群における外側効果をなくした半導体集積回路
が得られる。 According to the present invention, as explained above, a semiconductor integrated circuit can be obtained in which the outer side effect in the upper electrode group is eliminated.
第１図は容量素子を有する半導体集積回路の一
例の回路図、第２図ａ，ｂは公知の単位容量素子
の例の平面図及び断面図、第３図は公知の単位容
量素子群の配置説明図、第４図は従来のエツチン
グ状況説明図、第５図は本発明の一実施例の配置
説明図である。
C1〜C2……容量、S1〜S2……電子スイツチ、
Ａ……増幅器、１……上部電極、２……下部電
極、３……絶縁層、４……コンタクト部、５……
接続用アルミ配線、６……エツチング部、７……
枠状パターン。
Fig. 1 is a circuit diagram of an example of a semiconductor integrated circuit having a capacitive element, Fig. 2 a and b are a plan view and a sectional view of an example of a known unit capacitive element, and Fig. 3 is an arrangement of a known unit capacitive element group. FIG. 4 is an explanatory diagram of a conventional etching situation, and FIG. 5 is an explanatory diagram of a layout of an embodiment of the present invention. C 1 ~ C 2 ... Capacity, S 1 ~ S 2 ... Electronic switch,
A...Amplifier, 1...Top electrode, 2...Lower electrode, 3...Insulating layer, 4...Contact part, 5...
Aluminum wiring for connection, 6...Etched part, 7...
frame pattern.
Claims (1)
量素子群を含む半導体集積回路において、前記単
位容量素子群を形成する上部電極群の周辺を前記
上部電極と同一の材料同一の加工条件で形成さ
れ、かつ前記一定間隔と実質的に等しい間隔を保
つて設けられた枠状パターンで囲むことを特徴と
する半導体集積回路。1. In a semiconductor integrated circuit including a plurality of unit capacitance element groups arranged at regular intervals, the periphery of the upper electrode group forming the unit capacitance element group is formed using the same material and the same processing conditions as the upper electrode. and is surrounded by a frame-like pattern provided at substantially equal intervals to the constant interval.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16978883A JPS6060751A (en) | 1983-09-14 | 1983-09-14 | Semiconductor integrated circuit |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP16978883A JPS6060751A (en) | 1983-09-14 | 1983-09-14 | Semiconductor integrated circuit |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS6060751A JPS6060751A (en) | 1985-04-08 |
| JPS6348186B2 true JPS6348186B2 (en) | 1988-09-28 |
Family
ID=15892883
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP16978883A Granted JPS6060751A (en) | 1983-09-14 | 1983-09-14 | Semiconductor integrated circuit |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS6060751A (en) |
Families Citing this family (4)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS6461043A (en) * | 1987-09-01 | 1989-03-08 | Nec Corp | Semiconductor device |
| JPH0864764A (en) * | 1994-08-25 | 1996-03-08 | Nippon Motorola Ltd | Unit capacitor |
| JP2004179419A (en) | 2002-11-27 | 2004-06-24 | Toshiba Corp | Semiconductor device and manufacturing method thereof |
| CN103765574B (en) | 2011-08-24 | 2017-06-30 | 瑞萨电子株式会社 | Semiconductor device |
-
1983
- 1983-09-14 JP JP16978883A patent/JPS6060751A/en active Granted
Non-Patent Citations (1)
| Title |
|---|
| IEEE JOURNAL OF SOLID-STATE CIRCUITS=1975 * |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6060751A (en) | 1985-04-08 |
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