JPH11312784A - Semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable a pair of capacitance devices to be controlled in capacitance and shortened in development period by a method, wherein a small capacitive device for control is connected to the capacitive devices and set trimmable. SOLUTION: Capacitive devices Ca and Cb are formed in an island region, the control capacitance element Cx are provided adjacent to the devices Ca and Cb. The capacitance elements Ca and Cb and the control capacitance elements Cx are connected in parallel with connection electrodes 11. A pattern of capacitance elements Ca and Cb is designed so as to realize a prescribed capacitance ratio of Ca to Cb, including the control capacitance element Cx. When the capacitance elements Ca and Cb is broken in a prescribed capacitance ratio, the connection electrodes 11 of the control capacitance elements Cx are cut off to control the capacitance elements Ca and Cb in capacitance. If the result of adjustment is satisfactory, the connection electrodes 11 are changed in pattern, and a semiconductor integrated circuit device of this constitution is put in production.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device incorporated in an integrated circuit and incorporating a capacitance element for obtaining a circuit capacitance ratio.

[0002]

2. Description of the Related Art In an integrated circuit network incorporated in a semiconductor integrated circuit device, for example, a plurality of active filter circuits are incorporated, and when a pair of these characteristics is required, the characteristics of a capacitive element included in the filter circuit are required. In some cases, the importance of pairing is important.

FIG. 3A shows an example of a capacitive element used in a BIP type integrated circuit. In the figure, 1 is a P-type semiconductor substrate, 2 is a P-type isolation region, 3 is an island region composed of an N-type layer surrounded by the isolation region 2, and 4 is an N-type island formed on the surface of the island region 3. A lower electrode region, 5 is an oxide film, 6 is a dielectric thin film such as a silicon nitride film, 7 is an aluminum upper electrode, and 8 is a lower electrode extraction electrode. The capacitance value is the dielectric thin film 6
Is roughly determined by the area in contact with the surface of the lower electrode 4,
This area is equal to the area of the opening 5a from which the oxide film 5 covering the lower electrode 4 has been removed.

For example, to obtain a capacitance ratio of 1: 3, as shown in FIG. 3B, the area of the opening 5a of the capacitor Cb is three times the area of the opening 5a of the capacitor Ca. In many cases, patterns were designed with the area of For example, if the capacitance element Ca is 5 pF and the capacitance element Cb is 15 pF,
The ratio between the two can be designed to be 1: 3. Incidentally, FIG.
FIG. 3B is a sectional view taken along line AA of FIG.

[0005]

The above-described capacitance element has an island region 3 in addition to the capacitance determined by the dielectric thin film 6.
(Embedding layer 9) and junction capacitance C1 between substrate 1 and island region 3
This is a structure in which the junction capacitance C2 of the isolation region 2 is inevitably connected. In particular, when a diffusion region of the same conductivity type as that of the island region 3 is used as the lower electrode region 4, the connection is made in parallel with the original capacitance, so that the values of the junction capacitances C1 and C2 directly affect the original capacitance.

[0006] With such an effect, FIG.
When the pattern design shown in FIG.
1. Since the ratio of the area of the PN junction forming C2 does not become the same as the designed capacitance ratio, there is a phenomenon that the ratio of the capacitance values collapses. That is, the opening 5a of the oxide film 5
Is designed to be 1: 3, the ratio of the PN junction area of the island regions 3 accommodating them is not 1: 3, and due to this effect, a deviation such as 5 pF: 16 pF is caused. It will happen.

Conventionally, a method has been adopted in which a prototype is developed first, the area of the opening 5b is adjusted based on the actually measured data, and the prototype is newly produced. However, the patterning process of the oxide film 5 is located relatively in the middle of the manufacturing process, so that even if a change is made, a longer time is required until the lot is completed, and the development time is longer. there were. It should be noted that even if the capacitance value fluctuates due to the influence of manufacturing variations,
The fact that the ratio of the capacitance values of the capacitance elements CA and CB does not collapse is referred to as good pairing.

[0008]

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned conventional problems, and is directed to a semiconductor integrated circuit device which obtains a capacitance ratio between a first capacitance element and a second capacitance element.
Connecting one or both of the first and second capacitive elements with a plurality of adjusting capacitive elements having a value smaller than the values of the first and second capacitive elements in parallel, and connecting the adjusting capacitive elements. Is cut so that the capacitance ratio of the first and second capacitance elements can be adjusted.

[0009]

DESCRIPTION OF THE PREFERRED EMBODIMENTS One embodiment of the present invention will be described below in detail with reference to the drawings.

In FIG. 1, a first capacitive element Ca and a second
Are arranged adjacent to each other, and an adjusting capacitance element Cx is arranged adjacent to each of them. The capacitance elements Ca and Cb and the adjustment capacitance element Cx each have the same structure as the cross-sectional structure shown in FIG. 3 and are individually housed in electrically isolated island regions 3.

Each of the capacitance elements Ca and Cb and the adjustment capacitance element C
x is connected in parallel by an electrode wiring 11 connected to the upper electrode 7. Assuming that the electrode wiring is, for example, a three-layer aluminum wiring, the electrode wiring is formed of a third wiring layer, that is, a wiring layer located at the uppermost layer. The lower electrodes 4 of these capacitive elements Ca, Cb, Cx are connected to the ground potential GND.

The capacitance element Cx for adjustment is designed to have a capacitance value of, for example, the minimum design unit of 1 pH. This capacitance value depends on the area of the opening 5 a of the oxide film 5 and the dielectric thin film 6.
Is controlled by the dielectric constant and the film thickness. In this example, assuming that one adjustment capacitance element Cx is connected to the capacitance element Ca and the value of the capacitance element Ca is 4 pF, the total capacitance value is 5 pF. The capacitance element Cb is connected to three adjustment capacitance elements Cx, and the value of the capacitance element Cb is 1
Assuming 2 pF, the total capacitance value is 5 pF.
This gives a capacity ratio of 5: 15 = 1: 3. After the completion of the prototype lot, the individual values of the capacitance elements Ca and Cb were measured,
Suppose that it turns out that the ratio of both has collapsed. For example, while the capacitance element Ca has a design value of 5 pF (with the total capacitance value), the finish is 4 pF, and the capacitance element Cb has a design value of 15 pF.
Assume that the finish is 13 pF in F (in the total capacitance value). In this case, 4 pF: 13 pF = 1: 3.25, and it is clear that the pairing property has been lost.

The capacitance value is adjusted by cutting the connection electrode 11 by laser trimming and separating the adjustment capacitance element Cx. In the above example, a ratio of 4 pF: 12 pF = 1: 3 is obtained by separating one adjusting capacitive element Cx connected to the capacitive element Cb. In this state, a measurement test is performed again. If a good result is obtained, the mask of the third-layer wiring from which the connection electrode 11 is cut is changed. Then, a lot stopped immediately before patterning of the third-layer aluminum wiring is manufactured using the changed mask.
With this method, the period from modification to completion of the finished product can be greatly reduced.

The adjustment capacitance element CX not connected is merely a dummy. For example, the number of the adjusting capacitive elements CX is
A ratio according to the value of the capacity ratio (in this example, 1: 3 = 1 piece:
3), the area ratio of the junction capacitances C1 and C2 generated in the island region 3 corresponds to this, so that it is possible to contribute to ensuring pairing.

FIG. 2 shows a second embodiment of the present invention. The previous embodiment adjusts the capacitance value,
Alternatively, the area ratio of the junction capacitance of the adjustment capacitance element CX can be matched with the capacitance ratio, but the area ratio of the junction capacitances C1 and C2 of the main body capacitance elements Ca and Cb cannot be matched. Therefore, in the present embodiment, the capacitance elements Ca and Cb are configured by connecting the unit capacitance elements Cy of the minimum trimming unit (for example, 1 pH) in parallel. Capacity value is 5:
If it is 15, five unit capacitance elements Cy are arranged to form a capacitance element Ca, and fifteen unit capacitance elements Cy are arranged to form a capacitance element Cb, and each is connected to the common electrodes 12 and 13 by the connection electrode 11. Each of the unit capacitance elements Cy is housed in the island region 3.

With such a configuration, in addition to the ratio of the capacitance value determined by the area of the opening 5a, the area ratio of the junction capacitances C1 and C2 inevitably generated in the island region 3 is determined by the designed capacitance ratio. Can be set to Therefore, a change in the capacitance value due to a manufacturing variation or the like appears completely in the capacitive elements Ca and Cb in the same manner, so that a configuration that does not affect the variation in the pairing property can be achieved. Moreover, since the capacitance value can be trimmed by cutting the connection electrode 11, the change is extremely easy.

[0017]

As described above, according to the present invention, the trimming of the capacitance value becomes possible by adding the adjusting capacitance element Cx to the element requiring the pairing of the capacitance values. Therefore, even if it turns out that the pairing is broken in the prototype, it is possible to immediately achieve the designed capacity ratio by adjusting the capacitance value, and immediately measure the effect of the result. . In addition, since the adjustment can be performed near the end of the manufacturing process, the product can be shipped immediately by changing the design and manufacturing using the lot stopped immediately before.

Further, according to the second embodiment, since only the trimming capacitance elements are connected in parallel to obtain the capacitance ratio, the ratio of the junction capacitances C1 and C2 of the island region 3 is also adjusted to the capacitance ratio. This has the advantage that the pairing of the capacitance values can be further improved.

[Brief description of the drawings]

FIG. 1 is a plan view for explaining the present invention.

FIG. 2 is a plan view for explaining a second embodiment of the present invention.

3A is a cross-sectional view for explaining a conventional example, and FIG.
It is a top view.

Claims (4)

[Claims] 1. A semiconductor integrated circuit device for obtaining a capacitance ratio between a first capacitor and a second capacitor, wherein one or both of the first and second capacitors are provided with the first and second capacitors. A plurality of adjustment capacitance elements having a value smaller than the value of the capacitance element are connected in parallel, and the capacitance ratio of the first and second capacitance elements can be adjusted by disconnecting the connection of the adjustment capacitance element. A semiconductor integrated circuit device characterized in that: 2. The multi-layer wiring according to claim 1, wherein the connection between the first or second capacitance element and the adjustment capacitance element is connected to an uppermost wiring layer of the multilayer wiring and cut off the uppermost wiring layer. 2. The semiconductor integrated circuit device according to claim 1, wherein: 3. The semiconductor integrated circuit according to claim 1, wherein each of the first and second capacitors and the adjustment capacitor is formed in an electrically isolated island region. apparatus. 4. The semiconductor integrated circuit device according to claim 1, wherein the first and second capacitance elements and the capacitance element for adjustment all have the same capacitance value. .