KR100475730B1 - Variable Capacitors and Manufacturing Methods - Google Patents

Abstract

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable capacitance capacitor capable of varying or increasing the capacitance of a capacitor without changing the design of a product. The present invention relates to a semiconductor device in which a capacitor is formed on an interlayer insulating film for insulating the lower structures and the upper wiring layer during multilayer wiring. The plurality of capacitors may include a plurality of metal patterns in which the capacitors are sequentially stacked and dielectric layers interposed between the metal patterns. In the present invention, in forming one metal pattern, one continuous metal pattern in series may be simultaneously used as the upper electrode of the lower capacitor and the lower electrode of the upper capacitor. One of them may be used as the upper electrode of the lower capacitor, and the other may be used as the lower electrode of the upper capacitor.

Description

Variable Capacitors and Manufacturing Method Thereof

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a variable capacitor, and more particularly, to a variable capacitor and a method of manufacturing the same, which are employed in precision analog devices.

The semiconductor device typically uses a capacitor such as a metal oxide-semiconductor (MOS) structure, a PN junction structure, a polysilicon-insulator-polysilicon (PIP) structure, and a metal-insulator-metal (MIM) structure.

Among these capacitors, all capacitors other than the MIM structure have limitations in reducing the resistance of the electrodes because at least one electrode is made of single crystal silicon or polycrystalline silicon. Therefore, it is difficult to realize a high speed capacitor using a single crystal or polycrystalline silicon as an electrode. This is because it is necessary to reduce the resistance of the capacitor electrode in order to reduce the frequency dependency in order to realize the high speed of the capacitor.

For this reason, in a semiconductor device requiring a high speed capacitor, as shown in FIG. 1, the first metal pattern 20 is provided as a lower electrode on the first interlayer insulating film 10 with the lower structure, and the first metal pattern 20 is formed thereon. A MIM capacitor in which another interlayer insulating film 12 having a contact hole, a dielectric film 32, and a second metal pattern 22 used as an upper electrode are sequentially stacked to expose a portion of the metal pattern 20 is used.

The MIM capacitor is made during the multi-layer wiring process due to the high integration of the semiconductor device, so that the electrode structure of low resistance can be easily realized. Temperature Coefficient for Capacitor) is lower than that of PIP capacitors, resulting in very good electrical properties. Therefore, it is mainly used for precision analog products.

However, MIM capacitors have a number of problems, such as time-consuming design changes and manufacturing of the product itself in order to vary the capacitance during the multilayer wiring process, and increase in size of the product to increase the capacitance.

Accordingly, an object of the present invention is to provide a variable capacitor capable of easily varying the capacitance in a multilayer wiring process.

Another object of the present invention is to provide a manufacturing method capable of efficiently manufacturing the variable capacitor.

A variable capacitor for achieving the object of the present invention is a semiconductor device for forming a capacitor on the interlayer insulating film for insulating the lower structures and the upper wiring layer in a multi-layer wiring, the capacitor is a plurality of metal patterns sequentially stacked And dielectric layers interposed between the metal patterns, a plurality of capacitors are connected in series.

The manufacturing method of the series variable capacitor includes: a first step of forming a first interlayer insulating film for insulating the lower structures formed on the semiconductor substrate and the wiring layers to be formed on the semiconductor substrate during the multi-layer wiring; A second step of forming a first metal pattern using a photo and etching process after depositing a metal on the resultant; Forming a contact hole so that a portion of the first metal pattern is exposed by selectively etching the second interlayer insulating layer on the resultant by using a photo and etching process; Forming a first dielectric film on the surface of the resultant material; Depositing a metal on the dielectric layer, and forming a second metal pattern forming a first capacitor together with the first metal pattern and the first dielectric layer by using a photolithography and an etching process; By repeating the fifth step from the third step, the third interlayer insulating film, the second dielectric film, and the third metal pattern forming the second capacitor together with the second metal pattern and the second dielectric film are sequentially formed on the resultant surface. It is characterized by the sixth step of forming.

According to another aspect of the present invention, a variable capacitor includes a first metal pattern formed on the first interlayer insulating layer in a semiconductor device in which a capacitor is formed on the first interlayer insulating layer to insulate the lower structures and the upper wiring layer during the multilayer wiring. And a second metal pattern in which a first metal layer stacked on top of the first metal pattern with a dielectric film interposed therebetween to form a first capacitor, and a second metal layer connected to the first metal pattern via vias are separated from each other. A third capacitor which is stacked on top of the second metal layer of the second metal pattern with a dielectric film interposed therebetween to form a second capacitor connected in parallel with the first capacitor, and is connected to the first metal layer of the second metal pattern through vias It is characterized by the inclusion of metal patterns.

The parallel variable capacitor has the same structure as the series capacitor described above by sequentially stacking a metal pattern and interposing a dielectric film therebetween. In the parallel capacitor, one metal pattern was separated into two, and one of them was used as the upper electrode of the lower capacitor and the other was used as the lower electrode of the upper capacitor.

A method of manufacturing such a parallel variable capacitor includes: a first step of forming a first interlayer insulating film for insulating the lower structures formed on the semiconductor substrate and the wiring layers to be formed on the semiconductor substrate during the multi-layer wiring; A second step of forming a first metal pattern using a photo and etching process after depositing a metal on the resultant; A third step of forming a first contact hole so that a part of the first metal pattern is opened by selectively etching the second interlayer insulating layer on the resultant by using a photo and etching process; Forming a first dielectric film on the surface of the resultant material; A fifth step of forming a first via such that a portion of the first metal pattern is opened by using a photo and etching process from an upper portion of the resultant; After depositing a metal on the surface of the resultant through a first metal layer and the first via positioned on the first contact hole using a photo and etching process to form a first capacitor together with a first metal pattern and a first dielectric layer A sixth step of forming a second metal pattern such that the second metal layer for connecting in parallel with the second capacitor to be formed in the upper portion is separated; Forming a second contact hole so that a part of the second metal layer of the second metal pattern is opened by selectively etching the third interlayer insulating film on the resultant surface by using a photo and etching process; An eighth step of forming a second via so as to open a portion of the first metal layer of the second metal pattern by using a photolithography and an etching process after forming a second dielectric layer on the surface of the resultant; After depositing the metal on the resultant surface, a second capacitor is formed together with the second metal layer and the second dielectric layer of the second metal pattern using a photolithography and an etching process, and then connected through the first metal layer and the second via of the second metal pattern. It is characterized by including a ninth step of forming a third metal pattern to be formed.

Hereinafter, a variable capacitor according to the present invention will be described in detail with reference to the accompanying drawings.

2 to 11 are vertical cross-sectional views illustrating an embodiment of a series variable capacitance capacitor according to an exemplary embodiment of the present invention, in which a plurality of capacitors are stacked by successively repeating a method using a conventional two-layer wiring.

2 to 6 show a process of manufacturing a first capacitor by performing a method using a conventional two-layer wiring as it is.

Specifically, as shown in FIG. 2, first, a transistor including a gate electrode and a source / drain region as a lower structure is formed on a semiconductor substrate, and then the upper structures and contact holes (not shown) to be formed in a subsequent process are formed. A first interlayer insulating film 10 is formed to insulate in all regions except for the above, and a metal, for example, aluminum, an aluminum alloy, copper, or a copper alloy is deposited on the first interlayer insulating film 10 and then photographed and etched. After forming the first electrode wiring layer for connecting the first metal pattern 20 to be used as the lower electrode of the first capacitor and the device, a second interlayer insulating film 12 is formed over the first electrode wiring layer.

Hot temperature oxide (HTO) or Boro-Phospho Silicated Glass (BPSG) is deposited and used as the first and second interlayer insulating films 10 and 12.

Next, as shown in FIGS. 3 and 4, a photoresist for defining the shape of the metal pattern to be used as the upper electrode of the second capacitor and the lower electrode of the first capacitor on the second interlayer insulating film 12. 40) A pattern is formed and a contact hole is formed by performing a tapered dry etching process so that a part of the surface of the first metal pattern 20 is opened using the pattern as an etching mask.

Next, after the photoresist 40 is removed, an oxide film or a plasma nitride film such as a first dielectric film 32, for example, a plasma oxide film, a p-SiH ₄ oxide film, a high density plasma oxide film, and the like is formed on the entire upper surface of the resultant product as shown in FIG. 5. The same nitride film is deposited.

Subsequently, as shown in FIG. 6, a metal (aluminum, aluminum alloy, copper, copper alloy, etc.) is again deposited on the surface of the first dielectric layer 32, and then the upper electrode of the first capacitor is simultaneously formed using a photographic and etching process. The second metal pattern 22 and the second electrode wiring layer provided as the lower electrode of the second capacitor are patterned and formed.

Next, as shown in FIG. 7, after the third interlayer insulating film 14 is formed on the resultant, a first capacitor as shown in FIGS. 4 to 6 is manufactured as shown in FIGS. 8 to 11. A second dielectric film 34, a third metal pattern 24, which is an upper electrode of the second capacitor, and a third electrode wiring layer are simultaneously formed on the third interlayer insulating film 14 in the same order as the process.

Here, reference numeral 42 shows a photoresist pattern for defining the shape of the upper electrode of the second capacitor.

The variable capacitance capacitor manufactured by this process is connected to two capacitors in series using a three-layer metal wiring process, but further capacitors may be formed by an additional wiring process to obtain a desired capacitance.

The series variable capacitance capacitor is formed of three layers of metal patterns successively stacked and a dielectric film between the metal patterns, so that, for example, the capacitance of the first capacitor is 4 pF as shown in FIG. When the capacitance of the two capacitors is 2pF, the total capacitance of the two capacitors can provide a variable capacitance of about 1.3pF to 4pF.

13 to 25 illustrate examples of parallel variable capacitors according to the present invention in the order of manufacturing process.

Referring first to FIG. 13, like a series variable capacitor, a transistor including a gate electrode and a source / drain region as a lower structure is formed on a semiconductor substrate, and then the upper structures and contact holes to be formed in a subsequent process are formed. After forming the first interlayer insulating film 10 to insulate in all regions except for, and depositing a metal thereon, the first metal pattern to be used as the lower electrode of the first capacitor using the photoresist 40a as an etching mask After the first electrode wiring layer for connecting the element 22 with the element 22 is formed, a second interlayer insulating film 12 is subsequently deposited and formed thereon.

Next, as shown in FIGS. 14 and 15, the second interlayer insulating film 12 is tapered dry-etched to open a portion of the surface of the first metal pattern 20 using the photoresist 40a as an etching mask. After forming the first contact hole, the photoresist 40a is removed and the first dielectric layer 32 is deposited on the resultant as shown in FIG. 16.

Next, as shown in FIGS. 17 and 18, a photoresist 41 pattern is formed on an upper portion of the resultant, and the first dielectric layer 32 is formed at a distance from the first contact hole by using the photoresist 41 pattern as an etching mask. And selectively etching the second interlayer insulating layer 12 to form a first via 50 so that a part of the first metal pattern 20 is opened.

When forming the first via 50, first, an upper layer of the first dielectric layer 32 and the second interlayer insulating layer 12 is etched using isotropic wet etching, and then the remaining portion of the second interlayer insulating layer 12 is dried using dry etching. It is preferable to etch.

Subsequently, as shown in FIG. 19, a metal is deposited on the upper part of the resultant, and is interviewed with the first dielectric layer 32 through the first contact hole by using a photolithography and etching process. The second metal pattern and the second metal wiring layer are patterned and formed to separate the second metal layer 22a connected to the first metal pattern 20 through the first metal layer 22 and the first via 50 forming the capacitor. do.

Next, as shown in FIG. 20, the third interlayer insulating film 14 is deposited on the resultant, and then the photoresist 42 pattern is used as an etch mask as shown in FIGS. 21 and 22. The photoresist 42 is removed after the third interlayer insulating layer 14 is selectively etched to form a second contact hole so that a part of the second metal layer 22a is opened.

Next, as shown in FIG. 23, a second dielectric layer 34 is deposited on the resultant, and another photoresist is used as an etch mask. As shown in FIG. 24, the first metal layer 22 of the second metal pattern is illustrated. The second via 52 is formed so that a portion of the portion is open. The formation method of the second via 52 is the same as the formation method of the first via 50.

Next, as shown in FIG. 25, after depositing a metal on the entire upper surface of the resultant, the second dielectric layer 34 is connected to the first metal layer 22, which is the upper electrode of the first capacitor, through the second via 52. ), The third metal pattern 24 and the third metal wiring layer forming the second metal layer 22a and the second capacitor of the second metal pattern are formed.

The parallel variable capacitance capacitor manufactured by the method as described above is continuously and repeatedly proceeded through the process steps shown in FIGS. 14 to 25 on top of the resultant to secure the desired capacitance. Can be formed.

Such a parallel variable capacitor is formed of a dielectric film between the metal layers of the three layers and the metal layers continuously stacked like the series capacitor described above, and as shown in FIG. 16, for example, the capacitance of the first capacitor Is 2pF and the capacitance of the second capacitor is 2pF, the total capacitance of the two capacitors is about 4pF.

As described in detail above, according to the present invention, the capacitance of the capacitor can be varied, as well as the capacitance of the capacitor by a simple method of manufacturing a plurality of capacitors using the technology used for manufacturing the capacitor in the existing two-layer wiring. To increase the bar, there is an effect that can reduce the design change of the product due to the variable capacitance of the capacitor and the resulting manufacturing time.

1 is a vertical cross-sectional view of a conventional capacitor.

2 to 11 are vertical cross-sectional views showing an embodiment of the series variable capacitance capacitor according to the present invention in the order of manufacturing process.

FIG. 12 is an equivalent circuit diagram of the series variable capacitance capacitor shown in FIG. 11.

13 to 25 are vertical cross-sectional views showing an embodiment of a parallel variable capacitor in accordance with the present invention in the manufacturing process order.

FIG. 26 is an equivalent circuit diagram of the parallel variable capacitance capacitor shown in FIG. 25.

Explanation of symbols on the main parts of the drawings

10,12,14 interlayer insulating film 20,22,22a, 24 metal pattern

32,34: dielectric film 40,40a, 42: photoresist

50,52: Via

Claims (6)

In a semiconductor device in which a capacitor is formed on the first interlayer insulating film for insulating the lower structures and the upper wiring layer in the multilayer wiring, A first metal pattern formed on the first interlayer insulating film; A second metal pattern having a first metal layer stacked on top of the first metal pattern with a dielectric layer interposed therebetween to form a first capacitor, and a second metal pattern separated from a second metal layer connected via a via to the first metal pattern; A second capacitor stacked on top of the second metal layer of the second metal pattern with a dielectric film interposed therebetween to form a second capacitor connected in parallel with the first capacitor, and connected to the first metal layer of the second metal pattern via a via; 3 Capacitive capacitor comprising a metal pattern. The variable capacitance capacitor of claim 1, wherein the first, second, and third metal patterns are aluminum, copper, or an alloy thereof. The variable capacitor of claim 1, wherein the dielectric layer is an oxide layer or a nitride layer. The variable capacitance capacitor of claim 1, wherein a plurality of capacitors having the same structure as the second capacitor are further stacked on the second capacitor. A first step of forming a first interlayer insulating film to insulate the lower structures formed on the semiconductor substrate and the wiring layers to be formed on the semiconductor substrate during the multilayer wiring; A second step of forming a first metal pattern using a photo and etching process after depositing a metal on the resultant; A third step of forming a first contact hole so that a part of the first metal pattern is opened by selectively etching the second interlayer insulating layer on the resultant by using a photo and etching process; Forming a first dielectric film on the surface of the resultant material; A fifth step of forming a first via such that a portion of the first metal pattern is opened by using a photo and etching process from an upper portion of the resultant; After depositing a metal on the surface of the resultant through a first metal layer and the first via positioned on the first contact hole using a photo and etching process to form a first capacitor together with a first metal pattern and a first dielectric layer A sixth step of forming a second metal pattern such that the second metal layer for connecting in parallel with the second capacitor to be formed in the upper portion is separated; Forming a second contact hole so that a part of the second metal layer of the second metal pattern is opened by selectively etching the third interlayer insulating film on the resultant surface by using a photo and etching process; An eighth step of forming a second via so as to open a portion of the first metal layer of the second metal pattern by using a photolithography and an etching process after forming a second dielectric layer on the surface of the resultant; After depositing the metal on the resultant surface, a second capacitor is connected to the first capacitor in parallel with the second metal layer and the second dielectric layer of the second metal pattern by using a photolithography and an etching process. And a ninth step of forming a third metal pattern connected through the first metal layer and the second via. The method of claim 5, wherein the first and second vias are formed by mixing wet and dry etching.

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