JP2000311964A - Semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To obtain a semiconductor device which is capable of preventing signals from being delayed due to capacitance in signal lines reducing power supply/ground noises. SOLUTION: An inner circuit 14 and a ground pad 11, and a power supply pad 11 and a signal pad 13 are connected together with pad wiring layers 31, 32, and 33 respectively. Wiring layers 34, 35, 36, and 37 are formed extending under the pad wiring layers 31, 32, and 33 in a wiring region between the pads and the inner circuit, so as to surround the inner circuit 14. The wiring layers 35 and 36 are connected to the power supply pad wiring layer 32 via contacts 24, and a gap 30 occupied by an insulating film is provided between the wiring layers 35 and 36. The signal wiring layer 33 crosses the wiring layers 34 to 37 at right angles in a plan view.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a power supply pad and a signal pad arranged at a peripheral portion of a semiconductor chip, an internal circuit arranged at a central portion, and a wiring region of a multilayer wiring structure arranged between the internal circuit and the pad. To a semiconductor device.

[0002]

2. Description of the Related Art Generally, a semiconductor device has an internal circuit, and the internal circuit is composed of a plurality of circuit blocks on which elements such as transistors are formed. In a semiconductor device, an internal circuit and a pad are connected by a wiring obtained by patterning a single wiring layer, the pad is connected to an external circuit via a bonding wire and an external connection lead, and the internal circuit is connected to an external circuit. And electrical signals are exchanged.
In such a conventional semiconductor device, a smoothing capacitor is connected between a power supply terminal and a ground terminal outside the semiconductor device so that noise is not transmitted from an external power supply to the inside of the semiconductor device.

In recent years, when the frequency of signals handled by a semiconductor device has reached several hundred MHz, bonding wires, external connection leads, and the like act as a common impedance (inductance, etc.) for a plurality of circuit blocks. It became so. For this reason, noise generated in a certain circuit block in the semiconductor device is transmitted to another circuit block, causing a malfunction and a deterioration in operation accuracy. Even if a smoothing capacitor is provided outside the semiconductor device, a sufficient smoothing effect cannot be obtained with respect to noise generated inside.

In order to prevent interaction between circuit blocks due to such noise, a dedicated power supply /
A ground terminal may be provided. However, with the increase in the circuit scale, the number of circuit blocks of the internal circuit also increases, the number of power supply / ground terminals increases, and the size of the package on which the semiconductor device is mounted also increases.

In order to solve the former problem, Japanese Patent Laid-Open No.
Japanese Patent Publication No. -307077 (hereinafter referred to as Conventional Example 1)
Use unused pads that are not used for external connections,
It is disclosed to form a decoupling capacitor. In this publication, a plurality of wiring layers are stacked with an insulating film interposed therebetween, and a power supply wiring and a ground wiring are alternately arranged every other layer to increase the stray capacitance. However, an unused pad cannot always be formed near a predetermined circuit block, and a desired floating capacitance cannot be obtained, or a sufficient smoothing effect can be obtained due to resistance of a wiring for connecting to an unused pad. Was not obtained.

In Japanese Patent Application Laid-Open No. 5-283611 (hereinafter referred to as Conventional Example 2), a power supply wiring and a ground wiring are wrapped around an internal circuit of a semiconductor device, and are arranged to face each other. It is disclosed that a decoupling capacitor is formed to reduce noise. Increasing the number of power / ground terminals by making the power supply wiring and the ground wiring a circular wiring, adding a new process for forming a circular wiring layer, and forming irregularities or forming a high dielectric constant film. Instead, the circuit block can obtain a power supply potential and a ground potential with low impedance from the nearest surrounding wiring.

Hereinafter, the configuration of a conventional semiconductor device will be described with reference to the drawings. FIG. 20 is a plan view showing a conventional semiconductor chip. As shown in FIG. 20, a power supply pad 1, a ground pad 2 and a signal pad 3 are arranged at the periphery of the chip, an internal circuit 4 is arranged at the center of the chip, and the power supply pad 1 and the terminals of the internal circuit 4 Are connected by a power supply wiring 5, the ground pad 2 and the terminal of the internal circuit 4 are connected by a ground wiring 6, and the signal pad 3 and the terminal of the internal circuit 4 are further connected by a signal wiring 7. Connected.

A power supply wiring layer 9 extending so as to surround the internal circuit 4 and a ground wiring layer 8 are formed parallel to each other so as to go around the internal circuit 4 or to go around the upper layer and the lower layer. Is formed. In the publication of Conventional Example 2, the latter configuration is described, in which an insulating film having a high dielectric constant is formed between an upper layer and a lower layer, and irregularities are formed on the upper and lower wiring layers. As shown in this prior art, by arranging a power supply wiring layer and a ground wiring layer with an insulating film interposed therebetween, a capacitance is formed between the power supply wiring layer and the ground wiring layer. By configuring a low-pass filter, power / ground noise can be reduced.

[0009] Another conventional technique (conventional example 3) has the following problem. In the case where the conventional internal circuit is miniaturized and the semiconductor device is operated at high speed due to the evolution of the manufacturing method, if the size of the package is reduced in accordance with the miniaturization of the internal circuit, a good product of the internal circuit or When inspecting a defective product (die sort test), it is necessary to change the pin arrangement of the prober, the bonding position information of the bonding tool needs to be changed, or the size of the package used by a user who uses the package increases. Inconvenience may occur due to fluctuations in the height. For this reason, even if the internal circuit is miniaturized, the size of the package itself is not miniaturized, and it is sometimes desired to keep the arrangement of the pads.

In this case, it is necessary to connect the pads 1 to 3 arranged at the periphery of the chip and the internal circuit 4 (core) with long wirings 5 to 7. Therefore, this wiring 5
7, the influence of the inductance and resistance components increases, and in this case, the internal circuit 4 is likely to malfunction.

[0011]

However, in the conventional example 2 described in the above-mentioned publication, in the wiring region between the pad and the internal circuit, the signal wiring connecting the pad and the internal circuit and the power supply wiring layer are formed. However, there is a problem in that a parasitic capacitance is added between them, and signal delay occurs.

Further, the wiring near the end of the side of the chip has a longer wiring length than the wiring near the center of the side, the parasitic resistance and the parasitic capacitance of the wiring are larger, and the delay time is longer than the wiring near the center of the side. Become. For this reason, even if a signal is supplied from the outside at the same timing, there is a difference in the time to reach the internal circuit, which causes a problem that the signal cannot be taken in accurately.
In particular, as the operating frequency of the semiconductor device increases, the influence of this difference in delay time cannot be ignored.

The second conventional example also has a problem that the manufacturing cost is increased because a new manufacturing process of forming a peripheral power supply wiring is added to increase the decoupling capacitance.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor device capable of preventing a signal from being delayed due to a capacitance on a signal line while reducing power / ground noise. Aim. It is another object of the present invention to provide a semiconductor device capable of preventing a delay time of a signal line connecting a pad and an internal circuit from being varied depending on a pad position and reducing the delay time difference. It is in.

[0015]

A semiconductor device according to the present invention comprises a first power supply pad and a second
A power supply pad and a signal pad; an internal circuit disposed in the center of the chip; and a wiring region formed by multilayer wiring laminated through an insulating film in a region between each of the pads and the internal circuit. A first power supply pad formed on the upper insulating film and connected to the first power supply pad and the second power supply pad, respectively;
The wiring region, comprising: a power supply pad wiring layer and a second power supply pad wiring layer; and a signal wiring layer formed on the uppermost insulating film and connecting the signal pad and the internal circuit. A first power supply wiring layer and a second power supply wiring layer connected to the first power supply pad wiring layer or the second power supply pad wiring layer via contacts, respectively, so as to surround the internal circuit. The uppermost first power supply wiring layer is divided into a plurality of parts in a direction from the internal circuit toward a chip edge.

Another semiconductor device according to the present invention includes a first power supply pad, a second power supply pad, and a signal pad disposed in a peripheral portion of a chip, an internal circuit disposed in a central portion of the chip, and A wiring region formed of multilayer wiring laminated on a region between a pad and the internal circuit via an insulating film; and a first power supply pad and a second power supply pad formed on the uppermost insulating film. A first power supply pad wiring layer and a second power supply pad wiring layer connected to each other; and a signal wiring layer formed on the uppermost insulating film and connecting the signal pad and the internal circuit. A first power supply wiring layer connected to the first power supply pad wiring layer or the second power supply pad wiring layer via a contact and extending so as to surround the internal circuit; 2 Wiring layer for power supply The first power supply wiring layer is divided into a plurality of layers in a direction from the internal circuit toward the edge of the chip, and a conductive layer connected to the first power supply wiring layer is provided between each first power supply wiring layer. A semiconductor device, characterized by the absence of any.

The distance between the first and second power supply wiring layers may be smaller than the distance between the first and second power supply wiring layers immediately below the first and second power supply wiring layers. In the signal wiring layer, a portion that intersects the first power supply wiring layer and / or the second power supply wiring layer in a plan view has a first power supply wiring layer and / or a second power supply wiring layer.
Or perpendicular to the second power supply wiring layer, or
It is preferable that the power supply wiring layer and / or the second power supply wiring layer be inclined at the same angle.

Still another semiconductor device according to the present invention includes a first power supply pad, a second power supply pad, and a signal pad disposed in a peripheral portion of a chip, an internal circuit disposed in a central portion of the chip, A wiring region composed of multilayer wiring laminated on a region between each pad and the internal circuit via an insulating film; and a first power supply pad and a second power supply pad formed on the uppermost insulating film A first power supply pad wiring layer and a second power supply pad wiring layer respectively connected to the first power supply pad wiring layer, and a signal wiring layer formed on the uppermost insulating film and connecting the signal pad and the internal circuit; And the wiring region is provided on a first insulating film formed on a substrate.
A layer wiring layer, a second layer wiring layer disposed on the second insulating film formed on the first insulating film, and a third insulating film formed on the second insulating film. A third layer wiring layer, wherein the first to third layer wiring layers extend so as to surround the internal circuit, and the third layer wiring layer and the second layer wiring layer are connected via a contact. The first power supply pad wiring layer is connected to the first power supply pad wiring layer via a contact, and the first power supply pad wiring layer is connected to the first power supply pad wiring layer via a contact;
A capacitor is formed between a layer wiring layer and the second layer wiring layer, and the third layer wiring layer is divided into a plurality of layers.

In this semiconductor device, another wiring layer connected to the first power supply pad wiring layer via a contact is provided between the first wiring layer and the substrate. And the first wiring layer to form a capacitor.

For example, a power supply line for supplying an internal circuit is connected to the first power supply pad, and the second power supply pad is connected to ground.

Still another semiconductor device according to the present invention includes a first power supply pad, a second power supply pad, and a signal pad disposed in a peripheral portion of a chip, an internal circuit disposed in a central portion of the chip, A wiring region composed of multilayer wiring laminated on a region between each pad and the internal circuit via an insulating film; and a first power supply pad and a second power supply pad formed on the uppermost insulating film A first power supply pad wiring layer and a second power supply pad wiring layer respectively connected to the first power supply pad wiring layer, and a signal wiring layer formed on the uppermost insulating film and connecting the signal pad and the internal circuit; Wherein the wiring region includes a first power supply wiring layer and a second power supply wiring layer connected to the first power supply pad wiring layer or the second power supply pad wiring layer via contacts, respectively. Extends around the internal circuit In each of the signal wiring layers, a portion intersecting the first power supply wiring layer in a plan view is orthogonal to the first power supply wiring layer, or has the same angle with respect to the first power supply wiring layer. It is characterized by being inclined at.

Still another semiconductor device according to the present invention has a power supply wiring layer formed around the periphery of a chip, the power supply wiring layer being formed in a plurality of wiring layers, and an upper power supply wiring layer. The area of the wiring layer for power supply is smaller than that of the lower wiring layer for power supply.

In this semiconductor device, the upper power supply wiring layer has first and second power supply wiring layers formed in a circular shape, and the first and second power supply wiring layers are spaced apart from each other by the first distance. It can be configured to be wider than the width of the first or second power supply wiring layer. Further, the upper power supply wiring layer can be used as a relay wiring with a lower power supply wiring layer.

[0024]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Embodiments of the present invention will be specifically described below with reference to the accompanying drawings. FIG. 1 is a plan view showing an arrangement of each layer of a semiconductor device according to an embodiment of the present invention, FIG. 2 is a sectional view taken along line AA of FIG. 1, and FIG.
FIG. 4 is a sectional view taken along line CC of FIG. FIG. 1 is an enlarged plan view of a corner portion of the semiconductor device. As shown in FIG. 1, an internal circuit 14 is disposed at a central portion of a semiconductor chip, and a ground pad 11 and a power supply pad 12 are provided at a peripheral portion of the semiconductor chip. And signal pads 13 are arranged. In a region between each of the pads 11 to 13 and the internal circuit 14, a wiring having a multilayer wiring structure is formed so as to surround the internal circuit 14, thereby forming a wiring region.

That is, a P-well region 17 is selectively formed on the surface of the semiconductor substrate 16, and an ohmic contact between the contact and the P-well region 17 is formed in the P-well region 17. P ⁺ region 18 is formed for removing the current.

An insulating film 19 made up of a plurality of insulating films is formed on the semiconductor substrate 16, and a first layer power supply (VC) made of a polysilicon film is formed on the lowermost insulating film.
C) A wiring layer 42 is formed, a second-layer ground (GND) wiring layer 41 made of a metal such as aluminum is formed on the insulating film thereon, and a metal such as aluminum is formed on the insulating film thereon. Power supply (VCC) wiring layer 39 made of
And third-layer ground (GND) wiring layers 38 and 40 are formed. Furthermore, a fourth layer power supply (VC
C) Wiring layers 35 and 36 and fourth-layer ground (GND) wiring layer 3
4, 37 are formed. On the surface of the insulating film 19, a radial ground (GND) pad wiring layer 31, a power supply (VCC) pad wiring layer 32, and a signal wiring layer 33 for connecting the pads 11 to 13 and the internal circuit 14 are provided. Is formed. That is, the ground pad 11 and the internal circuit 14 are connected by the ground pad wiring layer 31, and the power pad 1
2 and the internal circuit are connected by a power supply pad wiring layer 32, and the signal pad 13 and the internal circuit 14 are connected by a signal wiring layer 33. Although not shown in FIGS. 1 to 3, a cover insulating film for protecting the surface of the semiconductor device is formed on the insulating film 19 except for the pads 11 to 13 and the wiring layers 31 to 33. In the following description, this is not called the uppermost insulating film.

The first power supply wiring layer 42 made of a polysilicon film in the insulating film 19 is disposed so as to surround the internal circuit 14 and has a relatively wide width occupying almost the entire width of the wiring region in the width direction. The second-layer ground wiring layer 41 is also arranged so as to surround the internal circuit 14 and has a wide width occupying almost the entire area in the width direction of the wiring region. Although the width of the layer 41 is slightly wider than that of the first power supply wiring layer 42, the width of the second ground wiring layer 41 is smaller than the width of the first power supply wiring layer 42 where the contact 20 is not formed. Is the same as

In the third layer, three wirings, that is, a ground wiring layer 38, a power supply wiring layer 39, and a ground wiring layer 40 are formed so as to surround the internal circuit 14 in a triple manner.
4 in this order. In the fourth layer, four wirings, that is, the ground wiring layer 34, the power supply wiring layer 35, the power supply wiring layer 36, and A ground wiring layer 37 is formed. FIG. 1 shows the fourth wiring layers 34 to 37 in addition to the wiring on the insulating film 19.

The first power wiring layer 42 and the second ground wiring layer 41 can be formed by patterning a polysilicon film and a metal film to a predetermined width, respectively. Further, the third-layer ground wiring layers 38 and 40 and the third-layer power supply wiring layer 39 can be formed by patterning a metal film formed in the wiring region into three ring-shaped wirings. Layers 34 and 37 and a fourth power supply wiring layer 35,
36 can be formed by patterning a metal film into four ring-shaped wirings. Further, the insulating film 19
The upper wirings 31, 32, and 33 can be similarly formed by patterning a metal film.

As shown in FIGS. 1 and 2, the ground pad wiring layer 31 connected to the ground pad 11 and the fourth ground wiring layers 34 and 37 under the ground pad wiring layer 31 form an insulating film therebetween. They are connected by the formed contact 23.
As shown in FIGS. 1 and 4, the power supply pad wiring layer 32 connected to the power supply pad 12 and the fourth power supply wiring layers 35 and 36 under the power supply pad wiring layer 32 are formed in an insulating film therebetween. They are connected by a contact 24.

As shown in FIGS. 2 and 4, the fourth-layer ground wiring layers 34, 37 and the third-layer ground wiring layers 38, 4
0 is connected by the contact 22, and the fourth power supply wiring layers 35 and 36 and the third power supply wiring layer 39 are connected by the contact 22.

Further, the third ground wiring layers 38 and 40 are
The three ground wiring layers 41 are connected by contacts 21.
Have been. Then, the ground wiring layer 41 of the second layer and the substrate surface
P ⁺The region 18 is connected by a contact 20.
You.

Further, as shown in FIG. 3, the third power supply wiring layer 39 and the first power supply wiring layer 42 are connected by a contact 26. This contact 26 is
The second ground wiring layer 41 is inserted through the opening 28 provided in the layer ground wiring layer 41 so as not to contact the second ground wiring layer 41. Also, the second-layer ground wiring layer 41
And a P ⁺ region 18 on the substrate surface are connected by a contact 25. The contact 25 passes through the first power supply wiring layer 42 so as not to contact the first power supply wiring layer 42 through the opening 27 provided in the first power supply wiring layer 42.

Of the wiring in the insulating film 19, the fourth
In the layer wiring layers, the power supply wiring layers 35 and 36 are commonly connected to a third power supply wiring layer 39 below the power supply wiring layers 35 and 36.
The power supply wiring layers 35 and 36 are separated from each other with a slit (gap) 30 therebetween. The gap 30 is formed by etching and removing this portion when patterning the wiring layers 34 to 37.

The signal pad 1 is formed on the insulating film 19.
A signal wiring 33 connecting the internal circuit 3 and the internal circuit 14 is formed. The signal wiring 33 vertically intersects the ground wiring layer 37 and the power supply wiring layer 36 below it on the pad 13 side in plan view, and intersects the lower power supply wiring layer 35 and ground wiring layer 34 on the internal circuit 14 side in plan view. Intersects vertically. The arrangement pitch of the signal pads 13 is larger than the arrangement pitch of the input terminals of the signal lines in the internal circuit 14, and
Since the relative positional relationship between them is arbitrary, the internal circuit 14
The signal wiring layer 33 connecting the signal line input terminal and the signal pad 13 has an inclined portion 15 that extends at an incline with respect to the chip edge at the center. That is, the signal wiring layer 33
The portion on the side of the pad 13 and the side of the internal circuit 14 extends perpendicularly to the lower fourth wiring layer extending in parallel with the edge of the chip, and a portion between the vertical portions extends obliquely with respect to the edge of the chip. It has become. Some of the signal wiring layers arranged in the center of the chip extend linearly. In any case, the signal line wiring is formed by the lower power supply wiring layers 33 and 35 and the ground wiring. In the portion where the layers 37 and 34 intersect, they extend perpendicular to them.

Further, the fourth power supply wiring layers 35 and 36 and the ground wiring layers 34 and 37 are arranged close to a limit in a photolithography (PR) process for patterning these wiring layers. Have been. The wiring layer 35
In order to reduce the parasitic capacitance between the wirings 31 to 33, the line width of
It is desirable that the width be the minimum width that can be relayed to .about.24, and in a region where there is no contact, it is desirable that the width be as narrow as possible near the limit in the photolithography (PR) process. It is desirable that the width of the gap 30 be wide for the same reason.

The power supply (VCC) is called a first power supply, and the ground (GND) is called a second power supply.

Next, the arrangement of each layer of the semiconductor chip will be described. 5A and 5B are plan views showing the whole of each layer. FIG. 5A shows the uppermost layer, FIGS. 5B to 5E show the lower layers sequentially, and FIG. 5F shows the arrangement of diffusion layers on the surface of the semiconductor substrate. FIG. 5A is a diagram showing the entire arrangement of the pad wiring layer in FIG. 1, and FIG. 5B is a diagram showing the entire arrangement of the fourth-layer wiring layer therebelow, which are shown in FIG. I have. And
5C is a diagram illustrating the entire layout of the third wiring layer, FIG. 5D is a diagram illustrating the entire layout of the second wiring layer, and FIG. 5E is a diagram illustrating the entire layout of the first wiring layer. , FIG. 5 (c), (d),
FIGS. 6, 7, 8 and 9 show enlarged views of a quarter of (e) and (f), respectively. FIG. 1 is a partially enlarged view of FIGS. 5A and 5B.

As shown in FIG. 5A, the pad wiring layer 3 connected to the ground pad 11, the power supply pad 12, and the signal pad 13 extends from the peripheral portion of the chip toward the internal circuit 14.
1, 32, and 3 are formed. As shown in FIG. 5B, the power supply in the fourth layer is formed so as to surround the internal circuit 14 four times below the pad wiring layers 31, 32, and 33. Wiring layers 35 and 36 and ground wiring layers 34 and 37 are formed.

Further, under the fourth layer, as shown in FIGS. 5 (c) and 6, the third power supply wiring layer 39 and the third wiring layer 38 surround the internal circuit 14 in three layers. ,
40 are formed. The power supply wiring layer 39 is connected to the upper (fourth) power supply wiring layers 35 and 3 via the contact 22.
6 and the ground wiring layers 38 and 40 are
Are connected to the ground wiring layers 34 and 37 of the fourth layer via. Further, as shown in FIGS. 5D and 7, a second-layer ground wiring layer 41 surrounding the internal circuit 14 is formed below the third layer. In addition, the second ground wiring layer 4
1 is connected to the upper (third layer) ground wiring layers 38 and 40 via the contacts 21. Further, the ground wiring layer 41
Has a plurality of openings 28, and inside the openings 28 are upper (fourth layer) power supply wiring layers 35 and 36 and lower layers (first layer).
The contact 26 for connecting the power supply wiring layer 42 is inserted. Here, the upper (fourth) power supply wiring layer 35,
An example is shown in which the contact 26 connecting the power supply wiring layer 36 and the lower (first layer) power supply wiring layer 42 is formed in a single manufacturing step, but the inside of the opening 28 is the same as the ground wiring layer 41 of the second layer. The contact 26 may be formed in separate (two times) manufacturing steps by providing a relay wiring layer formed in the steps.

Further, a first power supply wiring layer 42 surrounding the internal circuit 14 is formed under the second layer, as shown in FIGS. The first power supply wiring layer 42 is connected to the upper (third) power supply wiring layer 39 via the contact 26. Further, the power supply wiring layer 4
2, a plurality of openings 27 are formed.
Inside the upper (second layer) ground wiring layer 41 and the lower layer P
^The contact 25 connecting the ⁺ region 18 is inserted. Here, an example is shown in which the contact 25 connecting the upper (third) power supply wiring layer 39 and the lower P ⁺ region 18 is formed in one manufacturing process. A relay wiring layer formed in the same step as the power supply wiring layer 42 may be provided, and the contacts 25 may be formed in separate (two times) manufacturing steps. The first power supply wiring layer 42 is formed of polysilicon, and the second to fourth wiring layers and the pad wiring layers 31 to 33 are formed of metal such as aluminum.

On the surface of the semiconductor substrate 16, a P-well 17 extending in a ring shape around the internal circuit 14 is formed so as to match with the above-mentioned wiring layer. The P ⁺ region 18 formed on the surface of the P well 17 corresponds to FIG.
(F) and as shown in FIG. 9, the first power supply wiring layer 42
Is connected to the ground wiring layer 41 of the second layer via a contact 25 inserted into the opening 27 formed in the second layer.

Next, the operation of the semiconductor device configured as described above will be described. The signal line is input from the signal pad 13 to the internal circuit 14 via the signal wiring layer 33, the power supply voltage VCC is applied to the power supply pad 12, and the ground pad 11 is connected to an external ground wiring by bonding. The power supply voltage is supplied from the power supply pad wiring layer 32 to the contact 24,
Power is supplied to power supply wiring layers 35, 36, 39, 42 having a multilayer wiring structure formed in the wiring region via the wirings 22, 26. On the other hand, the ground potential GND is applied from the ground pad wiring layer 31 to the ground wiring layers 34, 37, 38, 40, 41 of the multilayer wiring structure via the contacts 23, 22, 21 and the second potential.
From the ground wiring layer 41 through the contact 20
6 is applied to a P ⁺ region 18 on the surface of the substrate 6 to apply a ground (GND) potential to a P well 17 formed on the substrate 16. Also, a power supply and ground pad wiring layer 32,
Reference numeral 31 is connected to the internal circuit 14 and supplies the internal circuit 14 with a power supply potential and a ground potential, respectively. Further, although not shown, a wiring layer for connecting the internal circuit 14 to the power supply wiring layer 35 and the ground wiring layer 34 is formed in a region other than the regions where the power supply and ground pad wiring layers 32 and 31 are formed. And internal circuit 1
4 may be supplied with a power supply potential and a ground potential, respectively.

In this embodiment, a multilayer wiring structure is formed in the wiring area around the chip. In this multilayer wiring structure, the ground pad wiring layer 31 on the insulating film 19 is formed in the insulating film 19. And the uppermost power supply wiring layers 35 and 36 in parallel with an insulating film therebetween. In the insulating film 19, the third power supply wiring layer 39 is formed.
And the ground wiring layer 41 of the second layer are opposed to each other in parallel with an insulating film interposed therebetween, and the ground wiring layer 41 of the second layer and the power supply wiring layer 42 of the first layer are between them. They are arranged to face each other in parallel with the insulating film interposed therebetween. Therefore, the internal circuit 14
A bypass capacitor is interposed between the external power supply pad 12 and the grounding pad 11, and power supply noise and ground noise are eliminated in this multilayer wiring structure.

In this case, a signal wiring layer 33 is formed on the insulating film 19 in addition to the power supply pad wiring layer 32 and the ground pad wiring layer 31, and the signal wiring layer 33 is formed.
It is conceivable that parasitic capacitance may be added between the power supply wiring layers 35 and 36 and the ground wiring layers 34 and 37 in the fourth layer below the power supply wiring layers 35 and 36. And 36 are not wide wiring layers extending over one surface, but have a gap 30 between them, and the uppermost power supply wiring layers 35 and 36 have a narrower overall width. Therefore, the signal wiring layer 33 and the uppermost (fourth) power supply wiring layer 3
Parasitic capacitance between the first and second electrodes 5 and 36 is small. Also, the ground wiring layers 34, 3 arranged on both sides of the power supply wiring layers 35, 36
7 also has a small width, so that adding unnecessary parasitic capacitance to the signal wiring layer 33 is suppressed.

On the other hand, since the third power supply wiring layer 39 having a large width is formed below the fourth power supply wiring layers 35 and 36, the third power supply wiring layer 39 is located between the third power supply wiring layer 39 and the lower second power supply wiring layer 41. Constitutes a bypass capacitor having a sufficiently large capacitance value. Therefore, power / ground noise can be sufficiently removed. The third power supply wiring layer 39 and the signal line wiring layer 3
3 is much smaller than that between the third layer and the fourth layer.

In this embodiment, the fourth layer of the uppermost layer
Power supply wiring layers 35 and 36 and the fourth
Between the first and second ground wiring layers 34 and 37,
A bypass capacitor is formed between the two. For example, in the present embodiment, the thickness of the first polysilicon wiring layer is 0.1 μm, and the insulating film formed between the first polysilicon wiring layer and the substrate on the substrate is as thin as 6 nm. It is. The distance between the surface of the polysilicon wiring layer and the lower surface of the second metal wiring layer (the lowermost layer of the metal wiring) is 0.1 mm.
78 μm, the distance between the second wiring layer and the third metal wiring layer (the thickness of the insulating film) is 0.8 μm, and the third wiring layer is
The distance (the thickness of the insulating film) between the first metal wiring layer (the uppermost metal wiring layer in the insulating film) and the distance between the fourth wiring layer and the pad wiring layer (the insulating film) is 0.8 μm. 0.8μ)
m, and the thickness of the second to fourth metal wiring layers is 0.6
1 μm, and the thickness of the pad wiring layer is 1.01 μm. Further, the distance between the fourth power wiring layer 35 (and 36) and the fourth ground wiring layer 34 (and 37) is 0.4 μm,
The width of these wiring layers 34 to 37 is 100 μm.
In the above dimensions, the capacitance value between the surface of the semiconductor substrate on which the polysilicon film is formed and the second metal wiring layer is 3.9εk, where εk is the relative dielectric constant, and the capacitance value between the metal wiring layers is Is 4.2εk. As described above, in the fourth uppermost layer, the distance between the power supply wiring layer 35 and the ground wiring layer 34 and the distance between the power supply wiring layer 36 and the ground wiring layer 37 are extremely short, and a bypass capacitor is provided between them. It is formed.

As a result, power / ground noise is further reduced. Normally, the lower the insulating film, the thinner the insulating film.
Therefore, between the P well 17 and the first power supply wiring layer 42, and between the lower first power supply wiring layer 42 and the second ground wiring layer 4.
1 and between the second ground wiring layer 41 and the third power supply wiring layer 39, the capacitor insulation film between the conductors has a small thickness, and the area of the conductors is small. Since it is large, it is easy to obtain an extremely large capacitance value. In contrast,
Since the capacitor formed by the conductor (the third layer and the fourth layer) disposed in the upper layer and the insulating film between them has a thickness of the insulating film 19 larger than that of the lower layer, even if a wiring layer having the same area is formed. , It is not possible to obtain a large capacitance value,
In this embodiment, the side conductor of the wiring layer is used, and the upper conductor, that is, the fourth power supply wiring layers 35 and 36 form a capacitor between the adjacent fourth conductive layers 34 and 37. Therefore, the distance between conductors, that is, the thickness of the insulating film is PR
Since it can be reduced to the limit determined by the process, an extremely large capacitance value can be obtained. Therefore, the multilayer wiring structure of this embodiment can constitute a high-efficiency and high-capacity bypass capacitor.

As described above, in this embodiment, since the uppermost power supply wiring layers 35 and 36 are narrow with the gap 30 therebetween, the signal wiring formed thereon is formed. Although the parasitic capacitance between the signal wiring layer 33 and the power supply wiring layers 35 and 36 can be sufficiently reduced.
As a result, some parasitic capacitance occurs. Although this causes a slight delay in the signal, in the present embodiment, the signal wiring layer 33 is formed by the power supply wiring layers 35 and 3.
6 and the region intersecting with the ground wiring layers 34 and 37,
It intersects vertically with these lower power supply wiring layers. For this reason,
In plan view, the signal wiring layer 33 and the power wiring layers 35 and 36
As long as the width of the signal wiring layer 33 is uniform, the area where the signal wiring layer 33 and the ground wiring layers 34 and 37
3 is constant. For this reason, each signal wiring layer 33
Is constant, and therefore, the amount of signal delay caused by the parasitic capacitance is constant.

On the other hand, in the conventional semiconductor device shown in FIG. 20, the signal wiring layer 7 connecting the signal pad 3 and the internal circuit 4 extends linearly, so that the input / output The angle at which the signal wiring layer 7 is inclined with respect to the chip edge differs depending on the position of the terminal and the position of the signal pad 3. Therefore, when the power supply wiring layer is arranged below the signal wiring layer 7 in the wiring region so as to extend parallel to the chip edge as in the present embodiment, the signal wiring layer 7 and the lower power supply wiring layer cross each other. The angle to be formed differs depending on the position of the signal pad 3, and even if the width of the signal wiring layer 7 is constant, the area where the signal wiring layer 7 and the lower power supply wiring layer overlap in a plan view is different. Then, the parasitic capacitance applied to the signal wiring layer 7 differs for each signal line, and the delay time differs for each signal line. On the other hand, in the present embodiment, as shown in FIG.
3 intersects vertically with the lower power supply wiring layers in the region where the power supply wiring layers 35 and 36 and the ground wiring layers 34 and 37 intersect, so that the signal wiring layer 33 and the power supply wiring layers 35 and The area where the wiring 36 and the ground wiring layers 34 and 37 overlap is constant for all the signal wiring layers 33.
Accordingly, the parasitic capacitance applied to each signal wiring layer 33 is constant, and the amount of signal delay resulting therefrom is constant.

Further, since the first and second power supply wiring layers are formed of a plurality of multi-layered wiring layers, the wiring resistance of the first and second power supply wiring layers can be reduced, and the impedance in the internal circuit 14 can be reduced with low impedance. A power supply (VCC) potential and a ground (GND) potential can be supplied to each circuit block.

In the above description, the first power supply is set to the power supply potential and the second power supply is set to the ground potential.
The power supply may be a power supply potential. In this case, the P ⁺ region 1
8 may be changed to an N ⁺ region, and the P well region 17 may be changed to an N well region.

Next, a second embodiment of the present invention will be described. FIG. 10 is a quarter of a chip showing the second embodiment of the present invention.
FIG. 11 is an enlarged plan view of a portion, and FIG. 11 is a sectional view taken along line AA of FIG. A ground pad 61, a power supply pad 62 and a signal pad 63 (63 a, 63 b) are arranged in the peripheral portion of the chip. In the uppermost wiring layer, the ground pad wiring layer 64 extends from these pads toward the internal circuit 14. , Power supply pad wiring layer 65 and signal pad wiring layer 66 (66
a, 66b) are formed so as to extend and are connected to respective terminals of the internal circuit. Under the pad wiring layers, a fourth-layer ground wiring layer 7 is interposed via an insulating film.
1, power supply wiring layer 72, ground wiring layer 73, and power supply wiring layer 7
4 are formed so as to surround the internal circuit 14 four times. The ground wiring layer 71 and the power supply wiring layer 72, and the ground wiring layer 73 and the power supply wiring layer 74 are respectively arranged unevenly on the internal circuit 14 side and the pads 61, 62, 63 side.
A relatively wide insulating film region (slit 30) exists between the two. A power supply wiring layer 75 is formed in a third layer below the fourth wiring layer, and a second power supply layer 75 is formed below the third layer.
In this layer, a ground wiring layer 76 is formed, and in a first layer below this second layer, a power supply wiring layer 77 is formed, and all of these wiring layers 75, 76, 77 are internally formed. The circuit 14 is arranged so as to surround the circuit 14.
Then, the ground pad wiring layer 64 and the ground wiring layers 71, 73
Are connected by a contact 67, and the power supply wiring layers 72 and 74 and the power supply pad wiring layer 65 are connected by a contact 68.
Connected by The power supply wiring layers 75 and 77 are connected to the power supply wiring layers 72 and 74 via contacts, and the ground wiring layer 76 is connected to the ground wiring layers 71 and 73 via contacts.

Also in the present embodiment, in the peripheral power supply wiring layer below the pad wiring layer, the power supply wiring layer is divided into two wiring layers 72 and 74. However, in the uppermost power supply wiring layer, in the first embodiment, GN
Although each wiring layer is arranged in the order of D-VCC-VCC-GND, in this embodiment, GND-VCC-GND-
These wiring layers are arranged in the order of VCC.

On the surface of the wiring region of the semiconductor substrate 59, a P ⁺ region 60 is formed on the entire surface. Furthermore,
In this embodiment, some signal pad wiring layers 66b
And the power supply pad wiring layer 65 is different from the first embodiment.
It is not orthogonal to the underlying wiring layers 71 to 74.

The intersection area between the signal pad wiring layer 66b and the power supply / ground wiring layers 71, 72 (or 73, 74) is set to be substantially the same as that of the signal pad wiring layer 66a. As a result, the parasitic capacitance at the intersection is substantially the same, and the signal delay at the intersection can be made substantially the same.

The gap 3 in the signal pad wiring layer 66b
By making the width on the zero region wider than that of the central part of the semiconductor chip (not shown), the wiring resistance can be reduced, and the difference in signal delay time between the edge part of the chip and the central part of the chip side can be reduced.

In the semiconductor device having such a structure, the power supply wiring layers 72 and 74 below the pad wiring layer are separated into two, as in the first embodiment, and the power supply wiring layer is entirely divided accordingly. Has become narrower. Therefore, the parasitic capacitance between the signal pad wiring layer 66 and the uppermost (fourth layer) power supply wiring layers 72 and 74 is small. The power supply wiring layers 72.
Since the widths of the ground wiring layers 71 and 73 disposed near the base 74 are also narrow, it is possible to prevent the unnecessary wiring from being added to the signal wiring layer 66.

The power supply wiring layers 72 and 74 and the ground pad wiring layer 64 face each other with an insulating film interposed therebetween, and have a wide power supply wiring layer 75, a ground wiring layer 76, and a power supply wiring layer 77. Are opposed to each other with an insulating film interposed therebetween, a capacitor is formed therebetween, and a bypass capacitor is interposed between the internal circuit 14 and the power supply pad 62 and the ground pad 61 for external drawing. In this multilayer wiring structure, power supply noise and ground noise are removed.

Next, a third embodiment of the present invention will be described. FIG. 12 is a quarter of a chip showing the second embodiment of the present invention.
FIG. 13 is a sectional view taken along line AA of FIG. 12, and FIG. 14 is a sectional view taken along line BB of FIG.
An N-well 82 is provided on the surface of a P-type semiconductor
4 is formed so as to surround the N well 82.
An N ⁺ region 83 for contact is formed therein. An insulating film 84 is formed on the surface of the semiconductor substrate 81, and the first ground wiring layer 1 is formed in the insulating film 84.
09, a second power supply wiring layer 106, and third power supply wiring layers 103 and 105 and a ground wiring layer 104 are formed. The power supply wiring layers 103 and 106
8 are connected to the power supply pad wiring layer 95 and the N ⁺ region 83 on the substrate surface.
7 are connected to each other by a contact 109, and these wiring layers are connected to a ground pad wiring layer 94 by a contact 110. The fourth layer also has a conductive layer. The fourth layer includes conductive layers 100 and 101 for relaying a contact 108 connected to the power pad wiring layer and a contact 110 connected to the ground pad wiring layer 94. This is a conductive layer 102 for relay.

On the insulating film 84, a ground pad 91, a power supply pad 92, and a signal pad 93 are formed in the peripheral portion of the chip, and the pads 91, 92, 93 are directed to the internal circuit 14 from these pads 91, 92, 93. Ground pad wiring layer 94,
A power supply pad wiring layer 95 and a signal pad wiring layer 96 are formed.

In this embodiment, the uppermost conductive layer is
It is a conductive layer for relaying a contact, not a wiring layer that goes around the internal circuit 14. In the third layer below this top layer,
Since the power supply wiring layers 103 and 105 are formed separately from each other, the parasitic capacitance between the signal pad wiring layer 96 and the power supply wiring layers 103 and 105 is extremely small also in this embodiment. Moreover, the power supply wiring layer 103,
Since the third layer 105 has a thick insulating film between itself and the signal pad wiring layer 96, the capacitance component attached to the signal pad wiring layer 96 is extremely small.

Next, the result of estimating the parasitic capacitance added to the signal line in the semiconductor device of the present embodiment and calculating the signal delay time will be described in comparison with a conventional semiconductor device.

First, in the first embodiment shown in FIGS. 1 to 9, the sheet resistance of the signal wiring layer 33 is set to 75 mΩ / □. At this time, since the wiring resistance R is proportional to the length (L) of the wiring and inversely proportional to the width (W), R = 75 (mΩ) ×
L / W. Then, the signal wiring layer 33
The capacitance per unit area between the uppermost and first and second power supply wiring layers 34 to 37 is 120 aF / μm ² . At this time, since the wiring capacitance C is proportional to the product (area) of the length (L) and the width (W) of the wiring, C = 120 (aF / μ).
m ² ) × L × W. In the above formula, a is 1 × 10 ^- means ^18. Further, the capacitance per unit area between the signal wiring layer 33 and the power supply wiring layer 39 is set to 30 aF / μm. At this time, the wiring capacitance C is
Since it is proportional to the product (area) of the length (L) and the width (W) of the wiring, it can be expressed as C = 30 (aF / μm ² ) × L × W. The delay time t due to the signal wiring layer 33 is generally represented by t = (wiring resistance R) × (wiring capacitance C).

First, a difference in signal delay time applied to the signal wiring layer 33 is calculated depending on the presence or absence of the gap 30.

(Case 1) A gap 3 is formed in the uppermost power supply wiring layer.
As shown in FIG. 15, the width of the fourth power supply wiring layer 35 and the ground wiring layer 34 is increased to 700 μm (1400 μm in two rows) as shown in FIG. Is 0.4 μm, the delay time t1 is represented by the following equation 1.

[0067]

T1 = (75 mΩ × 1400/100) × (120 aF / μm ² × 1400 × 100) = 1.05Ω × 16.8 pF = 17.6 ps (Case 2) A gap 30 is formed in the uppermost power supply wiring layer. In some cases, as shown in FIG. 16, the signal wiring 3 orthogonal to the power supply wiring layer
3, the wiring length L is 1400 μm, and the wiring width W is 100 μm. Power supply wiring layers 35 and 36 and ground wiring layers 34 and 37
Is 50 μm, and the gap 30 between the power supply wiring layers 35 and 36 is
Is 1200 μm. In this case, the delay time t2
Is represented by Equation 2 below.

[0068]

T2 = (75 mΩ × 1200/100) × (30 aF / μm ² × 1200 × 100) + 2 × (75 mΩ × 100/100) × (120 aF / μm ² × 100 × 100) = 0.9Ω × 3.6 pF + 2 × 75 mΩ × 1.2 pF = 3.24 ps + 0.18 ps = 3.42 ps As described above, the case compared to the conventional example shown in Case 1 (in which the entire surface under the signal wiring is covered with the power / ground wiring layer) In the case of the present embodiment shown in FIG. 2, by providing the gap 30 in the uppermost power / ground wiring layer, the delay time in the signal wiring portion can be reduced to 1/5.

Next, the effect of making the intersecting areas uniform will be described.

(Case 3) In the case where the signal wiring crosses obliquely in the entire range as in the conventional case. As shown in FIG. 17, the width of each of the power supply wiring layers 35 and 36 and the ground wiring layers 34 and 37 is 200 μm, The distance between the wiring layers 35 and 36 is 600 μm. The crossing angle between the power supply wiring layer 35 and the signal wiring 33a is 45 degrees.

The delay time t3 in this case is expressed by the following equation (3).

[0072]

T3 = (delay in gap 30 region) + (delay in power supply wiring 35 to 37 region) = (75 mΩ × 600√2 / 100) × (30 aF / μm ² × 600 × ² × 100) + 2 × ( 75 mΩ × 400√2 / 100) × (120 aF / μm ² × 400√2 × 100) = 0.64 Ω × 2.55 pF + 2 × 0.42 Ω × 6.79 pF = 1.62 ps + 5.76 ps = 7.38 ps (Case 4) 18) In the case where the signal wiring layer 33 is orthogonal to the power supply wiring layer and the other is an oblique signal wiring, as shown in FIG.
When the signal wiring layer 33 is orthogonal to the power supply wiring layer,
The delay time t4 is expressed by the following equation (4).

[0073]

T4 = (75 mΩ × 600√2 / 100) × (30 aF / μm ² × 600√2 × 100) + 2 × (75 mΩ × 400/100) × (120 aF / μm ² × 400 × 100) = 0.64 Ω × 2.54 pF + 2 × 0.30 Ω × 2.88 pF = 1.62 ps + 2.88 ps = 4.50 ps (Case 5) Delay time of wiring in central portion As shown in FIG. 19, delay time of wiring in central portion Is represented by the following Equation 5.

[0074]

T5 = (75 mΩ × 600/100) × (30 aF / μm ² × 600 × 100) + 2 × (75 mΩ × 400/100) × (120 aF / μm ² × 400 × 100) = 0.45Ω × 1.80 pF + 2 × 0.30Ω × 4.80 pF = 0.81 ps + 2.88 ps = 3.69 ps As described above, the delay time t5 of the signal wiring in the central part shown in Case 5 and the corner time of the corner part shown in Case 3 (conventional) While the difference t53 from the delay time is 32.9 ps, case 4
The difference t54 from the delay time of the present invention can be reduced to 0.8 ps.

That is, by making the crossing area with the power supply wiring the same in the central part and the corner part, the difference in the delay time in the signal wiring can be greatly reduced. In particular, this effect becomes more remarkable as the cross area with the power supply wiring is larger. Such an effect becomes possible for the first time because the gap 30 is provided between the power supply wirings.

In the above embodiment, the insulating film exists as the gap 30 between the power supply wiring layers 35 and 36. However, if the conductor layer is not connected to the power supply wiring layers 35 and 36, the power supply wiring layer 35. , 36 may be present.

[0077]

As described above, according to the present invention,
The uppermost first power supply wiring layer of the multilayer wiring structure provided in the wiring area is divided into a plurality of parts, and an insulating film or the like occupies between them. And the parasitic capacitance between the signal wiring layer and the first power supply wiring layer is small. This makes it possible to reduce signal delay.

If a second power supply wiring layer is provided close to the same layer of the first power supply wiring layer, a bypass capacitor having a large capacitance value between both side surfaces can be formed.

Further, by forming the signal wiring layer to be perpendicular or inclined at a certain angle with respect to the first power supply wiring layer disposed thereunder, the parasitic capacitance given to the signal wiring layer is reduced. Can be made constant for each signal line.

Furthermore, since the intersection area between the signal wiring layer and the peripheral power supply wiring layer is substantially the same in the vicinity of the center of the chip side of the semiconductor device and in the periphery (corner portion), the delay time difference due to the pad position is reduced. It is possible to provide a semiconductor device which is high speed and has few malfunctions.

Furthermore, since the first and second power supply wiring layers are formed in multiple layers, the wiring resistance of the first and second power supply wiring layers can be reduced. Therefore, a power supply potential and a ground potential with low impedance can be supplied to each circuit block in the internal circuit, and a stable semiconductor device with less interference and noise between circuit blocks can be provided.

Furthermore, the peripheral power supply wiring can be manufactured in the same process as the process of forming the internal circuit without adding a new manufacturing process, so that the manufacturing cost does not increase.

[Brief description of the drawings]

FIG. 1 is a plan view showing a semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view taken along line AA of FIG.

FIG. 3 is a sectional view taken along line BB of FIG. 1;

FIG. 4 is a sectional view taken along line CC in FIG. 1;

FIG. 5 is a plan view showing the entire layer arrangement in each layer of the embodiment.

FIG. 6 is a partially enlarged view of FIG. 5 (c).

FIG. 7 is a partially enlarged view of FIG. 5 (d).

FIG. 8 is a partially enlarged view of FIG. 5 (e).

FIG. 9 is a partially enlarged view of FIG. 5 (f).

FIG. 10 is a plan view showing a second embodiment of the present invention.

11 is a sectional view taken along line AA of FIG.

FIG. 12 is a plan view showing a third embodiment of the present invention.

13 is a sectional view taken along line AA of FIG.

FIG. 14 is a sectional view taken along line BB of FIG. 12;

FIG. 15 is a diagram for estimating the parasitic capacitance of Case 1;

FIG. 16 is a diagram for estimating a parasitic capacitance of case 2;

FIG. 17 is a diagram for estimating the parasitic capacitance of Case 3;

FIG. 18 is a diagram for estimating the parasitic capacitance of Case 4;

FIG. 19 is a diagram for estimating the parasitic capacitance of Case 5;

FIG. 20 is a plan view showing a conventional semiconductor device.

[Explanation of symbols]

11, 61, 91: ground pad 12, 62, 92: power supply pad 13, 63 (63a, 63b), 93: signal pad 14: internal circuit 16: semiconductor substrate 19: insulating film 20, 21, 22, 23, 24, 25, 26, 67, 6
8, 108, 109, 110: contact 30: gap 31, 64, 94: ground pad wiring layer 32, 65, 95: power supply pad wiring layer 33, 66 (66a, 66b), 96: signal wiring layer 34 , 37, 38, 40, 41, 71, 73, 76, 1
04, 107: ground wiring layers 35, 36, 39, 42, 72, 74, 77, 103,
105, 106: power supply wiring layer 100, 101, 102: conductive layer

──────────────────────────────────────────────────続 き Continued on the front page (51) Int.Cl. ⁷ Identification code FI Theme coat ゛ (Reference) H01L 23/12 NB 27/04 ED F term (Reference) 5F033 HH04 HH08 KK01 KK04 KK08 VV04 VV05 VV07 XX24 XX27 5F038 AC05 AZ06 BE07 BE09 BH03 BH19 CA10 CD02 CD04 CD05 CD09 CD12 CD13 EZ10 5F064 DD42 DD44 EE08 EE10 EE23 EE33 EE36 EE42 EE43 EE44 EE46 EE47 EE52 EE53

Claims (16)

[Claims] 1. A first power supply pad, a second power supply pad, and a signal pad disposed in a peripheral portion of a chip, an internal circuit disposed in a central portion of the chip, and between each of the pads and the internal circuit. And a first power supply pad formed on the uppermost insulating film and connected to the first power supply pad and the second power supply pad, respectively. A pad wiring layer and a second power supply pad wiring layer; and a signal wiring layer formed on the uppermost insulating film and connecting the signal pad and the internal circuit. A first power supply wiring layer and a second power supply wiring layer connected to the first power supply pad wiring layer or the second power supply pad wiring layer via contacts, respectively, extend so as to surround the internal circuit. , The first in the top layer
A semiconductor device, wherein the power supply wiring layer is divided into a plurality of parts in a direction from the internal circuit toward a chip edge. 2. A first power supply pad, a second power supply pad, and a signal pad disposed in a peripheral portion of a chip, an internal circuit disposed in a central portion of the chip, and between each of the pads and the internal circuit. And a first power supply pad formed on the uppermost insulating film and connected to the first power supply pad and the second power supply pad, respectively. A pad wiring layer and a second power supply pad wiring layer; and a signal wiring layer formed on the uppermost insulating film and connecting the signal pad and the internal circuit. A first power supply wiring layer and a second power supply wiring layer connected to the first power supply pad wiring layer or the second power supply pad wiring layer via contacts, and extending so as to surround the internal circuit; The uppermost first power supply wiring layer is A semiconductor device which is divided into a plurality of parts in a direction from an internal circuit to a chip edge, and wherein no conductor layer connected to the first power supply wiring layer exists between each first power supply wiring layer. 3. The space between the first and second power supply wiring layers is smaller than the space between the first and second power supply wiring layers immediately below the first and second power supply wiring layers. Semiconductor device. 4. The signal wiring layer according to claim 1, wherein the signal wiring layer has a first shape in a plan view.
4. The semiconductor device according to claim 1, wherein a portion crossing the power supply wiring layer is orthogonal to the first power supply wiring layer. 5. 5. The signal wiring layer, wherein a portion crossing the first power supply wiring layer in a plan view is inclined at the same angle with respect to the first power supply wiring layer. The semiconductor device according to claim 1, wherein: 6. The signal wiring layer according to claim 1, wherein the signal wiring layer has a first shape in a plan view.
4. A power supply wiring layer and a second power supply wiring layer, wherein a portion intersecting the first power supply wiring layer and the second power supply wiring layer is orthogonal to the first power supply wiring layer and the second power supply wiring layer. 3. The semiconductor device according to claim 1. 7. Each of the signal wiring layers has a portion which intersects the first power wiring layer and the second power wiring layer in plan view with the first power wiring layer and the second power wiring layer. The semiconductor device according to claim 1, wherein the semiconductor device is inclined at the same angle with respect to the semiconductor device. 8. In the wiring region, a second power supply wiring layer extending in parallel with the first power supply wiring layer in the uppermost layer is formed, and the first power supply wiring layer and the second power supply wiring layer are formed in parallel. 2
The semiconductor device according to any one of claims 1 to 7, wherein a capacitor is constituted by the power supply wiring layer. 9. A first power supply pad, a second power supply pad, and a signal pad disposed in a peripheral portion of the chip, an internal circuit disposed in a central portion of the chip, and between each of the pads and the internal circuit. And a first power supply pad formed on the uppermost insulating film and connected to the first power supply pad and the second power supply pad, respectively. A pad wiring layer and a second power supply pad wiring layer; and a signal wiring layer formed on the uppermost insulating film and connecting the signal pad and the internal circuit. A first wiring layer disposed on a first insulating film formed on a substrate, a second wiring layer disposed on a second insulating film formed on the first insulating film, A third wiring layer disposed on the third insulating film formed on the second insulating film. The first to third wiring layers extend so as to surround the internal circuit, and the third and second wiring layers are connected to the first power supply pad wiring layer via contacts. The first wiring layer is connected to the first power supply pad wiring layer via a contact, and constitutes a capacitor between the first wiring layer and the second wiring layer. The semiconductor device according to claim 1, wherein the third wiring layer is divided into a plurality of parts. 10. A wiring layer connected between the first wiring layer and the substrate via a contact to the first power supply pad wiring layer, wherein the other wiring layer is connected to the first wiring layer. 10. The semiconductor device according to claim 9, wherein a capacitor is formed between the first wiring layer and the first wiring layer. 11. The power supply line for supplying an internal circuit to the first power supply pad, and the second power supply pad is connected to ground. 13. The semiconductor device according to item 9. 12. A first power supply pad, a second power supply pad, and a signal pad disposed in a peripheral portion of a chip, an internal circuit disposed in a central portion of the chip, and between each of the pads and the internal circuit. And a first power supply pad formed on the uppermost insulating film and connected to the first power supply pad and the second power supply pad, respectively. A pad wiring layer and a second power supply pad wiring layer; and a signal wiring layer formed on the uppermost insulating film and connecting the signal pad and the internal circuit. A first power supply wiring layer and a second power supply wiring layer connected to the first power supply pad wiring layer or the second power supply pad wiring layer via contacts, respectively, extend so as to surround the internal circuit. , Each signal wiring layer is a plan view. Wherein a portion crossing the first power supply wiring layer is orthogonal to the first power supply wiring layer. 13. A first power supply pad, a second power supply pad, and a signal pad disposed in a peripheral portion of a chip, an internal circuit disposed in a central portion of the chip, and between each of the pads and the internal circuit. And a first power supply pad formed on the uppermost insulating film and connected to the first power supply pad and the second power supply pad, respectively. A pad wiring layer and a second power supply pad wiring layer; and a signal wiring layer formed on the uppermost insulating film and connecting the signal pad and the internal circuit. A first power supply wiring layer and a second power supply wiring layer connected to the first power supply pad wiring layer or the second power supply pad wiring layer via contacts, respectively, extend so as to surround the internal circuit. , Each signal wiring layer is a plan view. A semiconductor device, wherein a portion intersecting the first power supply wiring layer is inclined at the same angle with respect to the first power supply wiring layer. 14. A power supply wiring layer formed so as to extend around a chip peripheral portion, wherein the power supply wiring layer is formed in a plurality of wiring layers, and the area of the upper power supply wiring layer is reduced by the lower power supply wiring layer. A semiconductor device characterized in that it is narrower than a wiring layer for use. 15. The upper power supply wiring layer includes first and second power supply wiring layers formed in a circular shape, and the first and second power supply wiring layers are spaced apart from each other by a first or a second distance. 15. The semiconductor device according to claim 14, wherein the width of the two power supply wiring layers is wider. 16. The semiconductor device according to claim 14, wherein the upper power supply wiring layer is a relay wiring with a lower power supply wiring layer.