JP3408165B2 - Semiconductor integrated circuit device - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device, and more particularly to a highly efficient wiring pattern of a BIP-IC.

[0002]

2. Description of the Related Art Conventionally, the wiring of a BIP-IC has been mainly provided with a power supply line and a ground line in the first layer and mutual wiring in the second layer.

For example, Japanese Patent Application Laid-Open No. 2-3952 has an example. This is a region between the power supply line and the ground line, the element arrangement region is formed in a rectangular shape,
This is the so-called building block method. In this publication, all the building blocks have the same size.

In FIG. 10, the building blocks are different in size, and the electronic circuit blocks A to
I is incorporated and an IC circuit is realized as a whole. The length of each block is unified by the length of d,
The sides are of substantially different lengths in which one electronic circuit block can be placed.

A pair of power supply lines (power supply lines 10, 11, 12 and ground line 13,
14, 15) supplies power to each electronic circuit block.

Here, each electronic circuit block (building block) is indicated by a dotted line, and is indicated by A to I from the top.

The connection between the semiconductor elements in each building block is realized by the wiring of the first layer. Here, the wiring 16 in the X axis (left and right with respect to the paper surface) and the wiring 17 in the Y axis (vertical direction with respect to the paper surface) are combined and realized. In the drawing, what is indicated by the alternate long and short dash line is the wiring formed in the first layer, and the portion indicated by the cross is the portion in contact with the semiconductor element.

The wiring between the blocks is mainly realized by the second layer wiring. Here, it is indicated by a two-dot chain line. For example, the electrical connection between the block D and the block G is realized by the wiring 18, and the connection between the block E and the block H is
It is realized by the second layer wiring 19 and the first layer wirings 16 and 17. These are the power line 12 and the ground line 1
This is because 4 is extended as the wiring of the first layer and can be configured only in the second layer.

Further, the power supply line 11 and the ground line 13
There is also a case in which the space between and is slightly widened and this is utilized as a wiring-dedicated area. This extends from above the ground line 13 to the wiring-dedicated area in the second layer wiring, and in the wiring-dedicated area, it extends only in the X-axis direction in the first layer wiring, and Since it passes above, it is again extended to the block D, for example, under the power supply line 11 by the second layer wiring.

Further, the ground lines 13, 14 and 15 are
The semiconductor substrate is in contact with the isolation region and is connected to the semiconductor substrate through the isolation region (hereinafter referred to as ISO). The semiconductor substrate is connected to, for example, an island that constitutes a lead frame and is grounded to the GND potential. The ISO is
It penetrates the epitaxial layer laminated on the semiconductor substrate, and is of the same conductivity type as the semiconductor substrate. Then, each semiconductor element is formed on the island surrounded by the ISO and is PN-separated. The ISO also extends as a contact in the lower layer of the ground line, and faces the opening of the insulating film. This is a black-painted area in FIG. Most of them are not spot-shaped because they fix the ground line to GND potential.
A long contact is formed in a strip shape. ISO by design
When the arrangement is not possible, the contact holes may be divided into some like the ground lines 14 and 15, but the contact holes are still strip-shaped, and the spot-shaped contacts are rare.

[0011]

As described above, the ground lines 13 and 14 extending from the ground pad,
15 generates a voltage fluctuation due to its own impedance. Therefore, for example, as shown by a black filled area, the ground wiring is in contact with a strip-shaped contact having a width of several μm to 10 μm and a length of several hundred μm to 1000 μm. Hereinafter referred to as full-face contact. However, with this full-face contact, since the impedance is still high and the whole-face contact is performed in the form of a strip having an extremely long length, it is difficult to arrange another pattern, and there is a problem that the packaging density cannot be improved.

[0012]

The present invention has been made in view of the above-mentioned problems, and is formed on a first layer wiring electrically connected to a semiconductor element and a second insulating film covering the first wiring layer. It has a formed second layer wiring and a third layer wiring formed on a third insulating film covering the second wiring layer, and the third layer wiring is unified in one direction. A power supply line and a ground line are provided, and an isolation region provided in a region adjacent to the ground wiring is provided with a contact row so as to expose the isolation region at a plurality of locations. The first-layer wiring that is in contact with and extends below the ground line and the first-layer wiring below the ground line are electrically connected, and extend along the ground line. The ground line at the end Solves by forming in the second layer of wiring which contacts with.

Secondly, the first layer wiring electrically connected to the semiconductor element, the second layer wiring formed on the second insulating film covering the first wiring layer, and the second wiring layer. A third layer wiring formed on a third insulating film that covers the third wiring layer, the third layer wiring is provided with a power line and a ground line unified in one direction, and the third layer wiring is provided in a lower layer of the ground wiring. A contact row that exposes the separation area at a plurality of locations is provided in the separated area, and the contacts of the contact row extend from one end contacting the separation area to the other end along the lower layer of the ground line. First layer wiring,
The second layer wiring is in electrical contact with the other end of the first layer wiring and extends along the ground line, and the second layer wiring is in contact with the ground line at the extended other end. It is a solution.

Thirdly, the resistance value generated in the semiconductor substrate from the ground wiring when contacting the entire isolation region occupying from one end to the other end of the contact row with the ground wiring is equal to or lower than the resistance value generated in the semiconductor substrate. This is solved by adjusting the pitch of the contact rows.

Fourthly, the problem is solved by providing a semiconductor element or a wiring in the semiconductor layer, the first insulating film or the second insulating film corresponding to the lower layer of the ground line between the contact columns.

Fifth, the contact size is 10 μm.
The length from one end to the other end of the contact row is several hundred μm to 1,000 μm, and the problem can be solved by setting the contact row to a pitch as large as possible to be substantially equal to the resistance value. Is.

First, by providing a ground line in the third wiring layer, semiconductor elements and wiring can be arranged below the ground line. Moreover, due to the semiconductor element surrounded by the isolation region, the isolation region and the ground line can be connected even when the isolation region cannot be arranged in the lower layer of the ground line. Furthermore, the positions of the contact holes for the isolation region and the first layer wiring, the contact holes for the first layer wiring and the second layer wiring, and the contact holes for the second layer wiring and the third layer wiring are displaced. Therefore, it is possible to prevent contact failure due to the influence of unevenness generated in each contact hole.

As can be seen from FIG. 6, when the contact pitch is set to 80 μm or less, a portion smaller than the contact resistance formed by the strip-shaped contacts occurs. Therefore, the contact formed on the ground line is
Even if a long strip-shaped contact shape as shown in the upper two lines in FIG. 5 is not formed, a contact resistance equal to or lower than the conventional value can be realized with a certain contact pitch as shown in the lower two lines. Moreover, between the contacts,
Since it can be used as a wiring formation region, the mounting density of elements or wiring can be improved as compared with the conventional structure. In other words, the conventional IC can be made smaller.

In a structure in which the contact size is 10 μm or less and the length from one end to the other end of the contact row is several hundreds μm to 1,000 μm, the contact row has a resistance value substantially equal to that of the entire surface contact. There are equal pitches. That is, as shown in FIG. 6, G with a contact interval of about 50 μm pitch or less is equal to or less than that of the substantially full surface contact.
An ND resistance value can be realized. Therefore, by setting the pitch as large as possible within this range, further elements can be arranged between the contacts.

[0020]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described below. The invention particularly relates to BIP-ICs.

Now, the first embodiment will be described with reference to FIG. In the figure, a semiconductor IC (semiconductor chip) 20 is shown, and bonding pads are formed on the periphery. A substantially rectangular region (rectangular region shown by the second dotted line from the outside) 24 excluding the regions where the bonding pads 21 to 23 are formed was used as a device formation region. However, a protective diode or the like may be formed under the bonding pad.

The formation region 24 of this element includes blocks A to
Divided into G. Generally, an IC circuit is divided into some electronic circuit blocks, and the electronic circuit blocks are formed in each of the blocks A to G. That is, here, one semiconductor IC circuit is composed of seven circuit blocks. The circuit book includes an AM circuit, a multiplex circuit, an FM-IF circuit, a noise canceller circuit, and the like. This circuit block is for a radio, and will be configured by another circuit block for a television or a video, for example.

Explaining the cross section of the IC, first, there is a P-type semiconductor substrate, and at least one N-type epitaxial layer is laminated on this substrate. This epitaxial layer is usually one layer, but in an optical IC, for example,
There is a stack of two or three layers and an epitaxial layer.
Further, there is an ISO that reaches the semiconductor substrate from the surface of this epitaxial layer, and each semiconductor element is built in an island surrounded by this ISO. Examples of this semiconductor element include a transistor, a diode, a capacitor, a diffusion resistor, a diode and the like. Further, in the island, a buried layer is formed between the epitaxial layer and the semiconductor substrate. For example, the buried layer where the NPN type transistor is formed is N + type,
The purpose is to reduce collector resistance.

That is, in each of the blocks A to G surrounded by the dotted line, semiconductor elements forming each circuit block are formed.

A first insulating film is formed on the epitaxial layer, and a first wiring layer is formed on the insulating film. Furthermore, a second insulating layer is covered thereover, a second wiring layer is formed, and a third insulating layer is further formed thereon, and a third insulating layer is further formed. Wiring layer is formed. Here, the insulating film and the insulating layer are
The silicon oxide film, the Si3N4 film, the PSG film, the NSG film or the TEOS film may be used alone or in combination to form a plurality of layers. The manufacturing method is spin-on, C
It is formed by VD, low pressure CVD, plasma CVD or the like. Of course, each of them has a contact formed to realize a predetermined circuit.

Further, a passivation film is provided on the entire surface and is mounted on, for example, a lead frame, the leads and the bonding pads are connected by thin metal wires, and resin sealing is performed to complete the process.

The feature of the present invention is that the ground lines 25-2
7 is formed in the third layer. Ground pad 2
Since 3 is directly connected to the lead via a thin metal wire, it is stable as a GND potential. However, the GND potential becomes more unstable as it goes to the tips of the ground lines 25 to 27. However, if this is not a problem, it is not necessary to form a long band like the contact shown in FIG. For example, if no contact is provided or the ground line 2
If some contacts 28 to 30 are provided somewhere 5 to 27 and no other contacts are formed, the lower layer of the ground line other than the formation region of the contacts 28 to 30 is used as a formation region of elements and wirings. it can. See FIG. 7 for details. The interconnection of the elements in each block is
Although illustrated as an example in the block F, it is realized by making heavy use of the X-axis and Y-axis first layer wirings 31, 32. Moreover, a cross indicates a contact. Further, the connection between the blocks is realized by, for example, the wiring 33 of the first layer and the wiring 34 of the second layer extending from the block A to the block F.

Next, before describing the second embodiment with reference to FIG. 2, the second point of the present invention will be described below with reference to FIGS. 5 and 6.

Reference numerals 110, 111, 112 and 11 in FIG.
The portion indicated by 3 is an isolation region formed in the semiconductor layer. In addition, the areas 114, 115, and 11 filled in black
Reference numerals 6, 117 denote contact holes formed by opening an insulating film, and ground wirings 118, 119, 120, 12
1 is electrically connected through the contact hole. Here, in order to simplify the drawing, the ground wiring has the same size as the isolation region, but the isolation region may be formed larger than the ground wiring.

The upper two lines in FIG. 5 have a width (vertical length) of 8 μm.
(Or 4 μm) and contact hole 1 with a length of 600 μm
14, 115. Further, the contact holes 114, 115
Leave a margin of about 5 μm around the
18, 119 have a width of 18 μm (or 14 μm) and a length of 610 μm. Further, the sizes of the isolation regions 110 and 111 therebelow are substantially the same.

On the other hand, the bottom two are contact holes 116, 1
17 are formed in an island shape and have a length and width of 8 μm (or 4
μm), and the sizes of the ground wirings 120 and 121 and the isolation regions 112 and 113 are the same as the above two wirings. Moreover, although pads for measurement are provided on all the ground wirings, they are omitted in the drawing.

First, the upper two ground wirings 118 and 119.
The result of measurement by applying a resistance measurement probe to the pad connected to is the dotted line in FIG. That is, the measurement is performed between the first ground wiring 118 from the top, the P + type isolation region 110 therebelow, the P type semiconductor substrate under the isolation region, the second isolation region 111, and the ground wiring 119 thereabove. is there.

On the other hand, the solid line in FIG. 6 is measured by applying a probe to the measurement pads connected to the lower two ground wirings 120 and 121 in FIG. All measured contact sizes under the ground wiring are uniform. In the experiment, 8μm × 8μm (or 4μm × 4μ
m), which has a different contact pitch. These resistance values are tentatively defined as GND resistance values, and the vertical axis represents the pitch and the horizontal axis represents the pitch. For example, 4 μm
In the contact (shown as 4 μ □ in the figure), the GND resistance value decreases almost linearly as the pitch decreases, and intersects with the broken line (band-shaped full-face contact, resistance value shown as stripe resistance value in the figure). The slope has gradually decreased since the hit. Then, from about 60 μm pitch, it fell below the stripe resistance value.

As for the 8 μm contact (8 μ □ in the figure), the GND resistance value decreases almost linearly as the pitch becomes smaller, and the slope thereof gradually decreases from the point where it crosses the broken line. Then, from about 80 μm pitch, it became lower than the stripe resistance value.

For example, for an 8 μm contact, about 80
Up to the μm pitch, the GND resistance value is substantially the same or lower. Therefore, if it is desired to fix the GND voltage as much as possible on the circuit, it is necessary to make the pitch 80 μm finer. However, if accuracy is not required so much, it is effective to widen the pitch as much as possible for pattern flexibility. For example, the pitch can be expanded up to about 80 μm pitch in order to make it equal to the GND resistance value of the entire surface contact. That is, the ground wiring may be in contact with the isolation region via the contact, and the wiring and the circuit element can be arranged in the lower layer between the adjacent contact holes.

That is, in the ground wiring realized by the striped entire surface contact, the GND resistance value measured by the method realized by the upper two wires in FIG. 5 is Rg. Further, the GND resistance value measured by the method of realizing the bottom two lines of FIG. 5 is Rn (where n is the pitch) with the ground wiring realized in the same size as the width and length of this striped entire surface contact.
In the expression, by selecting the pitch n as large as possible from the pitch n showing the resistance value equal to or less than Rg, it is possible to realize the ground wiring which is not larger than the GND resistance value of the entire surface contact. Moreover, since the semiconductor elements are arranged through the contact holes, the semiconductor element can be arranged between the contacts and the flexibility of the pattern can be improved.

FIG. 2 is substantially the same as FIG. 1, except that the ground lines 25 to 27 have contact holes. Therefore, the same parts as those in FIG. 1 are denoted by the same reference numerals, and only different points will be described below. For example, the ground line 25 between the block A and the block F
In between, there is a portion in contact with the ISO formed thereunder via the contact holes 35 and 36.
That is, as shown in FIG. 10, since there is no strip-shaped long region that completely opens up to the isolation region, there is an advantage that elements and wirings 33 and 34 can extend here.

Specifically, it will be described with reference to FIG. That is, the ground line 40 of FIG. 7 will be described as the ground line formed between the contacts.

FIG. 7 is a diagram in which elements and wirings are formed under the ground line 40 of FIG. 2 (or FIG. 4), and reference numeral 4 is used.
Reference numerals 1 and 42 are diffusion resistances indicated by dotted lines. This diffusion resistance is a diffusion region formed of P type or N type in the above-mentioned epitaxial layer. A cross mark indicates a contact hole, and the wiring 47 of the first layer extending in the block formed below the ground line 40 and the diffusion resistance 41 are connected via the contact hole 43. The other end is connected to the first-layer wiring 48 formed below the ground line via the contact hole 44. Similarly, diffusion resistance 4
2 also through the contacts 45 and 46, the wiring 4 of the first layer
8 and 49 are connected. And the wiring 49 of the first layer
Is the contact hole 50 formed of the opening of the second insulating layer.
Is connected to the wiring 51 of the second layer via
Passes under the ground line 40 and is electrically connected to another block above or below the ground line 40.

Further, reference numeral 52 is a capacitor, reference numeral 53 is an N or P type lower electrode region, for example, a Si nitride film is formed as a dielectric thin film, on which a poly nitride film is formed. A first upper electrode made of Si and Al is formed. Reference numeral 55 is an area where the lower electrode of the N-type or P-type extends to this point and is exposed, and a wiring 56 of the first layer to be the lower electrode is formed here.

Further, reference numeral 57 is a vertical transistor in which first-layer electrodes 57 to 60 which are in contact with the collector, base and emitter regions are formed.

That is, conventionally, as shown in FIG. 10, since the contact was formed in a strip shape, it was not possible to form a wiring or an element under the ground line. However, as shown in FIG. 7, since the ground line 4 is formed in the third layer, a semiconductor element can be formed in this lower layer. That is, even if the contact of the semiconductor element is arranged below the ground line, the wirings of the first and second layers can extend below the ground line, so that the semiconductor element can be positively formed under the ground line. It is possible to improve the packaging density. It also has the advantage that the chip size can be reduced by improving the packaging density.

The third embodiment will be described with reference to FIG. This semiconductor IC 70 has the same structure as the block shown in FIG.
The length of the vertical axis is unified to d and the horizontal axis is set to an arbitrary size, which is formed between the power supply line and the ground line. (If anything, it can be said that the power supply line and the ground line are arranged near the upper and lower sides of the block.) A bonding pad is formed around the semiconductor IC (semiconductor chip) 70. A substantially rectangular area (rectangular area indicated by a dotted line) 74 excluding the area where the bonding pads 71 to 73 are formed is used as an element formation area. However, a protective diode or the like may be formed under the bonding pad.

The formation region 74 of this element is in blocks A to
Divided into I. Similar to the first embodiment, the circuit block constitutes an IC circuit, and here, nine electronic circuit blocks constitute one semiconductor IC circuit.

Power lines 75 to 77, ground line 7
Since 8 to 80 are formed in the third wiring layer, semiconductor elements and wirings can be formed in this lower layer as described with reference to FIG. 7, and the flexibility of pattern arrangement is improved.

Further, here, the directions of the first layer wiring, the second layer wiring and the third layer wiring are defined.

That is, as shown in the blocks A and D, the interconnections in each block are realized by the X-axis first layer wiring 81 and the Y-axis direction first layer wiring 82. The wiring 81 is an inter-element connection, and is the wiring 82 of the block A.
Indicates the connection between the element and the ground line 78.

Subsequently, the wirings of the second layer are all unified in the Y-axis direction. The wiring 83 of the second layer connects between the block A and the block D, and the wiring 84 connects between the block B and the block H. Mainly the second layer wiring
It is formed in the Y-axis direction to realize wiring between blocks.

Further, the wiring of the third layer is unified on the X axis. That is, the power supply lines 75 to 77 extending from the VCC pad 72 and the ground lines 78 to 80 extending from the GND pad 73 are all unified in the X-axis direction. Further, between the power supply line and the ground line, the connection between the blocks in the horizontal direction is also realized, as shown by the black line. For example, wiring 85
Connects the block B and the block C, and the left end is connected to the semiconductor element after being in contact with the wiring of the first layer. The wiring 86 of the third layer connects the block C and the block G. The wiring from the block C to the wiring 86 is the wiring of the second layer, and the wiring from the left end of the wiring 86 to the block G is the wiring of the second layer. Has been realized in.

In this structure, the wiring is shown to be very sparse, but in reality it is very dense. Therefore, by unifying the second-layer wiring in the Y-axis direction and the third-layer wiring in the X-axis direction, the second-layer wirings do not intersect with each other and the third-layer wiring does not intersect.

Blocks (for example, blocks C and G) arranged in a relationship intersecting with the ground line and the power supply line.
Can be easily connected by utilizing the second layer wiring and the third layer wiring.

FIG. 4 is substantially the same as FIG. 3, except that the ground lines 78 to 80 are provided with contact holes. Further, the same parts as those in FIG. 3 are denoted by the same reference numerals, and the description thereof will be omitted.

Further, since the structure of FIG. 7 described above can be adopted below the ground line between the contacts, the flexibility of pattern arrangement can be improved and the mounting density can be improved.

Then, the ground line and I are shown in FIGS.
Another contact method of SO will be described.

2, FIG. 4 and FIG. 10 are in direct contact with the ISO directly below from the ground line, but FIG. 8 shows I located outside the ground line 200.
It makes contact with SO. After all, the dashed line is
The wiring is the first layer, and the chain double-dashed line is the second layer wiring.
Further, FIG. 8B is a sectional view taken along the line AA, and FIG.
[FIG. 7] is a cross-sectional view taken along the line BB.

The contact holes 201 and 202 are portions where ISO is exposed from the insulating film of the first layer.
O may extend from the contact holes 201 to 202 left and right or may be arranged in an island shape. That is, the upper end of the first-layer wiring 203 is connected to the ISO through the contact hole 201, and the lower end is connected to the second-layer wiring 203 through the contact hole 204 of the first-layer wiring 203 exposed from the second insulating layer. It is connected to the wiring 205. The second-layer wiring 205 is connected to the ground line 2 through the second-layer wiring contact 206 exposed from the third- layer insulating layer.
I am in contact with 00.

If the position of contact 206 is above contact 204, contact 201 (or 2
02) is located below the contact 204, the x in the figure
Since there is a recessed portion indicated by a mark, it has a drawback that it is difficult to form a contact hole.
Since the positions of (or 201), 204, and 206 are all deviated, there is an advantage that the contact hole can be opened without being affected by the recess.

Further, as described above, even if the ISO cannot be arranged immediately below the ground line due to the arrangement of the semiconductor elements surrounded by the ISO, the contact can be made only by disposing the ISO in the vicinity of the ground line. It will be possible.

FIG. 9 is for making contact with the ISO located inside the ground line 300. Again, the alternate long and short dash line is the wiring of the first layer, and the alternate long and two short dashes line is the wiring of the second layer. Further, FIG. 8B is a sectional view taken along the line AA of FIG. The right end of the wiring 301 of the first layer is the contact hole 3
Contact hole 3 of the wiring 301 of the first layer, which is connected to ISO through 02 and is exposed at the left end from the insulating layer of the second layer.
It is connected to the wiring 304 of the second layer via 03. The second-layer wiring 304 is in contact with the ground line 300 via the contact 305 of the second-layer wiring exposed from the third insulating layer.

The position of the contact 302 is the contact 30.
5, the recessed portion 306 indicated by X is relaxed by the second insulating layer 307, so that it is possible to suppress the difficulty of forming the contact hole due to the presence of the recessed portion. it can.

[0061]

According to the present invention, first, by providing the ground line in the third wiring layer, the semiconductor element and the wiring can be arranged below the ground line. Moreover, due to the semiconductor element surrounded by the isolation region, the isolation region and the ground line can be connected even when the isolation region cannot be arranged in the lower layer of the ground line. Furthermore, the positions of the contact holes for the isolation region and the first layer wiring, the contact holes for the first layer wiring and the second layer wiring, and the contact holes for the second layer wiring and the third layer wiring are displaced. Therefore, it is possible to prevent contact failure due to the influence of unevenness generated in each contact hole.

As can be seen from FIG. 6, when the contact pitch is set to 80 μm or less, a portion smaller than the contact resistance formed by the strip-shaped contacts occurs. Therefore, the contact formed on the ground line is
Even if a long strip-shaped contact shape as shown in the upper two lines in FIG. 5 is not formed, a contact resistance equal to or lower than the conventional value can be realized with a certain contact pitch as shown in the lower two lines. Moreover, between the contacts,
Since it can be used as a wiring formation region, the mounting density of elements or wiring can be improved as compared with the conventional structure. In other words, the conventional IC can be made smaller.

In a structure in which the contact size is 10 μm or less, and the length from one end to the other end of the contact row is several hundred μm to 1,000 μm, the contact row has a resistance value substantially equal to that of the entire surface contact. There are equal pitches. That is, as shown in FIG. 6, G with a contact interval of about 50 μm pitch or less is equal to or less than that of the substantially full surface contact.
An ND resistance value can be realized. Therefore, by setting the pitch as large as possible within this range, further elements can be arranged between the contacts.

[Brief description of drawings]

FIG. 1 is a plan view of a semiconductor integrated circuit device according to a first embodiment of the present invention.

FIG. 2 is a diagram in which contact holes having a predetermined pitch are adopted in FIG.

FIG. 3 is a plan view of a semiconductor integrated circuit device according to a second embodiment of the present invention.

FIG. 4 is a diagram in which contact holes having a predetermined pitch are adopted in FIG.

FIG. 5 is a diagram illustrating a method for measuring the resistance values of a strip-shaped entire surface contact and contacts formed at a predetermined pitch.

FIG. 6 is a diagram illustrating the measurement results of FIG.

FIG. 7 is a diagram illustrating an element that can be arranged below a ground line.

FIG. 8 is a diagram illustrating a contact method with a ground line.

FIG. 9 is a diagram illustrating a method of contacting with a ground line.

FIG. 10 is a plan view illustrating a conventional semiconductor device.

─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Mitsuo Osawa 2-5-5 Keihan Hondori, Moriguchi City, Osaka Sanyo Electric Co., Ltd. (56) Reference JP-A-2-248049 (JP, A) JP Flat 8-125150 (JP, A) (58) Fields surveyed (Int.Cl. ⁷ , DB name) H01L 21/822 H01L 21/768 H01L 21/82 H01L 27/04

Claims (3)

(57) [Claims] 1. A semiconductor layer of opposite conductivity type laminated on a semiconductor substrate of one conductivity type, a separation region of one conductivity type reaching from the surface of the semiconductor layer to the semiconductor substrate, and an island surrounded by the separation region. A plurality of semiconductor elements formed on the semiconductor layer, a first insulating film formed on the surface of the semiconductor layer, and a first-layer wiring provided on the first insulating film and electrically connected to the semiconductor element And a second insulating film formed on the second insulating film covering the first wiring layer.
A layer wiring and a third wiring formed on a third insulating film covering the second wiring layer.
A power supply line and a ground line, which are unified in one direction, are provided in the third layer wiring, and the isolation region provided in a region adjacent to the ground wiring is the isolation region. The contact row is exposed at a plurality of positions, and each contact of the contact row is the first insulating film.
The first-layer wiring that is in contact with the isolation region through the contact hole and extends to the lower layer of the ground line, and the first-layer wiring that is under the ground line are electrically connected, and along the ground line. A second layer of wiring that extends and contacts the ground line at its extended end, and each contact is provided in a layer below the ground line.
The semiconductor layer and the first insulating film corresponding to the non-existing portion
Alternatively, the semiconductor element and the first insulating film are formed on the second insulating film.
A semiconductor integrated circuit device comprising layer wiring or the second layer wiring . 2. A semiconductor layer of opposite conductivity type stacked on a semiconductor substrate of one conductivity type, a separation region of one conductivity type reaching from the surface of the semiconductor layer to the semiconductor substrate, and an island surrounded by the separation region. A plurality of semiconductor elements formed on the semiconductor layer, a first insulating film formed on the surface of the semiconductor layer, and a first-layer wiring provided on the first insulating film and electrically connected to the semiconductor element And a second insulating film formed on the second insulating film covering the first wiring layer.
A layer wiring and a third wiring formed on a third insulating film covering the second wiring layer.
The third layer wiring is provided with a power line and a ground line that are unified in one direction, and the isolation region provided in a lower layer of the ground line has a plurality of isolation regions. in having a contact row to be exposed, each contact of the contact row, said first insulating film
A first-layer wiring extending from one end in contact with the isolation region along the lower layer of the ground line to the other end in the contact hole and the other end of the first-layer wiring, Extended along the ground line,
It is formed by a second layer wiring which contacts the ground line at the extended other end, and the respective contacts are provided under the ground line.
The semiconductor layer and the first insulating film corresponding to the non-existing portion
Alternatively, the semiconductor element and the first insulating film are formed on the second insulating film.
A semiconductor integrated circuit device comprising layer wiring or the second layer wiring . 3. The semiconductor substrate and the isolation region are electrically connected to each other.
The resistance value from the ground line connected to
When the area and the ground line are in continuous contact
Be equal to or less than the above resistance value
The pitch of the contact rows exposing the isolation region
3. The claim 1 or claim 2 characterized in that
Mounted semiconductor integrated circuit device.