JPH04111462A - Semiconductor device - Google Patents

Abstract

PURPOSE:To enhance an area efficiency and reduce a chip size by laying out a connection terminal of each conductor layer so that its connection position may be arranged at least on a pair of diagonal line in terms of a capacity device formed by clamping an insulation layer with two conductor layers and preventing their connection positions from being lapped. CONSTITUTION:Conductor layers 1 and 2 form a capacity device by clamping an insulation layer 3 as if it were a sandwich. The position at which each conductor layer is connected with a connection terminal is laid out on the conductor layer 1 as marked with 8-1 and 8-2, and on the conductor layer 2 as marked with 9-1 and 9-2. More specifically, two corners out of the four corners on the conductor layer are properly selected so that each connection point on the conductor layers 1 and 2 may not be lapped. The selection of any connection position with the connections terminals to use is properly determined by the structure of the capacity device. For example, it is possible to use such locations as marked with 8-1 or 9-1 or 8-2 and 9-1. The terminal of the capacity device is arranged based on these connection positions so that it may be used as a single device or as a plurality of devices connected in parallel or in series.

Description

[Detailed Description of the Invention] [Summary] Regarding a semiconductor device including a capacitive element with good area efficiency, when obtaining a large capacitance value using a plurality of capacitive elements with good area efficiency, the present invention provides a method for easily obtaining an accurate large capacitance value. The purpose of providing a semiconductor device is to provide a semiconductor device including a capacitive element formed between two layers of a first conductive layer and a second conductive layer with an insulating layer sandwiched between the first and second conductive layers of the capacitive element. The connection terminals of the conductive layer each have at least one connection position.
They are arranged diagonally across the set and configured so that they do not overlap vertically.

[Industrial application field]

The present invention relates to a semiconductor device including a capacitive element with high area efficiency.

A capacitive element obtained by insulating two conductive layers with an insulating layer has poor area efficiency when connected in parallel to obtain a large capacitance value. Therefore, it has been desired to develop a semiconductor device including a capacitive element that is easy to manufacture by reducing the wiring area and preventing the wiring from passing over the pattern.

[Conventional technology]

Capacitive elements obtained by semiconductor manufacturing technology are obtained by insulating two conductive layers (for example, polysilicon) with an insulating layer. FIG. 5 shows a cross-sectional view of such a capacitive element. In FIG. 5, 1.2 is a conductive layer made of, for example, polysilicon, 3 is an insulating layer, 4 and 5 are contact holes, and 6 is a covering layer. Conductive layer 1.2
Since the space between the conductive layer 1 and the conductive layer 1 is insulated by the insulating layer 3,
A capacitance value is obtained that is inversely proportional to the spacing between .degree. 2 and proportional to the facing area. When used as a capacitive element, a terminal is required, so the connection hole 4.5 in contact with the conductive layers 1 and 2 is
The upper portion of the covering layer 6 is connected to wiring that is in contact with other capacitive elements. The contact holes 4 and 5 are usually formed by penetrating the covering layer 6 and filling the holes with a conductive material. The conductive layer pattern of this capacitive element is usually square, but when contact holes are provided on both sides and the capacitance is increased in parallel to increase the capacitance, connecting lines are connected as shown in the top view of Figure 6. use In FIG. 6, the covering layer 6 of FIG. 5 is removed. 7-1.7
Reference numeral 2 denotes a connection line, which is formed as a wiring layer on the horizontal plane between the covering layer 6 and the path when the semiconductor device is manufactured.

FIG. 7 is a cross-sectional view showing another configuration of FIG. 5. 8th
The figure is a top view of FIG. 7, and the same reference numerals as in FIGS. 5 and 6 indicate the same parts. In FIG. 7, the lower conductive layer 2
In contrast, the upper conductive layer 1 has a small area. It has a feature that a wiring layer is provided above the conductive layer 1 and 2 patterns.

[Invention or problem to be solved]

According to the configuration shown in FIG. 5, a portion of the conductive layer pattern protrudes to the outside in order to provide a terminal, so that the proportion of the area utilized as a semiconductor device is reduced. In other words, it has the disadvantage of poor surface efficiency.

According to the configuration shown in FIG. 7, it passes directly over the wiring layer or covering layer between adjacent capacitive elements, passes between the capacitive elements, and then passes over the covering layer between the capacitive elements again. Because the wires pass through the wire, there are large steps and wire breaks easily.

FIG. 9 is a cross-sectional view of the capacitive element of FIG. 8, showing the vertical direction on a scale larger than the horizontal direction.

The wiring layer has a large step and is connected to the next capacitive element. Since the distance from the covering layer to the lower conductive layer via the upper conductive layer/insulating layer is short, the electric field at the terminal part of the upper conductive layer will pass through the pinhole and reach the lower conductive layer if there is a pinhole in the insulating layer. It has the disadvantage that it is easy to reach the target and cause a short circuit.

SUMMARY OF THE INVENTION An object of the present invention is to provide a semiconductor device which eliminates the above-mentioned drawbacks and allows a simple and accurate large capacitance value to be obtained when obtaining a large capacitance value using a plurality of area-efficient capacitor elements.

[Means to solve the problem]

FIG. 1 is a diagram showing the basic configuration of the present invention. In FIG. 1, 1 and 2 are conductive layers, 3 is an insulating layer, and 1, 2, and 3 are entirely manufactured using semiconductor manufacturing technology to form a capacitive element. 8
-1.8-2.9-1.9-2 indicates the connection position with the connection terminal of the capacitive element.

In a semiconductor device including a capacitive element formed between two layers of a first conductive layer 1 and a second conductive layer 2 with an insulating layer 3 sandwiched therebetween, the present invention has the following configuration. That is, the connection terminals of the first and second conductive layers of the capacitive element have their connection positions 8-1. and configured so that they do not overlap vertically.

[Effect]

As shown in FIG. 1, the conductive layer 1.2 sandwiches the insulating layer 3 to form a capacitive element.

The positions where each conductive layer connects to the connection terminal are a total of 1.8-2 marks on conductive layer 1 and 9-1, 9-2 marks on conductive layer 2.
They are located as indicated by the marks. That is, two of the four corners of the conductive layer are used as appropriate so that the connection positions on the conductive layer 1.2 do not overlap vertically. Which of the connection positions with the connection terminals to use can be used as appropriate depending on the configuration of the capacitive element. For example, two locations of 8-1° and 9-1 may be used, or 8-2.9-1 may be used. Terminals of the capacitive element are configured depending on these connection positions, and the capacitive element is connected and used as a single element, or a plurality of elements are connected in parallel or in series.

〔Example〕

FIG. 2 is a diagram showing the configuration of an embodiment of the present invention.

In FIG. 2, the same reference numerals as in FIG. 1 indicate the same components. The difference from FIG. 1 is that the conductive layer 1. Since the two corners of each conductive layer do not have connection positions with external terminals, the corners of each conductive layer are rounded off in a plane at the two corners of each conductive layer. Note that the use of predetermined connection positions is the same as in FIG. 1.

FIG. 3 is a plan view showing a configuration in which two capacitive elements having the configuration shown in FIG. 2 are connected as another embodiment of the present invention.

Figure 3A shows the case of parallel connection, in which the upper conductive layer and the lower conductive layer are arranged symmetrically with respect to the dashed dotted line, and the terminals are connected to each other and to each other by connection lines 11 and 12 as shown in the figure. ,
When viewed from the terminals 8-1 and 9-2, a capacitance value twice that of the individual layer is obtained.

FIG. 3B shows a case of series connection, in which the conductive layers of the respective elements are arranged horizontally, and the terminals 8-3 and 9-10 are connected by the connecting wire 13, and the terminals 8-1 and 9-10 are connected in series. 93, a capacitance value of 172 of the capacitance value of the individual element is obtained.

Next, FIG. 4 is a diagram showing an arrangement for obtaining various multiple values of individual elements as yet another embodiment of the present invention.

FIG. 4A shows a plan view, and FIG. 4B shows a cross-sectional view.

In FIG. 4B, 1.2 is a conductive layer of polysilicon, 3
is an insulating layer of SiO□, 4 and 5 are connection holes (contact holes), 6 and a covering layer of SiO□, 7-1.7-2- is Af
The connection line (wiring layer) is shown. As shown by broken lines in FIG. 4A, the capacitance I is made up of two unit elements having a capacitance value C connected in parallel, so the combined capacitance is 2C. Four capacitors (■) are connected in parallel to obtain 4C. Similarly, the capacity ■ is 6C,
The capacity ■ is 8C. When viewed from the two terminals below the letters Capacity I and Capacity ■, it shows that a predetermined capacitance value is obtained.

It is also possible to obtain 10C by further connecting capacitors (2) and (2) in parallel. The material of the conductive layers 1 and 2 is a diffusion layer or Af.
Layers can be used. It is clear that the materials of the wiring layers and insulating layers can also be changed to other materials.

〔Effect of the invention〕

In this way, according to the present invention, when connecting multiple capacitive elements, the position and length of the wiring layer used are reduced in relation to the conductive layer pattern, so area efficiency can be maintained high and chip size can be reduced. It is effective in reducing the size. L.S.
This can contribute to lowering costs when manufacturing as I. Furthermore, when the capacitor pattern is made point-symmetrically, even if a misalignment occurs in the mask alignment, the capacitance value is less affected, and variations in capacitance characteristics are reduced. Therefore, it can be easily applied when forming a circuit that requires a high relative capacitance ratio, such as a switched capacitor filter, and is extremely effective in terms of manufacturing.

FIG. 2 is a diagram showing the configuration of an embodiment of the invention, FIG. 3 is a diagram showing the configuration of another embodiment of the invention, and FIG. 4 is a diagram showing the configuration of still another embodiment of the invention. 5 is a diagram showing the configuration of a conventional semiconductor capacitive element, FIG. 6 is a diagram showing a configuration in which the elements of FIG. 5 are connected in parallel, FIG. 7 is a diagram showing another configuration of FIG. 5, The figure is a top view of FIG. 7, and FIG. 9 is a longitudinal sectional view of FIG. 8.

1.2-・Conductive layer 3-Insulating layer 8-1.8-2.9-1.9-2...Connection position with connection terminal Patent applicant Fujitsu Ltd. Representative Patent attorney Seiki Eika

[Brief explanation of drawings]

FIG. 1 is a diagram showing the principle configuration of the present invention, The reason behind the purchase of this book Y Ming No. figure Twl everyone 1 No. Ward cephalic arm) No. figure Figure 3 +) No. figure fW11tkilf+F No. figure

Claims (1)

[Claims] One or two first conductive layers (1) and second conductive layers (2)
In a semiconductor device including a capacitive element formed with an insulating layer (3) in between, connection terminals of the first and second conductive layers of the capacitive element are located at connection positions (8-1) (8-2). (9-1) (9-
2) are arranged on at least one set of diagonal lines, and do not overlap vertically. 2. A plurality of capacitor-forming conductive layers according to claim 1 are arranged close to each other such that connection positions of connection terminals of the first or second conductive layer are close to each other. semiconductor devices.