JPS6325716Y2 - - Google Patents
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- Publication number
- JPS6325716Y2 JPS6325716Y2 JP4183281U JP4183281U JPS6325716Y2 JP S6325716 Y2 JPS6325716 Y2 JP S6325716Y2 JP 4183281 U JP4183281 U JP 4183281U JP 4183281 U JP4183281 U JP 4183281U JP S6325716 Y2 JPS6325716 Y2 JP S6325716Y2
- Authority
- JP
- Japan
- Prior art keywords
- electrode
- electrodes
- dielectric ceramic
- ceramic layer
- length direction
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
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- 239000000919 ceramic Substances 0.000 claims description 34
- 239000003990 capacitor Substances 0.000 claims description 25
- 239000004020 conductor Substances 0.000 description 12
- 238000010586 diagram Methods 0.000 description 7
- 238000000605 extraction Methods 0.000 description 5
- 229910052573 porcelain Inorganic materials 0.000 description 2
- 244000126211 Hericium coralloides Species 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 230000003014 reinforcing effect Effects 0.000 description 1
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- Ceramic Capacitors (AREA)
- Fixed Capacitors And Capacitor Manufacturing Machines (AREA)
Description
【考案の詳細な説明】
本考案は、主として内部電極構造のチツプ状磁
器コンデンサに関する。DETAILED DESCRIPTION OF THE INVENTION The present invention mainly relates to a chip-shaped porcelain capacitor with an internal electrode structure.
従来の此種のコンデンサとしては、たとえば第
1図、第2図に示すような構造のものが提案され
ている。まず、第1図に示すものは、誘電体磁器
1の内部に、誘電体磁器層1Aを間に挾んで電極
2,3を埋設し、該電極2,3の互に相反する一
端を、誘電体磁器1の両側面に設けた端部電極
4,5に導通接続させた構造となつている。この
タイプのコンデンサは、電極2,3を補強層1
B1,1B2によつてサポートしてあるので、容量
層となる誘電体磁器層1Aの層厚を薄くして大容
量化を図りつつ、充分な機械的強度を確保するこ
とができる。 As a conventional capacitor of this type, one having a structure as shown in FIGS. 1 and 2, for example, has been proposed. First, in the device shown in FIG. 1, electrodes 2 and 3 are buried inside a dielectric ceramic 1 with a dielectric ceramic layer 1A in between, and opposite ends of the electrodes 2 and 3 are connected to the dielectric ceramic layer 1A. It has a structure in which it is electrically connected to end electrodes 4 and 5 provided on both sides of the body porcelain 1. This type of capacitor has electrodes 2 and 3 connected to a reinforcing layer 1.
Since it is supported by B 1 and 1B 2 , it is possible to reduce the layer thickness of the dielectric ceramic layer 1A serving as a capacitive layer and increase the capacity while ensuring sufficient mechanical strength.
次に第2図に示すものは、誘電体磁器1の内部
および必要ならばその表面に、より多層の電極
2,3を設けた積層形のコンデンサとなつてお
り、電極2−3間の誘電体磁器層1A1〜1A5に
より非常に大きな静電容量を取得できる。 Next, the capacitor shown in Fig. 2 is a multilayer capacitor in which more multilayer electrodes 2 and 3 are provided inside a dielectric ceramic 1 and, if necessary, on its surface. A very large capacitance can be obtained by the body ceramic layers 1A 1 to 1A 5 .
この種のコンデンサはプリント回路基板に実装
する場合、第3図に示すように、プリント回路基
板6上の導体パターン7,8に端部電極4,5を
半田付け固定して平面状に実装する。 When this type of capacitor is mounted on a printed circuit board, the end electrodes 4 and 5 are soldered and fixed to the conductor patterns 7 and 8 on the printed circuit board 6, as shown in FIG. .
ところが、電極2,3のパターンが、長さ方向
に非対称となつているため、コンデンサの下側を
他の導体パターン9が通る場合、この導体パター
ン9との間の浮遊容量が、コンデンサの取付け方
向によつて変化してしまうという欠点があつた。
すなわち、第3図に示すように、端部電極4を導
体パターン7に半田付けし、端部電極5を導体パ
ターン8に半田付けしたとき、端部電極4−導体
パターン9間に発生する浮遊容量C2と、端部電
極5−導体パターン9間に発生する浮遊容量C1
との間には、C1≪C2なる関係が成立するが、第
4図に示すように取付方向を逆にして端部電極4
を導体パターン8に半田付けし、端部電極5を導
体パターン7に半田付けした場合には、浮遊容量
C1,C2の関係がC1≫C2となり、明らかに方向性
が出てくるのである。 However, since the patterns of the electrodes 2 and 3 are asymmetrical in the length direction, when another conductor pattern 9 passes under the capacitor, the stray capacitance between the conductor pattern 9 and the capacitor is The problem was that it changed depending on the direction.
That is, as shown in FIG. 3, when the end electrode 4 is soldered to the conductor pattern 7 and the end electrode 5 is soldered to the conductor pattern 8, the floating air generated between the end electrode 4 and the conductor pattern 9 is Capacitance C 2 and stray capacitance C 1 generated between end electrode 5 and conductor pattern 9
However, as shown in Fig. 4, if the mounting direction is reversed , the end electrode 4
is soldered to the conductor pattern 8, and the end electrode 5 is soldered to the conductor pattern 7, the stray capacitance
The relationship between C 1 and C 2 is C 1 ≫ C 2 , and a directionality clearly emerges.
この浮遊容量の方向性をなくするため、第5図
に示すように、誘電体磁器1の内部の同一平面上
に、面積が同一で互に独立する電極10,11お
よびこの電極10,11に対して誘電体磁器層を
間に挾んで対向する電極12,13をそれぞれ埋
設し、電極10,11と電極12,13との間の
誘電体磁器層のほぼ中間部に、これらの電極10
〜13から独立した電極14を埋設すると共に、
電極10,12および電極11,13を端部電極
15,16にそれぞれ導通させたコンデンサが提
案されている。しかし、このコンデンサは、第6
図に示すように、コンデンサC3〜C6を直並列に
接続した等価回路となるため、容量値が高く取れ
ない等の欠点があつた。 In order to eliminate the directionality of this stray capacitance, as shown in FIG. On the other hand, opposing electrodes 12 and 13 are buried with a dielectric ceramic layer in between, and these electrodes 10 are buried approximately in the middle of the dielectric ceramic layer between the electrodes 10 and 11 and the electrodes 12 and 13.
While embedding an electrode 14 independent from ~13,
A capacitor has been proposed in which electrodes 10, 12 and electrodes 11, 13 are electrically connected to end electrodes 15, 16, respectively. However, this capacitor
As shown in the figure, since the equivalent circuit is formed by connecting capacitors C 3 to C 6 in series and parallel, it has drawbacks such as the inability to obtain a high capacitance value.
本考案は上述する従来の欠点を除去し、プリン
ト回路基板に実装した場合、取付方向を上、下、
左、右に取り変えても、プリント回路基板上の導
体パターンに対する浮遊容量の方向性が発生せ
ず、しかも取得容量の大きなチツプ状のコンデン
サを提供することを目的とする。 The present invention eliminates the above-mentioned conventional drawbacks, and when mounted on a printed circuit board, the mounting direction can be changed from top to bottom.
To provide a chip-shaped capacitor that does not cause stray capacitance to be directional with respect to a conductor pattern on a printed circuit board even if it is switched to the left or right, and has a large acquired capacitance.
上記目的を達成するため、本考案は、誘電体磁
器層を間に挾んでその両面側に対となる電極パタ
ーンを対向配置したコンデンサにおいて、電極パ
ターンのそれぞれは、同一面上で互いに独立する
実質的に同一幅の2つの電極を幅方向にギヤツプ
を介して併設すると共に、前記2つの電極の長さ
方向の相反する一端部を、前記誘電体磁器層の長
さ方向の相反する端面にそれぞれ導出し、前記電
極パターン間では、前記2つの電極の幅を対向関
係にある電極と同一幅とすると共に、前記対向関
係にある電極の長さ方向の相反する一端部を前記
誘電体磁器層の長さ方向の相反する端面にそれぞ
れ導出し、対向関係にない電極の長さ方向におけ
る一端部を前記誘電体磁器層の長さ方向の端面に
おいて互いに導通接続させたことを特徴とする。 In order to achieve the above object, the present invention provides a capacitor in which a dielectric ceramic layer is sandwiched between the two electrode patterns, each of which has a pair of electrode patterns facing each other on both sides of the dielectric ceramic layer. Two electrodes having the same width are arranged side by side with a gap in the width direction, and opposite end portions of the two electrodes in the length direction are respectively placed on opposite end surfaces of the dielectric ceramic layer in the length direction. Between the electrode patterns, the two electrodes are made to have the same width as the opposing electrodes, and opposite ends of the opposing electrodes in the length direction are connected to the dielectric ceramic layer. It is characterized in that the electrodes are led out to opposite end faces in the length direction, and one end portions in the length direction of the electrodes that are not in an opposing relationship are conductively connected to each other at the end faces in the length direction of the dielectric ceramic layer.
以下実施例たる添付図面を参照し、本考案の内
容を具体的に説明する。第7図は本考案に係るコ
ンデンサの電極構造を説明する図である。この実
施例では、第1図に示したような内部電極構造の
チツプ状コンデンサを対象としており、誘電体磁
器層17を間に挾んで電極パターン18,19を
対向させた構造となつている。電極パターン18
は、同一面上で互いに独立する2つの電極20,
21を、幅方向にギヤツプg1,g2を介して併設す
ると共に、2つの電極20,21の長さ方向の相
反する一端部を、誘電体磁器層17の長さ方向の
相反する端面にそれぞれ導出する。電極パターン
19でも、同一面上で互いに独立する2つの電極
22,23を、幅方向にギヤツプg3,g4を介して
併設すると共に、2つの電極22,23の長さ方
向の相反する一端部を、誘電体磁器層17の長さ
方向の相反する端面にそれぞれ導出する。そし
て、電極パターン18−19間では、互いに対向
関係にある電極20と電極22、電極21と電極
23の長さ方向の相反する一端部を、誘電体磁器
層17の長さ方向の相反する端面にそれぞれ導出
し、対向関係にない電極20と電極23、電極2
1と電極22の長さ方向における一端部を、誘電
体磁器層17の長さ方向の端面において互いに導
通接続させてある。 DESCRIPTION OF THE PREFERRED EMBODIMENTS The content of the present invention will be specifically described below with reference to the accompanying drawings, which are examples. FIG. 7 is a diagram illustrating the electrode structure of the capacitor according to the present invention. In this embodiment, a chip-shaped capacitor having an internal electrode structure as shown in FIG. Electrode pattern 18
are two mutually independent electrodes 20 on the same plane,
21 are placed side by side in the width direction with gaps g 1 and g 2 interposed therebetween, and opposite ends of the two electrodes 20 and 21 in the length direction are connected to opposite end faces of the dielectric ceramic layer 17 in the length direction. Derive each. Also in the electrode pattern 19, two mutually independent electrodes 22 and 23 are provided on the same surface side by side with gaps g 3 and g 4 interposed therebetween, and one opposite end of the two electrodes 22 and 23 in the length direction is provided. portions are respectively led out to opposite end faces in the length direction of the dielectric ceramic layer 17. Then, between the electrode patterns 18 and 19, opposite ends in the length direction of the electrodes 20 and 22, and electrodes 21 and 23, which are in a mutually opposing relationship, are connected to opposite ends in the length direction of the dielectric ceramic layer 17. The electrodes 20 and 23, which are not in a facing relationship, and the electrode 2
1 and one end of the electrode 22 in the length direction are electrically connected to each other at the end face of the dielectric ceramic layer 17 in the length direction.
電極パターン18に属する2つの電極20,2
1は、容量取得の主要な重なり面積を生じる電極
部分20a,21aの幅W1がほぼ同一となるよ
うにし、この電極部分20a,21aに連設した
電極取出部20b,21bを誘電体磁器層17の
長さ方向における両端部にそれぞれ導出してあ
る。電極パターン19側においても、容量取得の
主要な重なり面積を生じる電極部分22a,23
aの幅W2が電極部分20a,21aの幅W1とほ
ぼ同一になるようにし、この電極部分22a,2
3aに連設した電極取出部22b,23bを誘電
体磁器層17の長さ方向における両端部にそれぞ
れ導出してある。したがつて、異なる電極パター
ン18,19間では、対向しない電極20と電極
23の電極取出部20b,23bおよび電極21
と電極22の電極取出部21b,22bが、誘電
体磁器層17の同一端部に導出されることとな
る。そして、誘電体磁器層17の同一端部に導出
された電極取出部20b,23b、21b,22
bを、誘電体磁器層17の両端部に付与される端
部電極(第1図、第2図の符号4,5で示す)に
よつて互に導通接続する。すなわち、第8図にモ
デル化して示すように、電極20と電極23とを
端部電極による接続ラインイによつて導通させ、
電極21と電極22とを同じく接続ラインロによ
つて導通させるものである。 Two electrodes 20, 2 belonging to the electrode pattern 18
1, the widths W 1 of the electrode parts 20a and 21a, which produce the main overlapping area for capacitance acquisition, are made to be almost the same, and the electrode extraction parts 20b and 21b connected to the electrode parts 20a and 21a are formed using a dielectric ceramic layer. 17 are led out at both ends in the length direction. Also on the electrode pattern 19 side, electrode portions 22a and 23 that produce the main overlapping area for capacitance acquisition
The width W 2 of a is approximately the same as the width W 1 of the electrode portions 20a, 21a, and these electrode portions 22a, 2
Electrode extraction portions 22b and 23b connected to the dielectric ceramic layer 3a are led out at both ends in the length direction of the dielectric ceramic layer 17, respectively. Therefore, between the different electrode patterns 18 and 19, the electrode extraction portions 20b and 23b of the electrode 20 and the electrode 23 that do not face each other and the electrode 21
The electrode extraction parts 21b and 22b of the electrode 22 are led out to the same end of the dielectric ceramic layer 17. Electrode extraction portions 20b, 23b, 21b, 22 led out to the same end of the dielectric ceramic layer 17
b are electrically connected to each other by end electrodes (indicated by reference numerals 4 and 5 in FIGS. 1 and 2) provided at both ends of the dielectric ceramic layer 17. That is, as modeled and shown in FIG. 8, the electrode 20 and the electrode 23 are electrically connected through the connection line 1 formed by the end electrode.
The electrode 21 and the electrode 22 are also electrically connected through a connecting line.
上述のような構造であると、プリント回路基板
に実装するにあたり、第9図に示すように、電極
20,23に導通する端部電極24を導体パター
ン7に半田付けし、電極21,22に導通する端
部電極25を導体パターン8に半田付けした場合
と、第10図に示すように、端部電極25を導体
パターン9に半田付けし、端部電極24を導体パ
ターン8に半田付けした場合とで、導体パターン
9に対するコンデンサの電極関係が全く同一とな
る。コンデンサを反転させて取付けた場合でも、
外層たる誘電体磁器層の層厚が同一である限り、
同様である。したがつて、上下、左右方向の浮遊
容量C3の方向性をほぼ完全になくし、取付方向
に左右されることなく浮遊容量C3を一定化する
ことができる。 When the above structure is mounted on a printed circuit board, as shown in FIG. In the case where the conductive end electrode 25 is soldered to the conductive pattern 8, and in the case where the end electrode 25 is soldered to the conductive pattern 9 and the end electrode 24 is soldered to the conductive pattern 8, as shown in FIG. The relationship between the electrodes of the capacitor and the conductor pattern 9 is exactly the same in both cases. Even if the capacitor is installed upside down,
As long as the thickness of the outer dielectric ceramic layer is the same,
The same is true. Therefore, the directivity of the stray capacitance C 3 in the vertical and horizontal directions can be almost completely eliminated, and the stray capacitance C 3 can be made constant regardless of the mounting direction.
電極パターンの他の例としては、第11図A,
B、第12図A,Bに示すようなものが考えられ
る。第11図A,Bに示すものは、電極パターン
18およびこれと対向する電極パターン19を、
櫛歯状の電極20,21、22,23を互にかみ
合わせて構成してある。電極20,21、22,
23の櫛歯数は任意でよい。また、櫛歯部分の幅
aはほぼ同一とする。 Other examples of electrode patterns are as shown in FIG. 11A,
B. The types shown in FIGS. 12A and 12B are conceivable. In the case shown in FIGS. 11A and 11B, an electrode pattern 18 and an electrode pattern 19 opposite thereto are
It is constructed by interlocking comb-shaped electrodes 20, 21, 22, and 23. Electrodes 20, 21, 22,
The number of comb teeth (23) may be arbitrary. Furthermore, the width a of the comb tooth portions is approximately the same.
また、第12図A,Bに示す実施例では、電極
パターン18,19は、中心部に電極21または
23を設けると共に、この電極21または23を
両側から挾むように、電極20または22を設け
たパターンとなつている。電極21,23の幅b
は電極20,22の幅cの2倍とする。従つて、
電極21,23の幅は実質的に同一となる。完成
した状態では、電極20と電極22、電極21と
電極23とが互に対向する。そして対向関係にな
い電極20と電極23、電極21と電極22と
を、誘電体磁器層17の両端部で端部電極により
導通接続する。 Further, in the embodiments shown in FIGS. 12A and 12B, the electrode patterns 18 and 19 have an electrode 21 or 23 in the center and electrodes 20 or 22 sandwiching the electrode 21 or 23 from both sides. It has become a pattern. Width b of electrodes 21, 23
is twice the width c of the electrodes 20 and 22. Therefore,
The widths of the electrodes 21 and 23 are substantially the same. In the completed state, electrode 20 and electrode 22, and electrode 21 and electrode 23 face each other. Then, the electrode 20 and the electrode 23 and the electrode 21 and the electrode 22, which are not in a facing relationship, are electrically connected at both ends of the dielectric ceramic layer 17 by end electrodes.
これらの実施例の場合も、上下、左右方向への
浮遊容量の方向性をなくし、取付方向に左右され
ることなく、浮遊容量を一定化することができ
る。なお、上記実施例では、電極パターンは2層
だけとなつているが、より多層化して積層形のチ
ツプ状コンデンサとすることができる。 In the case of these embodiments as well, the directionality of the stray capacitance in the vertical and horizontal directions can be eliminated, and the stray capacitance can be made constant regardless of the mounting direction. In the above embodiment, the electrode pattern has only two layers, but it is possible to have more layers to form a laminated chip-shaped capacitor.
以上述べたように、本考案は、誘電体磁器層を
間に挾んでその両面側に対となる電極パターンを
対向配置したコンデンサにおいて、電極パターン
のそれぞれは、同一面上で互いに独立する実質的
に同一幅の2つの電極を幅方向にギヤツプを介し
て併設すると共に、前記2つの電極の長さ方向の
相反する一端部を、前記誘電体磁器層の長さ方向
の相反する端面にそれぞれ導出し、前記電極パタ
ーン間では、前記2つの電極の幅を対向関係にあ
る電極と同一幅とすると共に、前記対向関係にあ
る電極の長さ方向の相反する一端部を前記誘電体
磁器層の長さ方向の相反する端面にそれぞれ導出
し、対向関係にない電極の長さ方向における一端
部を前記誘電体磁器層の長さ方向の端面において
互いに導通接続させたことを特徴とするから、プ
リント回路基板に実装する場合、実装方向を上
下、左右に取り変えても、プリント回路基板上の
導体パターンに対する浮遊容量の方向性がなく、
取付方向に左右されることなく、浮遊容量を一定
化し得る大容量のチツプ状コンデンサを提供する
ことができる。 As described above, the present invention provides a capacitor in which paired electrode patterns are arranged facing each other on both sides of a dielectric ceramic layer with a dielectric ceramic layer in between, in which each of the electrode patterns is substantially independent of the other on the same surface. Two electrodes having the same width are provided side by side with a gap in the width direction, and opposite ends of the two electrodes in the length direction are respectively led out to opposite end faces of the dielectric ceramic layer in the length direction. However, between the electrode patterns, the width of the two electrodes is the same as that of the opposing electrode, and one opposite end of the opposing electrode in the length direction is set to the same width as the opposing electrode. The printed circuit is characterized in that the electrodes are led out to opposite end faces in the transverse direction, and one end in the length direction of the electrodes that are not facing each other is conductively connected to each other at the end face in the length direction of the dielectric ceramic layer. When mounting on a board, even if the mounting direction is changed from top to bottom or left to right, there is no directionality of stray capacitance with respect to the conductor pattern on the printed circuit board.
It is possible to provide a large-capacity chip-shaped capacitor that can keep stray capacitance constant regardless of the mounting direction.
第1図および第2図は従来のチツプ状コンデン
サの断面図、第3図および第4図はプリント回路
基板へ実装したときの欠点を説明する図、第5図
は従来のチツプ状コンデンサの別の例における断
面図、第6図は同じくその等価回路図、第7図は
本考案に係るコンデンサの電極構造を示す図、第
8図は同じく電気的接続をモデル化して示す図、
第9図および第10図は同じくその効果を説明す
る図、第11図A,Bおよび第12図A,Bは同
じく他の実施例における電極パターンを示す図で
ある。
17……誘電体磁器層、18,19……電極パ
ターン、20,21……電極パターン18の電
極、22,23……電極パターン19の電極。
Figures 1 and 2 are cross-sectional views of conventional chip capacitors, Figures 3 and 4 are diagrams illustrating drawbacks when mounted on a printed circuit board, and Figure 5 is a cross-sectional view of a conventional chip capacitor. 6 is an equivalent circuit diagram thereof, FIG. 7 is a diagram showing the electrode structure of the capacitor according to the present invention, and FIG. 8 is a diagram showing a modeled electrical connection.
FIGS. 9 and 10 are diagrams similarly explaining the effect, and FIGS. 11A and 11B and FIGS. 12A and B are diagrams similarly showing electrode patterns in other embodiments. 17... Dielectric ceramic layer, 18, 19... Electrode pattern, 20, 21... Electrode of electrode pattern 18, 22, 23... Electrode of electrode pattern 19.
Claims (1)
る電極パターンを対向配置したコンデンサにおい
て、電極パターンのそれぞれは、同一面上で互い
に独立する実質的に同一幅の2つの電極を幅方向
にギヤツプを介して併設すると共に、前記2つの
電極の長さ方向の相反する一端部を、前記誘電体
磁器層の長さ方向の相反する端面にそれぞれ導出
し、前記電極パターン間では、前記2つの電極の
幅を対向関係にある電極と同一幅とすると共に、
前記対向関係にある電極の長さ方向の相反する一
端部を前記誘電体磁器層の長さ方向の相反する端
面にそれぞれ導出し、対向関係にない電極の長さ
方向における一端部を前記誘電体磁器層の長さ方
向の端面において互いに導通接続させたことを特
徴とするコンデンサ。 In a capacitor having a pair of electrode patterns disposed opposite each other on both sides of a dielectric ceramic layer, each of the electrode patterns has two electrodes of substantially the same width that are independent of each other arranged side by side on the same surface with a gap in the width direction, and opposite ends of the two electrodes in the length direction are respectively led out to opposite end faces in the length direction of the dielectric ceramic layer, and between the electrode patterns, the width of the two electrodes is the same as that of the electrode facing each other, and
A capacitor characterized in that one end portion in the longitudinal direction of the electrodes in an opposing relationship is led out to each of the opposing end faces in the longitudinal direction of the dielectric ceramic layer, and one end portion in the longitudinal direction of the electrodes not in an opposing relationship is conductively connected to each other at the end face in the longitudinal direction of the dielectric ceramic layer.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4183281U JPS6325716Y2 (en) | 1981-03-25 | 1981-03-25 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP4183281U JPS6325716Y2 (en) | 1981-03-25 | 1981-03-25 |
Publications (2)
Publication Number | Publication Date |
---|---|
JPS57157128U JPS57157128U (en) | 1982-10-02 |
JPS6325716Y2 true JPS6325716Y2 (en) | 1988-07-13 |
Family
ID=29838872
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP4183281U Expired JPS6325716Y2 (en) | 1981-03-25 | 1981-03-25 |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS6325716Y2 (en) |
Families Citing this family (3)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7075774B2 (en) * | 2002-09-10 | 2006-07-11 | Tdk Corporation | Multilayer capacitor |
JP4646779B2 (en) * | 2005-10-26 | 2011-03-09 | 京セラ株式会社 | Multilayer capacitor, multilayer capacitor mounting structure, and multilayer capacitor manufacturing method |
CN111886663B (en) * | 2018-03-06 | 2022-11-04 | 京瓷Avx元器件公司 | Multilayer ceramic capacitor with ultra-wideband performance |
-
1981
- 1981-03-25 JP JP4183281U patent/JPS6325716Y2/ja not_active Expired
Also Published As
Publication number | Publication date |
---|---|
JPS57157128U (en) | 1982-10-02 |
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