JPH01268049A - Diffused resistor element - Google Patents

Abstract

PURPOSE:To suppress the effect of a FET and to obtain a stable resistance value, by connecting a first diffused resistor and a second resistor respectively comprising specified semiconductor regions in parallel, and electrically isolating the second diffused resistor so that said resistor is not forward-biased with respect to the first diffused resistor. CONSTITUTION:A first diffused resistor comprising a first conductivity type semiconductor region 11 which is formed in a second conductivity type semiconductor region 12 in a first conductivity type semiconductor region 13 is connected to a second diffused resistor comprising the second conductivity type semiconductor region 12 in a parallel. The second diffused resistor is electrically isolated so that the resistor 1 is not forward-biased with respect to the first diffused resistor. For example, the N<-> type well region 12 is formed in the P-type silicon substrate 13. The P-type impurity diffused region 11 is formed in the well region 12. Opening parts are formed in an insulating film 14 covering the surface. Electrodes 21-24 are provided at the opening parts so that the electrodes are used as the terminals of the diffused resistors. Buffers 15 and 16 are connected between the electrode 21 and the electrode 22 and between the electrode 23 and the electrode 24.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to a diffused resistance element constructed using a semiconductor region of a desired conductivity type, and particularly to a diffused resistance element in which the FET effect is suppressed.

[Summary of the invention]

The diffused resistance element of the present invention includes the second conductive type semiconductor region in a first diffused resistor made of a first conductive type semiconductor region formed in a second conductive type semiconductor region in a first conductive type semiconductor region. A second diffused resistor is connected in parallel, and the second diffused resistor is connected to the first diffused resistor! @
By electrically separating them so as not to create a bias, the FET effect is suppressed and a stable resistance value is obtained.

[Prior Art] When various signal processing circuits are constructed using a semiconductor integrated circuit device, a diffused resistance element formed from an impurity diffusion region by diffusing impurities into a semiconductor substrate is sometimes used as the resistance element.

FIG. 5 shows an example of a conventional diffused resistance element, in which an N-type epitaxial layer 52 is formed on a P-type semiconductor substrate 51, and a P-type impurity is diffused into a part of the surface of the N-type epitaxial layer 52. A region 53 is formed. An insulating film 54 covering the surface of the semiconductor substrate 51 covers both ends of the P-type impurity diffusion region 53 and the N-type epitaxial layer 52.
The electrodes 55a, 55 are opened in the openings.
b and 55c are provided. Here, the terminals of the diffused resistor are electrodes 55a and 55b, and electrode 55c is provided for applying a required voltage. In addition, as a technology related to such a diffused resistor, Japanese Patent Application Laid-Open No. 1986-
There is a prior art described in Japanese Patent No. 50553.

An example of the use of such a diffused resistance element is one used in a non-inverting amplifier or an inverting amplifier, as shown in FIGS. 6 and 7. As is known as -II, the gain of these is determined by the resistance.

That is, in the non-inverting amplifier shown in FIG.
, Rz determines the gain, and the gain A=(1+R1/R1).Furthermore, in the inverting amplifier shown in FIG. 7, the gain A--
(R2/R1).

[Problem to be solved by the invention]

In the semiconductor device forming the above-described diffused resistance element, the sheet resistivity ρ is increased in order to operate at low power, and the junction of the diffusion layer tends to be made shallow in order to increase the degree of integration.

However, when trying to achieve such high sheet resistivity or shallow junk silane, the above-mentioned diffused resistance element
The FET effect has become significant, and changes in its resistance have become a problem. That is, according to the example shown in FIG. 5, the diffused resistance element utilizes the impurity diffusion region 53, and a depletion 157 occurs at the junction 56 thereof. This depletion layer 57 expands when the impurity concentration is low, and the shallower the junction 56 is, the smaller the ratio of the area other than the depletion layer 57 in the impurity diffusion region 53 becomes. The FET effect becomes noticeable and its resistance value tends to shift.

Furthermore, when a circuit is configured using the above-mentioned diffused resistance element, for example, in the amplifier shown in FIGS. 6 and 7, the FE
The T effect causes problems such as gain fluctuations and distortion.

Further, the technique disclosed in the above-mentioned publication short-circuits the high potential side of the resistor and a well (land; island-like region) that has the resistor inside to control the potential of the well. However, if the resistance divider for supplying DC bias is not A, or if the potential across the resistor is varied by an AC signal, the problem arises that a stable resistance value cannot be obtained due to the FET effect. Ta.

Therefore, in view of the above-mentioned technical problems, the present invention has been developed to
The purpose of this invention is to provide a diffused resistance element that suppresses the T effect and obtains a stable resistance value.

(Means for Solving the Problems) In order to solve the above-mentioned technical problems, the diffused resistance element of the present invention has a first conductive type formed in a second conductive type semiconductor region in a first conductive type semiconductor region. a first diffused resistor consisting of a type semiconductor region, and a second diffusion resistor consisting of a second conductivity type semiconductor region.
The second diffused resistor is electrically isolated from the first diffused resistor so as not to be forward biased.

Here, in the present invention, for example, a buffer (emitter follower, source follower), a level shift circuit, etc. can be used as a means for electrically isolating so as to prevent forward bias.

[Effect]

The FET effect occurs because the depletion layer formed at the PN junction changes depending on the reverse bias voltage applied across the junction. Therefore, in the diffused resistance element of the present invention, the second diffused resistor made of the second conductivity type semiconductor region is connected in parallel with the first diffused resistor made of the first conductivity type semiconductor region therein. This parallel connection creates an in-phase bias state across the PN junction between the two diffused resistors, suppressing the FET effect. Paying attention to the second diffused resistor, the second diffused resistor is connected to the first diffused resistor as a substrate.
There is a tendency for an FET effect to occur between the conductive type semiconductor region and the conductive type semiconductor region. Therefore, the second diffused resistor itself is separated by electrically isolating means so as not to be forward biased. This separation essentially eliminates the FET effect of parallel connected resistors.

When a buffer or a level shift circuit is used as a means for electrically isolating to prevent forward bias, the first
At the same time, the potentials between the second diffused resistor and the second diffused resistor are maintained in the same phase.

〔Example〕

Preferred embodiments of the present invention will be described with reference to the drawings.

First Embodiment The diffused resistance element of this embodiment uses two diffused resistors and a buffer connected in parallel to sufficiently eliminate the FET effect.

First, the circuit configuration is shown in FIG. As shown in FIG. 1, the diffused resistance element of this example has a second conductivity type semiconductor region (N
A first diffused resistor 1 consisting of a first conductivity type semiconductor region formed in the first conductivity type semiconductor region (N type well region) is attached to a second conductivity type semiconductor region formed in the first conductivity type semiconductor region (N type well region). diffused resistors 2 are connected in parallel, and a buffer 3.4 is provided between each terminal of the first diffused resistor I and the second diffused resistor 2, respectively. That is, the input side of the buffer 3 is connected to one terminal 5 of the first diffused resistor l, and the second diffused resistor 2 is connected to the output side of the buffer 3.
One terminal of is connected.

2. The input side of a buffer 4 is connected to the other terminal 6 of the first diffused resistor 1, and the other terminal of the second diffused resistor 2 is connected to the output side of the buffer 4. .

The second diffused resistor 2 is biased with equal polarization by a P-type silicon substrate, and the P
A parasitic capacitance I Cc s is also formed at the N junction.

In the diffused resistor element of this embodiment having such a circuit configuration, the first diffused resistor 1 is connected in parallel with the second diffused resistor 2, and due to this parallel connection relationship, the difference between the two diffused resistors is The in-phase bias state is applied across the PN junction between the two, and the FET effect is suppressed. The parallel connection is performed via buffers 3 and 4, and therefore, the second diffused resistor 2 is maintained at the same potential as the first diffused resistor 1, and the second diffused resistor 2 is maintained at the same potential as the first diffused resistor 1.
While maintaining zero bias between the two diffused resistors 1.2,
FE due to PN junction between the second diffused resistor 2 and the substrate
It blocks the T effect.

FIG. 2 is a sectional view of a main part of the diffused resistance element of this embodiment, showing an N-type well region 12 formed in a P-type silicon substrate 13 and a structure formed in the N-type well region 12. It has a P-type impurity diffusion region 11. An opening is formed in the insulating film 14 covering the surface, and electrodes 21, 22, 23, 24 are provided in the opening to serve as terminal electrodes of each diffused resistor. Buffers 15 and 16 are connected between the electrodes 21 and 22 and between the electrodes 23 and 24.

To explain in more detail, the P-type silicon substrate 11
is grounded, and active elements such as transistors and passive elements such as capacitors are formed in other regions of this silicon substrate 11. The N-type well region 12 is formed separated from other elements, and the well region 12
The P-type impurity diffusion region 11 is formed therein.

On the surface of the substrate of the well region 12, there is an N-type high concentration impurity diffusion region 25. for making ohmic contact.
25 are provided, and the well region 12 is connected to the electrodes 21.24 via these N-type high concentration impurity diffusion regions 25.25.

A P-type impurity diffusion region 11 serving as a first diffused resistor is surrounded by an N-type well region 12 in the substrate. It faces the main surface of the substrate covered with the insulating film 14. This P-type impurity diffusion region 11 has terminals provided at both ends in parallel with the high concentration impurity diffusion regions 25.25, and electrodes 22.23 serving as the terminals are formed in closed portions formed in the insulating film 14. It is connected to the impurity diffusion region 11 of the IP type through.

The input side of the buffer 15, which is a high impedance terminal, is connected to the electrode 22. The output side of the buffer 15 is connected to the electrode 21. Similarly, the above buffer 1
6, the input side which is a high impedance terminal is connected to the above electrode 2.
Connect to 3. The output side of the buffer 16 is the electrode 2
Connect to 4.

The input side of the buffer 15 is connected to the electrode 22.
is one terminal 17 of the diffused resistance element, and the upper electromotive plate 23 connected to the input side of the buffer 16 is the other terminal 18 of the diffused resistance element.

In the diffused resistance element shown in FIG.
．． 16 to maintain the same potential, maintaining zero bias between the two diffused resistors. This is the PN junction 2 between the P-type impurity diffusion region 11 and the N-type well region 12.
If 0 is forward biased, the PN diode O
Although an N current will flow, zero bias or reverse bias will prevent an 0 Ntf current from flowing in the PN junction 20. Therefore, it can effectively function as a low distortion resistor.

Furthermore, in this diffused resistance element, the buffer 1
Due to the impedance characteristic of 5.16, it is possible to block the FET effect due to the PN junction 19 between the second diffused resistor and the substrate. Therefore, the resistor operates in a state where distortion is significantly removed.

In the above-mentioned embodiment, the buffer 15°16 was used as a means for electrically isolating to prevent forward bias.
A level shift circuit may be used to maintain the reverse bias of the PN junction 20, and the conductivity type P, N
may have opposite configurations.

Second Embodiment This embodiment is an example in which diffused resistance elements having the above-described configuration are used for a non-inverting amplifier and an inverting amplifier, respectively.

First, FIG. 3 shows an example of a non-inverting amplifier. Resistors 32 and 33 are connected to one terminal of the operational amplifier 31,
The other end of the resistor 32 is connected to the output terminal, and the other end of the resistor 33 is grounded. Each of these resistors 32 and 33 has an input side (high impedance side) connected to the resistor 32 and 33.
Buffers 34, 36, 37, 39 are provided to connect to. A resistor 35 is provided between the output sides of the buffers 34 and 36, and a resistor 38 is provided between the output sides of the buffers 37 and 39. Note that an input signal is supplied to a child terminal of the operational amplifier 31.

In this circuit, resistor 32.33 is the first diffused resistor and resistor 35.38 is the second diffused resistor. Therefore, the FET effect is significantly suppressed, and therefore a gain with extremely low distortion can be obtained.

Next, FIG. 4 shows an example of an inverting amplifier. operational amplifier 4
Resistors 42 and 43 are connected to the child terminals of resistor 42, the other end of resistor 42 is connected to the output terminal, and the other end of resistor 43 is supplied with an input signal.

Each of these resistors 42.43 is provided with a buffer 44, 46, 47.49 that connects an input end (high impedance side) to the resistor 42.43. A resistor 45 is provided between the output sides of the buffers 44 and 46, and a resistor 48 is provided between the output sides of the buffers 47 and 49.
is provided. Note that one terminal of the operational amplifier 31 is
Grounded.

Similarly, in this circuit, resistors 42 and 43 are first diffused resistors, and resistors 45 and 48 are second diffused resistors. Therefore, the FET effect is significantly suppressed, and therefore a gain with extremely low distortion can be obtained.

In addition, each buffer in the above-mentioned embodiment may be a level shift circuit. In the case of a level shift circuit, the first
and the second diffused resistor shall be maintained at a reverse bias.

〔Effect of the invention〕

As described above, in the diffused resistance element of the present invention, the PN junction between the first diffused resistor and the second diffused resistor is maintained at zero bias or reverse bias over the entire junction. Therefore, the FET effect due to the PN junction is sufficiently suppressed. Furthermore, since the second diffused resistor is separated by an electrically isolating means such as a buffer or a level shift circuit so as not to cause an order bias, the FET effect between it and the substrate is also blocked. Therefore, a circuit with low distortion can be obtained.

[Brief explanation of the drawing]

FIG. 1 is a circuit diagram of an example of the diffused resistance element of the present invention, FIG. 2 is a 7-part sectional view of an example of the diffused resistance element of the present invention, and FIG. 3 is a circuit diagram of an example of the diffused resistance element of the present invention. Circuit Diagram of Inverting Amplifier FIG. 4 is a circuit diagram of an inverting amplifier using an example of the diffused resistance element of the present invention. Further, FIG. 5 is a sectional view of a main part of an example of a conventional diffused resistance element, FIG. 6 is a circuit diagram of a general non-inverting amplifier, and FIG. 7 is a circuit diagram of a general inverting amplifier. 1... First diffused resistor 2... Second diffused resistor 3.4... Buffer 11... P type impurity diffusion region 12... N- type well region 13...・P-type silicon substrate 15.16...Buffer patent applicant Akira Koike, patent attorney representing Sony Corporation (and 2 others) Figure 1 Figure 2 Figure 3 M2! Figure 4

Claims (1)

[Claims] A first diffused resistor made of a first conductive type semiconductor region formed in a second conductive type semiconductor region in the first conductive type semiconductor region, and a second diffused resistor made of the second conductive type semiconductor region. 1. A diffused resistance element connected in parallel and electrically separated so that the second diffused resistor is not forward biased with respect to the first diffused resistor.