JPH01268048A - Diffused resistor element - Google Patents

Abstract

PURPOSE:To suppress the effect of a FET and to obtain a stable resistance value, by connecting a second conductivity type semiconductor region as a second diffused resistor in parallel to a first diffused resistor comprising a first conductivity type semiconductor region which is formed in the second conductivity semiconductor region in the first conductivity type semiconductor region. CONSTITUTION:A first diffused resistor comprising a first conductivity type semiconductor region 1 which is formed in a second conductivity type semiconductor region 2 in a first conductivity type semiconductor region 3 is connected to a second diffusion resistor comprising said second conductivity type semiconductor region 2 in parallel. For example, an N<-> type epitaxial layer 2 is separated from other elements and formed on a P-type silicon substrate 3. A P-type impurity diffused region 1 is formed in the layer 2. A pair of N<+> type high concentration impurity diffused regions 6 and 6 are formed in ohmic-contact with the neighboring P-type impurity diffused region on the surface part of the substrate. A pair of opening parts 8 and 8 are formed in an insulating layer 7 which covers the main surface of the substrate. An electrode 4 and an electrode 5 are formed at the opening parts 8 and 8, and a terminal A and a terminal B are provided.

Description

DETAILED DESCRIPTION OF THE INVENTION (Field of Industrial Application) The present invention relates to a diffused resistance element constructed using a semiconductor region of a desired conductivity type, and particularly to a diffused resistance element in which the FET effect is suppressed.

[Summary of the invention]

The diffused resistor element of the present invention includes a first diffused resistor made of a first conductive type semiconductor region formed in a second conductive type semiconductor region in a first conductive type semiconductor region, and a second conductive type semiconductor as described above. By connecting the regions in parallel as a second diffused resistor, the FET effect is suppressed and a stable resistance value is obtained.

[Conventional technology]

When various signal processing circuits are constructed using semiconductor integrated circuit devices, a diffused resistance element formed from an impurity diffusion region by diffusing impurities into a semiconductor substrate is sometimes used as the resistance element.

FIG. 4 shows an example of a conventional diffused resistance element, in which an N-type epitaxial layer 42 is formed on a P-type semiconductor substrate 4, and a part of the surface of the N-type epitaxial layer 42 is doped with P-type impurities. A wave'#i region 43 is formed. An insulating film 44 covering the surface of the semiconductor substrate 41 covers both ends of the P-type impurity diffusion region 43 and the N-type epitaxial region 1.
1142 are opened, and electrodes 45 are placed in these openings.
a, 45b and 45c are provided. Here, the terminals of the expansion paper antibody are electric FfA45a, 45b,
Electrode 45c is provided for applying a required voltage.

Further, as a technology related to such a diffused resistor, there is a prior art described in Japanese Patent Application Laid-Open No. 56-50553.

[Problem to be solved by the invention]

In the semiconductor device forming the above-described diffused resistance element, the sheet resistivity ρ is increased in order to operate at low power, and the junction of the diffusion layer tends to be made shallow in order to increase the degree of integration.

However, when trying to achieve such high sheet resistivity and shallow junction, the above-mentioned diffused resistance element
The FET effect has become significant, and changes in its resistance have become a problem. That is, according to the example of FIG. 4, the diffused resistance element utilizes the impurity diffusion region 43, and a depletion N47 occurs at the junction 46 thereof. This depletion 1i47 is
The lower the impurity concentration, the more it spreads, and the shallower the junction 46, the smaller the proportion of the region other than the depletion layer 47 in the impurity diffusion region 43. Therefore, the FET effect due to the expansion of the depletion 1i47 becomes significant, and its resistance value tends to shift.

Further, the technique disclosed in the above-mentioned publication short-circuits the high potential side of the resistor and a well (land; island-like region) that has the resistor inside to control the potential of the well. However, if the resistance division for supplying DC bias is not %, or if the potential across the resistor is varied by an AC signal, the problem arises that a stable resistance value cannot be obtained due to the FET effect. was.

Therefore, in view of the above-mentioned technical problems, the present invention has been developed to
The object of the present invention is to provide a diffused resistance element that suppresses the T effect and obtains a stable resistance value.

[Means to solve the problem]

In order to achieve the above object, the diffused resistance element of the present invention has the following features:
A first diffused resistor made of a first conductive type semiconductor region formed in a second conductive type semiconductor area in the first conductive type semiconductor region, and a second diffused resistor made of the second conductive type semiconductor region. It is characterized by being connected in parallel.

[Effect]

The FET effect is due to the fact that the depletion layer formed at the PN junction changes depending on the reverse bias voltage applied across the junction. Then, the resistance value of the diffused resistance element is modulated according to the spread of its depletion layer. Therefore, in the diffused resistance element of the present invention, the second
The diffused resistor is connected in parallel with the first conductivity type semiconductor region (first diffused resistor) which is the original diffused resistor therein, and the signal changes in the same phase throughout the PN junction, Bring the whole thing to zero bias state. As a result, modulation of the resistance value due to the FET effect is suppressed.

Here, a description will be given of how the FET effect is reduced. First, in a conventional diffused resistance element, the resistance value of the first diffused resistor made of the first impurity diffusion region is set to R.
o, the reverse bias voltage is Vl (v), and the modulation rate at that time is 100 kO (%). Then, Re (v+) - (6 to 1+) R6 (o) -...
■It becomes. Furthermore, in a resistor made of a second conductivity type semiconductor region, for example, an epitaxial layer, Rtp+ (Vl)-(1+kEp+) REPI due to the influence of a depletion layer.
(0) −■. And the sheet resistivity ρ of the resistor made of the above epitaxial layer,! When the ratio of the sheet resistivity ρ at the resistance R0 to 1 is N (N>1), it can be expressed as NRe (0)=Rt□(0)...■.

Next, the combined resistance RTOf (0) at zero bias is set to 1
+N (°, ° from equation ①).

However, in the diffused resistance element of the present invention, although k and □ receive modulation due to the relationship with the substrate, ko becomes zero. That is, the spread of the depletion layer between the first diffused resistor and the second diffused resistor is maintained in the same relationship even when the reverse bias voltage is increased, and the modulation degree of 0 is the same according to the present invention. 6 = o in the diffused resistance element. Therefore, the voltage v
At the time of bias l, the combined resistance Ryot (
■For I), from formulas ■, ■, and ■, Ro (Vl)+RFpI (Vl)R,)(0)
(□+ to it-) RlPI (0) Re (0
) + (1+kir+) Rxr+ (0)1+N
(□ to 1+) becomes. Here, when calculating the rate of change ΔR (v+), from equations ① and ②, RyoT (0) N (*p+ to 1+) 1 +N1+N
(1+kEr+) N1+N (1+k
ir+) □ to ten.

1+N (to 1+, □), and it can be seen that the rate of change ΔR(v+) depends on the values of kFp+ and N.

FIG. 3 compares the conventional diffused resistance element (broken line) and the diffused resistance element of the present invention (solid line), where the horizontal axis represents the bias voltage and the vertical axis represents the modulation factor of 00. In the conventional diffused resistance element, the modulation rate (k) increases as the reverse bias voltage increases, but it is shown that the modulation is sufficiently suppressed in the diffused resistance element of the present invention.

Next, to explain how much the FET effect is improved, if the ratio of the modulation degree of 0 and the modulation degree of the epitaxial layer kir+ of the second diffused resistor is M, then ke -MkFr+ , (M '＞１）・・・■
From the above formula 0, ΔR(V, ) = 6/((1+N) ・M)
...■, and the denominator for k is (14N) ・
It can be seen that the FET effect is reduced by the amount of M.

If N-3, M-2, 5, the rate of change ΔR(
Vl) is k. /10, resulting in an improvement of about 20 dB.

(Example〕 Preferred embodiments of the present invention will be described with reference to the drawings.

The diffused resistor element of this example utilizes two diffused resistors connected in parallel to realize suppression of the FET effect.

First, as for its structure, as shown in FIG. The main structure is 1.

The P-type silicon substrate 3 is grounded, and active elements such as transistors and passive elements such as capacitors are formed in other regions of the silicon substrate 3. The N- type epitaxial layer 2 is formed separated from other elements, and the P-type impurity diffusion region 1 is formed therein. The N'' type epitaxial layer N2 functions as a second diffused resistor, and from the voltage applied to the epitaxial layer 2, the depletion layer formed in the PN junction 10 between the P type impurity diffusion region 1 and the P type impurity diffusion region l is detected. Modulation of the resistance value is suppressed.On the surface of the substrate, a pair of N-type high concentration impurity diffusion regions 6. are provided adjacent to the P-type impurity diffusion region 1 to establish an ohmink contact. 6 is formed. That is, a voltage is applied to the N- type epitaxial layer 2 through these N-type high concentration impurity diffusion regions 6, 6. P-type as the first diffused resistor The impurity diffusion region 1 is surrounded by an N-type epitaxial layer 2 in the substrate and is formed facing the main surface of the substrate covered with the insulating layer 7. The insulation N7 at both ends has a pair of openings 8.8 for applying voltage.
is formed. These openings 8.8 extend not only to both ends of the P-type impurity diffusion region 1 but also to the upper part of the N''-type high concentration impurity diffusion region 6.6. An electrode 4 and an electrode 5 are formed in these openings 8 and 8, with the electrode 4 serving as a terminal A and the electrode 5 serving as a terminal B.

The diffused resistance element of this example having such a structure can be represented by an equivalent circuit as shown in FIG. In Figure 2, two resistors R0 and R0 are connected between terminal A and terminal B.
1PI are connected in parallel, the resistor R6 is the first diffused resistor formed by the P-type impurity diffusion region 1, and the resistor R1
, 1 is a second diffused resistor formed of an N-type epitaxial layer 2.

The N-type epitaxial layer 2 has a higher resistance value than the P-type impurity diffusion region 1, and the reduction of the FET effect of the diffused resistance element of this embodiment having such a structure is described in the above [effect]. As in the 0th equation, ΔR(V+)=ko/((1+N)・M)(
Then, N=Rtp/R., M-ka/A2. ).

Table 1 shows data regarding various resistors (TYPEs 1 to 3) to which the diffused resistance element of this example is applied.

Table 1 (ktr+=2.7% (voltage 5■)) As is clear from Table 1 above, the rate of change ΔR(V+) is ko
/10 ~ shows a value of about 076, and epitaxial layer 2
It can be seen that the FET effect is reduced by parallel connection of .

As described above, in the diffused resistance element of this example, the original P
An N° type epitaxial layer 2 having a high sheet resistance is provided in parallel with the type impurity diffusion region 1. Since this N- type epitaxial layer 2 is connected in parallel, any part of the junction 10 is set to zero bias, and voltage-dependent modulation of the depletion layer is suppressed. is not affected by the FET effect. The N-type epitaxial layer 2 is modulated (kt
r+ ), but its value is P when not connected in parallel.
It is small compared to the modulation degree (k6) of the type impurity diffusion region l. Therefore, F of the diffused resistor of this example made of composite resistance
The ET effect will be significantly reduced.

In this way, the diffused resistance element of this embodiment, in which the FET effect is reduced, can be used for all kinds of applications. Examples include resistors for setting DC bias, amplifiers, filters, and the like. This is particularly effective for circuits that require distortion removal.

In the above-described embodiment, the N-type high concentration impurity diffusion regions 6, 6 were formed on the surface of the N-type epitaxial layer 2, but contact may be made by other means. Further, the openings 8 and 8 are common contact holes for the P-type impurity diffusion region 1 and the N-type epitaxial layer 2, but they can be separate contact holes if parallel connection is to be realized. It's okay. Also, the first conductivity type is N type.

Although the second electrostatic type is P type, P and N may be reversed.

Further, the diffused resistance element of the present invention is not limited to the above-described embodiments, and various changes can be made without departing from the gist thereof.

[Effects of the Invention] In the diffused resistance element of the present invention, since the first diffused resistor and the second diffused resistor that form a junction are connected in parallel, the FET effect can be sufficiently reduced to improve operational performance. distortion can be suppressed. Furthermore, since the FET effect is suppressed, it becomes easier to arrange the resistors in terms of design, and the effort of simulation can be saved.

Furthermore, the diffused resistance element of the present invention functions satisfactorily as a resistor even when used up to a voltage higher than the power supply voltage Vcc. In principle, it has the ability to withstand pressure between the substrate and the epitaxy layer.

Moreover, it can be applied to any circuit, and is suitable for obtaining a low-distortion signal processing circuit.

[Brief explanation of the drawing]

Fig. 1 is a cross-sectional view of essential parts of an embodiment of the diffused resistance element of the present invention, Fig. 2 is its equivalent circuit diagram, and Fig. 3 is a comparison between the diffused resistance element of the present invention and a conventional diffused resistance element. FIG. 4 is a sectional view of a main part of an example of a conventional diffused resistance element. 1...P-type impurity diffusion region 2...N-type epitaxial layer 3...P-type silicon layer 4.5...Electrode patent applicant Sony Corporation representative patent attorney Akira Koike ( 2 others) A Ro B 2nd
figure

Claims (1)

[Claims] A first diffused resistor made of a first conductive type semiconductor region formed in a second conductive type semiconductor region in the first conductive type semiconductor region, and a second diffused resistor made of the second conductive type semiconductor region. A diffused resistance element characterized by being connected in parallel.