JPS60183762A - Semiconductor integrated circuit device - Google Patents
Semiconductor integrated circuit deviceInfo
- Publication number
- JPS60183762A JPS60183762A JP4081484A JP4081484A JPS60183762A JP S60183762 A JPS60183762 A JP S60183762A JP 4081484 A JP4081484 A JP 4081484A JP 4081484 A JP4081484 A JP 4081484A JP S60183762 A JPS60183762 A JP S60183762A
- Authority
- JP
- Japan
- Prior art keywords
- diffusion layer
- junction
- capacitor
- metal electrode
- circuit device
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000004065 semiconductor Substances 0.000 title claims abstract description 12
- 238000009792 diffusion process Methods 0.000 claims abstract description 30
- 239000002184 metal Substances 0.000 claims abstract description 16
- 239000003990 capacitor Substances 0.000 abstract description 17
- 238000000034 method Methods 0.000 abstract 1
- 239000000758 substrate Substances 0.000 description 2
- 239000003795 chemical substances by application Substances 0.000 description 1
- 238000010276 construction Methods 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 238000005516 engineering process Methods 0.000 description 1
- 230000010354 integration Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
- H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including only semiconductor components of a single kind
- H01L27/0805—Capacitors only
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Semiconductor Integrated Circuits (AREA)
Abstract
Description
【発明の詳細な説明】
〔発明の技術分野Ｊ
この発明は半導体隼積回路装置に関し、特にバイポーラ
■ＣにおけるＭＯＳ （金円−絶縁膜−半導体）容量の
改良に係るものである。DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention J] The present invention relates to a semiconductor integrated circuit device, and particularly to an improvement in MOS (metal circle-insulating film-semiconductor) capacitance in bipolar IC.
従来例でのこの種のバイポーラＩＣ’におけるＭＯ８容
量の概要断面（１り成を第１図に示す。すなわち。A schematic cross section (one configuration) of the MO8 capacitor in this type of bipolar IC' in a conventional example is shown in FIG.
この第１図において、符号１はＰ形半２８体基板５２は
この半導体裁板１上にエピタキシャル成長されたＮ形エ
ピタキシャル層、３はこのＮ形エピタキシャル層２内に
拡散形成されたＰ形ペース拡散層、４はこのＰ形ベース
拡散層３内に高濃鹿に拡散形成されたＮ形エミンタ拡散
層、５はこれらを農うＳｔＯ，などの砲縁膜、６はこの
穐似膜５を誘電体としてＭＯ８容量を構成するように、
エミッタ拡散層４と大部分の範囲で対向させた金属電極
、１は絶縁膜５の開口部を通してエミッタ拡散層４に接
続された金属電極、８および９はこれらの各金属電極６
および７に接続され／こそれぞれ１）Ｌ（・１弱；ｊ子
でるる。In FIG. 1, reference numeral 1 denotes a P-type half-28 substrate 52, an N-type epitaxial layer epitaxially grown on this semiconductor cutting board 1, and 3 a P-type space diffusion formed in this N-type epitaxial layer 2. The layer 4 is an N-type emitter diffusion layer formed by diffusion in this P-type base diffusion layer 3, 5 is a rim film such as StO that feeds these layers, and 6 is a dielectric layer that covers this akin-like film 5. As the body constitutes MO8 capacity,
A metal electrode 1 faces the emitter diffusion layer 4 over most of its range, 1 is a metal electrode connected to the emitter diffusion layer 4 through an opening in the insulating film 5, and 8 and 9 are metal electrodes 6 of each of these metal electrodes.
and 7 are connected to / respectively 1) L (・1 little; j child is Ruru.
しかしてこのようにｆ＋；成される従来例装置？〒にお
けるＭＯ３容量の容量値は、簡嶽膜５の膜Ｊ７およびｔ
、プ電率と、エミッタ拡散層４に対する金１１電（−５
６の対向面積とによって決定され１造営、１００μ７＋
×１００μｍの面積で１０９Ｆ’程度であシ、この従来
（１゛Ｖ成のままでよシ大きな容量値を得るためにはｏ
ｒ：ｊ広い面積を必要としていてチンブザイズが増し
。However, is there a conventional device in which f+ is formed like this? The capacitance value of MO3 capacity at
, and the gold-11 current (-5
Determined by the opposing area of 6, 1 construction, 100μ7+
The area of ×100μm is about 109F', and this conventional method (in order to obtain a larger capacitance value while maintaining the 1゛V configuration)
r:j Requires a large area and increases chimney size.
装置の高集積化、微細化を妨げるものでめった。This was a problem that hindered the high integration and miniaturization of devices.
この発明は従来のこのような欠点に鑑み、バイポーラＩ
Ｃにおいて１．高集稍化、微細化に適合するように狭い
面積で大きな容量値を得るために、ＭＯ８容量を構成す
る金属電極側とペース拡散層とを接続して同電位にさせ
、このＭＯ８容量と並列にエミッタ拡散層とペース拡散
層との接合容量を構成させたものである。In view of these drawbacks of the conventional technology, the present invention has developed a bipolar I
In C 1. In order to obtain a large capacitance value in a narrow area in order to adapt to high density and miniaturization, the metal electrode side that makes up the MO8 capacitor and the pace diffusion layer are connected to have the same potential, and parallel to this MO8 capacitor. The junction capacitance between the emitter diffusion layer and the space diffusion layer is configured as follows.
以下この発明に係る半導体集積回路装置の一実施例につ
き、第２図を参照して詳細に説明する。Hereinafter, one embodiment of the semiconductor integrated circuit device according to the present invention will be described in detail with reference to FIG.
この第２図実施例装置は前記第１図従来例装置に対応し
て表わしたもので、各図中、同一符号は同一または相当
部分を示しておシ、この実施例装置では前記したＭＯ８
容量側の金属電極６に対応する金属電極１１を、前記絶
縁膜５の開口部を通してペース拡散層３に接続させたも
のである。なお１２はこの金属電極１１に接続された電
極端子である。The device of the embodiment shown in FIG. 2 corresponds to the conventional device of FIG.
A metal electrode 11 corresponding to the metal electrode 6 on the capacitor side is connected to the pace diffusion layer 3 through the opening of the insulating film 5. Note that 12 is an electrode terminal connected to this metal electrode 11.
従ってこの実施例ｐｆＲの構成によるときは、゛、ペー
ス拡散層３とエミッタ拡散Ｆ″：４との接合部分におい
てＰＮ接合が形成されるので、これに逆バイアスを印加
することによ多接合容量として利用することができる。Therefore, when using the pfR configuration of this embodiment, a PN junction is formed at the junction between the pace diffusion layer 3 and the emitter diffusion F'': 4, and by applying a reverse bias thereto, the multi-junction capacitance is It can be used as
つまシミ極端子９，１２間には、金属電極１１−絶縁膜
５−エミッタ拡散層４によるＭＯ３容量と、ペース拡散
層３−エミッタ拡散層４による接合容量とが等何曲に並
列されることになる。そしてこのペース拡散層３−エミ
ッタ拡散層４による接合容量の容量値はその空乏層の巾
によシ決定されるが、前記と同行に、−ａ常、１００μ
ｍ×１００μｍの面積で１０ｐＦ程度であって、この実
施例装置の場合、これらのＭＯ８容量と接合容量との容
１−１値を、従来例とはソ同−面積で約２倍に増加させ
ることができるのである。Between the tab stain electrode terminals 9 and 12, the MO3 capacitance formed by the metal electrode 11, the insulating film 5, and the emitter diffusion layer 4, and the junction capacitance formed by the space diffusion layer 3 and the emitter diffusion layer 4 are arranged in parallel in equal numbers. become. The capacitance value of the junction capacitance between the pace diffusion layer 3 and the emitter diffusion layer 4 is determined by the width of the depletion layer.
It is about 10 pF in an area of m x 100 μm, and in the case of this example device, the capacitance 1-1 value of these MO8 capacitance and junction capacitance is increased to about twice that of the conventional example with the same area. It is possible.
以上詳述したようにこの発明に上れば、ＭＯ８Ｏ８容量
つ半導体集積回路装置において、このＭＯ８容量の金属
電極をペース拡散層に接続させて、ＭＯ８容量に並列す
る接合容量を（ｊｌ成させたから。As detailed above, according to the present invention, in a semiconductor integrated circuit device with an MO8O8 capacitor, a metal electrode of the MO8 capacitor is connected to a pace diffusion layer to form a junction capacitance (jl) in parallel with the MO8 capacitor. .
ＭＯ８容量のみの場合に比較してはソ同−面禎で約２倍
の容量値、もしくははマ同一の容量値を約半分の面積で
得ることができ、しかもＦｉＦｆ成が簡単で容易かつ安
価に実施できるなどの特長を有するものである。Compared to the case of only MO8 capacitance, it is possible to obtain approximately twice the capacitance value with the same surface area, or the same capacitance value in approximately half the area, and the FiFf structure is simple, easy, and inexpensive. It has the advantage of being able to be implemented in many ways.
第１図は従来例による半導体集積回路装置でのＭＯ８容
量の概要構成を示す断面図、第２図はこの発明の一実施
例による半導体集積回路装置でのＭＯ８容量の概要構成
を示す断面図である。
１・・・・半導体基板、２・・・・エピタキシャル層（
半導体層）、３・・・・ペース拡散層、４・・・・エミ
ッタ拡散層、５・・・・ｋ ４’ＦＡ膜、７．１１・・
・・金属電極。
代 理 人 大 岩 増 雄
第１図
！
第２図FIG. 1 is a sectional view showing the general structure of an MO8 capacitor in a semiconductor integrated circuit device according to a conventional example, and FIG. 2 is a sectional view showing a general structure of an MO8 capacitor in a semiconductor integrated circuit device according to an embodiment of the present invention. be. 1... Semiconductor substrate, 2... Epitaxial layer (
semiconductor layer), 3...Pace diffusion layer, 4...Emitter diffusion layer, 5...k 4'FA film, 7.11...
...Metal electrode. Agent Masuo Oiwa Figure 1! Figure 2
Claims (1)
次に形成させ、絶縁膜を介しエミッタ拡散層に対向する
金属電極を設けてＭＯ８容量を構成した半導体隼積回路
装置において、このＭ ＯＳ ＄ 肘の金属電極をベー
ス拡散層に接続さゼて、Ｍｏｓ容Ｊ＾１（並列する接合
容量を借成さ−げたことを／＋冒？２とする半導体（ｊ
♂積回路装置。This MOS $ By connecting the metal electrode of the elbow to the base diffusion layer, the semiconductor (J
♂ Product circuit device.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4081484A JPS60183762A (en) | 1984-03-02 | 1984-03-02 | Semiconductor integrated circuit device |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP4081484A JPS60183762A (en) | 1984-03-02 | 1984-03-02 | Semiconductor integrated circuit device |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPS60183762A true JPS60183762A (en) | 1985-09-19 |
Family
ID=12591115
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP4081484A Pending JPS60183762A (en) | 1984-03-02 | 1984-03-02 | Semiconductor integrated circuit device |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS60183762A (en) |
-
1984
- 1984-03-02 JP JP4081484A patent/JPS60183762A/en active Pending
Similar Documents
| Publication | Publication Date | Title |
|---|---|---|
| US3404321A (en) | Transistor body enclosing a submerged integrated resistor | |
| JPH02210860A (en) | Semiconductor integrated circuit device | |
| JPS60183762A (en) | Semiconductor integrated circuit device | |
| JPH01214055A (en) | Electrostatic breakdown protective device | |
| JPS58170062A (en) | Semiconductor device | |
| JPH01268049A (en) | Diffused resistor element | |
| JPH0656848B2 (en) | Lateral transistor | |
| JPH01194452A (en) | Integrated circuit device | |
| JPS601843A (en) | Semiconductor integrated circuit | |
| JPS6118344B2 (en) | ||
| JPS59127865A (en) | Semiconductor device | |
| JPH02240958A (en) | Semiconductor integrated circuit device | |
| JPS59130454A (en) | Semiconductor integrated circuit device | |
| JPH0440867B2 (en) | ||
| JPS60187048A (en) | Semiconductor device | |
| JPH0629466A (en) | Semiconductor integrated circuit | |
| JPH0432754Y2 (en) | ||
| JPH03155659A (en) | Semiconductor device | |
| JPH027553A (en) | Semiconductor integrated circuit device | |
| JPS6355223B2 (en) | ||
| JPH04112564A (en) | Semiconductor device | |
| JPH01268048A (en) | Diffused resistor element | |
| JPS6224659A (en) | Complex junction capacitor | |
| JPS62106663A (en) | Semiconductor device | |
| JPS59152666A (en) | Lateral transistor |