JPS5947755A - Semiconductor device - Google Patents

Semiconductor device

Info

Publication number
JPS5947755A
JPS5947755A JP15809382A JP15809382A JPS5947755A JP S5947755 A JPS5947755 A JP S5947755A JP 15809382 A JP15809382 A JP 15809382A JP 15809382 A JP15809382 A JP 15809382A JP S5947755 A JPS5947755 A JP S5947755A
Authority
JP
Japan
Prior art keywords
impurity diffusion
diffusion layer
ohmic electrode
electrode
metal electrode
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP15809382A
Other languages
Japanese (ja)
Inventor
Tomoyuki Watabe
知行 渡部
Fumio Nakazawa
中澤　文男
Koichi Yamazaki
幸一 山崎
Takahiro Okabe
岡部　隆博
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Hitachi Microcomputer System Ltd
Hitachi Ltd
Original Assignee
Hitachi Ltd
Hitachi Microcomputer Engineering Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hitachi Ltd, Hitachi Microcomputer Engineering Ltd filed Critical Hitachi Ltd
Priority to JP15809382A priority Critical patent/JPS5947755A/en
Publication of JPS5947755A publication Critical patent/JPS5947755A/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
    • H01L23/64—Impedance arrangements
    • H01L23/66—High-frequency adaptations
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Electrodes Of Semiconductors (AREA)
  • Semiconductor Integrated Circuits (AREA)

Abstract

PURPOSE:To reduce parasitic resistance of impurity diffusion layer and improve high frequency performance by arranging a capacitance element so that contact area of ohmic electrode to impurity diffusion layer is made large and an ohmic electrode surrounds metal electrodes. CONSTITUTION:A capacitance element has a structure that a metal electrode 5 and n- or p type impurity diffusion layer 3 are arranged face to face as the opposing electrodes, an insulating film 4 formed by SiO2, for example, is used as the dielectric material and an ohmic electrode 6 is formed around the metal electrode 5. The desired effect can be obtained by providing an ohmic electrode 6 to at least two side surfaces among three surfaces of rectangular metal electrode 5. Since an ohmic electrode of impurity diffusion layer is formed in such a way as surrounding metal electrode, parasitic resistance of impurity diffusion layer can be reduced and high frequency characteristic can be improved remarkably.

Description

【発明の詳細な説明】 本発明は半導体集積回路に訃ける容量素子の構造に係り
、特に高周波特性を改善した容−Ｗ素子に関するもので
ある。DETAILED DESCRIPTION OF THE INVENTION The present invention relates to the structure of a capacitive element used in a semiconductor integrated circuit, and particularly to a capacitive element with improved high frequency characteristics.

第１図（娼（１）］は従来の半導体集積回路に構成され
た標準的容量素子の平面図および断面図〔（ａ）におけ
るＡ−Ａ、’断面〕を示す。図に勢いて、１はｐ形（又
はｎ形）基板（シリコン基板）、２はｎ形（又はｐ形）
エピタキシャル層（シリコンエピタキシャル層）、３は
０１形（又はｐ＋形）不純物拡散層、４はＳ　＋　Ｏ□
等による絶縁膜、５は金属電極、６は不純物拡散層３の
オーミック電極、７はコンタクト孔である。この容量素
子は、不純物拡散層３と絶縁膜４と金属電極５とオーミ
ック電極６で構成されている。FIG. 1 (1) shows a plan view and a cross-sectional view [A-A, cross-section in (a)] of a standard capacitive element configured in a conventional semiconductor integrated circuit. is a p-type (or n-type) substrate (silicon substrate), 2 is an n-type (or p-type)
Epitaxial layer (silicon epitaxial layer), 3 is 01 type (or p+ type) impurity diffusion layer, 4 is S + O□
5 is a metal electrode, 6 is an ohmic electrode of the impurity diffusion layer 3, and 7 is a contact hole. This capacitive element is composed of an impurity diffusion layer 3, an insulating film 4, a metal electrode 5, and an ohmic electrode 6.

第２図は上記容量素子の等価回路図である。従来の構造
（第１図参照）では、不純物拡散層３のオーミック電極
６のコンタクト面積が小さいので、直列の寄生抵抗ｒが
大きくなり高周波性能が不充分であるという欠点があっ
た。FIG. 2 is an equivalent circuit diagram of the capacitive element. In the conventional structure (see FIG. 1), since the contact area of the ohmic electrode 6 of the impurity diffusion layer 3 is small, the series parasitic resistance r increases, resulting in insufficient high frequency performance.

本発明は上記の欠点を解消するためになされたもので、
不純物拡散層の寄生抵抗を低減させ、高周波性能が向上
した容量素子を提供することを目的とするものである。The present invention has been made to solve the above-mentioned drawbacks.
It is an object of the present invention to provide a capacitive element with improved high frequency performance by reducing the parasitic resistance of an impurity diffusion layer.

上記の目的を過酸するために、本発明の容量素子は、不
純物拡散層へのオーミック電極のコンタクト面積を太き
くシ、かつオーミック電極が金属電極周囲を取囲むよう
に配置して構成した。In order to achieve the above object, the capacitor element of the present invention is configured such that the contact area of the ohmic electrode to the impurity diffusion layer is large, and the ohmic electrode is arranged so as to surround the metal electrode.

以下、本発明を実施例によって説明する。Hereinafter, the present invention will be explained by examples.

第３図は本発明による一実施例の容量素子を示したもの
で、同図（ａ）は平面図、（ｂ）は（匈のＢ　−Ｂ　’
断面図である。この容座素子は、図に示したように金属
電極５とｎ　＋　　（又はｐ”）形不純物拡散層３を対
向電極とし、例えば５ｉ０２で形成した絶縁膜４を銹電
体とする構造であり、オーミック電極６を金属電極５の
周囲に形成したものである。なお、図では、矩形金属電
極５の３側面にオーミック電極６を設けた場合を示して
いるが、少なくとも２側面にオーミック電極６を設ける
ことにより所期の効果が得られる。凍だ、金属電極５の
形状が種々変形された場合も考えられるが、その２鴨合
には上記オーミック電極が不純物拡散ｌ−上に占める面
積の割合に準じて金属電極の周囲にオーミック電極を設
ければよい。FIG. 3 shows a capacitive element according to an embodiment of the present invention, in which (a) is a plan view and (b) is a (B-B'
FIG. As shown in the figure, this capacitor element has a structure in which a metal electrode 5 and an n + (or p'') type impurity diffusion layer 3 are used as opposing electrodes, and an insulating film 4 formed of, for example, 5i02 is used as a galvanic material. , an ohmic electrode 6 is formed around the metal electrode 5. Although the figure shows a case where the ohmic electrode 6 is provided on three sides of the rectangular metal electrode 5, the ohmic electrode 6 is provided on at least two sides. The desired effect can be obtained by providing the ohmic electrode 5.Although it is possible that the shape of the metal electrode 5 is variously deformed, the area occupied by the ohmic electrode on the impurity diffusion l- An ohmic electrode may be provided around the metal electrode according to the ratio.

以上説明したように、本発明によりば、金属電極の周囲
にそれを取囲むように不純物拡散層のオーミック電極を
形成しているので、第２図に示した直列抵抗ｒの原因と
なる不純物拡散層の寄生抵抗が低減でき、高周波性能が
大幅に改善できる効果がある。As explained above, according to the present invention, since the ohmic electrode of the impurity diffusion layer is formed around the metal electrode so as to surround it, the impurity diffusion that causes the series resistance r shown in FIG. This has the effect of reducing the parasitic resistance of the layer and significantly improving high frequency performance.

【図面の簡単な説明】[Brief explanation of the drawing]

第１１］ｔ１．従来の半λσ体集積回路に構成された容
量素子を示し２、回１．ｍ　（、＋１　ｒｊ平面図、（
１））は（ａ）の八−八′ｆと二かける断面図、第２図
ＱＪ第１１ｎ’′ｌに示した各層素子の等価回路図、第
３図Ｉｌｊ本発明による一実施例の容拐叱子を示し、同
図（ａ丹：ｌ：平角１図、（ｂ丹よ（３）のＢ−Ｂ′に
おける断面図である。 １・・・基板、２・・・エピタキシャル層、３・・・４
・細物拡散層、４・・・絶縁膜、５・・・くζ属電極、
６・・・オーミツ第　ｉ　図 （ａン 第２　図 第　３　区 （η〕11th] t1. 2 shows a capacitive element configured in a conventional half-λσ body integrated circuit. m (, +1 rj plan view, (
1)) is a cross-sectional view of 8-8'f and 2 in (a), an equivalent circuit diagram of each layer element shown in FIG. The same figure (a Tan: l: 1 flat view, (b Tanyo (3)) is a cross-sectional view taken along B-B'. 1...Substrate, 2...Epitaxial layer, 3 ...4
・Thin diffusion layer, 4... Insulating film, 5... Catalyst electrode,
6... Omitsu Figure i (A) Figure 2 Section 3 (η)

Claims (1)

【特許請求の範囲】[Claims] １、半導体基板上のｎ＋又はｐ＋形不純物拡散層と、該
不純物拡散層上の絶縁膜と金属電極を備えて成る容量素
子に訃いて、上記不純物拡散層とオーミックコンタクト
しているオーミック電極を上記金属電極の周囲の少なく
とも２側面に沿って設けたことを特徴とする半導体装］
ｄ、。1. A capacitive element comprising an n+ or p+ type impurity diffusion layer on a semiconductor substrate, an insulating film on the impurity diffusion layer, and a metal electrode, and an ohmic electrode in ohmic contact with the impurity diffusion layer as described above. A semiconductor device characterized by being provided along at least two sides around a metal electrode]
d.
JP15809382A 1982-09-13 1982-09-13 Semiconductor device Pending JPS5947755A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP15809382A JPS5947755A (en) 1982-09-13 1982-09-13 Semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP15809382A JPS5947755A (en) 1982-09-13 1982-09-13 Semiconductor device

Publications (1)

Publication Number Publication Date
JPS5947755A true JPS5947755A (en) 1984-03-17

Family

ID=15664143

Family Applications (1)

Application Number Title Priority Date Filing Date
JP15809382A Pending JPS5947755A (en) 1982-09-13 1982-09-13 Semiconductor device

Country Status (1)

Country Link
JP (1) JPS5947755A (en)

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4971924A (en) * 1985-05-01 1990-11-20 Texas Instruments Incorporated Metal plate capacitor and method for making the same
US5006480A (en) * 1988-08-08 1991-04-09 Hughes Aircraft Company Metal gate capacitor fabricated with a silicon gate MOS process
US6100591A (en) * 1998-05-25 2000-08-08 Nec Corporation Semiconductor device and method of fabricating the same

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4971924A (en) * 1985-05-01 1990-11-20 Texas Instruments Incorporated Metal plate capacitor and method for making the same
US5006480A (en) * 1988-08-08 1991-04-09 Hughes Aircraft Company Metal gate capacitor fabricated with a silicon gate MOS process
US6100591A (en) * 1998-05-25 2000-08-08 Nec Corporation Semiconductor device and method of fabricating the same

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