JPS5835981A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce an occupied area by shaping a load transistor and a drive transistor to a plurality of each Si layer forming an inverter circuit so as to be mutually stacked. CONSTITUTION:An n<+> layer 12 penetrating a p type substrate 11 is exposed and SiO2 22, 13 are formed, and an n layer 14 is stacked and an n layer 14' contacting with the p layer 11 in the window of the SiO2 13 and p layers 15 at both sides are shaped. A p layer 17 is stacked onto SiO2 16, a window thereof is bored onto the n layer 14', an n<+> layer 18 contacting with the n layer 14' and an n<+> source 19 separated from the layer 18 are molded to the window section, the surface is coated with SiO2 20 and a gate electrode 21 is formed, the MOS transistor TR1 for drive using the n<+> layer 18 as a drain and the junction type FET TR2 for load of an n<+> source 18, a p gate 15 and an n<+> drain are shaped, and the layer 12 is connected to a power supply VDD. With the inverter circuit by this constitution, the occupied area is reduced to approximately half conventional devices, and the degree of integration is increased without damaging characteristics.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly provides a semiconductor device having an inverter circuit suitable for high integration.

Conventionally, inverter circuits have been used very often in integrated circuits of semiconductor integrated devices, and these inverter circuits usually use load MO8) transistors.

FIG. 1 shows a cross-sectional structure of a semiconductor device having a conventional load MOS inverter circuit.

FIG. 2 is an equivalent circuit diagram of FIG. 1, and the same parts as in FIG. 2 are given the same numbers.

In these figures, 2, 3.4 are formed on a semiconductor substrate 1 of one conductivity type (for example, a p-type Si substrate), and 5.6 is an impurity diffusion region of the opposite conductivity type (n-type) to this semiconductor substrate. These are gate electrodes provided on semiconductor substrate 1 between impurity diffusion regions 2 and 3 and between impurity diffusion regions 3 and 4 via gate oxide films, respectively.

Here, the impurity diffusion regions 2 and 3 and the gate electrode 5 constitute one load transistor TR2, and similarly the impurity diffusion regions 3 and 4 and the gate electrode 6 constitute one driving transistor TR1.

In other words, this inverter circuit, as shown in Figure 1,
The impurity diffusion region 2 of the transistor TR2 is used as a drain, the impurity diffusion region 3 is used as a source, and the gate 6 and drain 2 are commonly connected to the drain power supply terminal vDD, thereby forming a load MO8 transistor. The impurity diffusion region 3 of one transistor TR1 is used as a drain, the impurity diffusion region 4 is used as a source, the source 4 is connected to ground, and the drain 3 is used as an output terminal,
Furthermore, by using gate 6 as an input terminal, the drive MOS
It constitutes a transistor.

A MOS inverter circuit is formed by the load MO8) transistor TR1 and the drive $oS transistor TR2.

However, in the conventional inverter circuit with the above structure, the load MO3) and the transistor TR2 are formed planarly on one main surface of the same semiconductor substrate as the drive MOS transistor TR1, so that the circuit is highly integrated. was being blocked. In other words, when trying to form a large number of inverter circuit elements at a high density, as long as a conventional planar arrangement is used, each inverter circuit occupies a large area, making it difficult to achieve a large degree of integration. It is.

The present invention eliminates the above-mentioned conventional drawbacks, and provides a semiconductor device having an inverter circuit that can achieve high density and high integration without reducing the dimensions of each inverter circuit.

That is, by arranging the transistors, which are the constituent elements of the circuit, in a direction perpendicular to the surface of the semiconductor substrate, the planar area occupied by the inverter circuit is significantly reduced compared to the conventional inverter circuit.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 is a sectional view of a main part of a semiconductor device according to an embodiment of the present invention, showing an inverter circuit with a laminated structure consisting of a plurality of semiconductor layers. , an n+ diffusion layer 12 extending from one principal surface to the other principal surface of this p-type substrate 11 is provided.
○The p-type substrate 11 is formed so that only this n'lt scattering layer 12 is exposed from one main surface of the p-type substrate 11.
An insulating film 22 is formed thereon. An insulating film 13 is formed on the other main surface of the p-type substrate 11 except for the n''4 region 12, and a second n-type semiconductor layer 14 is formed on this insulating film 13'. In this n-type semiconductor layer 14, an n-shaded region 14' is formed which contacts the n+ diffusion layer 12 through the opening of the insulating film 13, and further, the n-type semiconductor layer 14 excluding this n-shaded region 14' is formed in the n-type semiconductor layer 14. An insulating film 16 is formed on the top of the n+ diffusion layer 1 of the n-type semiconductor layer 14.
P expansion diffusion layers 16 are formed on both sides of 4'. Further, a third p-type semiconductor layer 17 is formed on the insulating film 16, and this p-type semiconductor layer 17 is in contact with the nt dispersion region 4' through the opening of the insulating film 16. A region 18 is formed. In addition, the p-type semiconductor layer 17 has n
An N1 scattering layer 19 is formed at a location a little apart from the boundary scattering layer 18, and an electrode 21 is formed between these N1 scattering layers 18 and 19 with an insulating film 2o serving as a surface protective layer interposed therebetween. has been done. The insulating film 20 has openings at the n+ diffusion layers 18 and 19, respectively.

In the semiconductor device having the above configuration, a transistor TR1i is formed using the n1 diffusion layer 19 as a source, the electrode 21 as a gate, and the n1 diffusion layer as a drain. On the other hand, n+ diffusion layer 18
A transistor TR2 is formed with the source + the pm diffused layer 15 as the gate, and the n''M diffused layer 12 as the drain. Note that TR1 is an MO8 type transistor, and TR2 is a junction field effect transistor.

Further, the drain electrode (n+ diffusion layer 12) of the transistor TR2 is connected to the power supply vDD, and the gate electrode (p diffusion layer 1
6) is applied with an appropriate potential. Further, the source electrode (n
By using the first loss layer 19) as the ground terminal, the gate electrode 21 as the input terminal, and the drain electrode (n+ diffusion layer 18) as the output terminal, an inverter circuit with the transistor TR2 as the load resistance and the transistor TR1 as the driving transistor is created. It is formed.

In the above embodiment, the transistor TR1 is formed as a junction field effect transistor in which the electric field of the n-diffusion layers 1 and 4', which serve as a channel, is controlled by changing the electric field by the voltage applied to the p-diffusion layer 16. It is also possible to form an MO8 type transistor with an insulating film interposed between the p-diffusion layer 16 and the channel (n-diffusion layer 14').

Further, in the above embodiment, the transistor TR2 is formed below the transistor TR1, but the second semiconductor layer 14 is provided on the third semiconductor layer 17, and the second
By providing the first semiconductor layer 11 on the semiconductor layer 14, it is also possible to form the transistor TR2 above the transistor TRI.

As is clear from the above embodiments, the semiconductor device of the present invention has a load transistor and a drive transistor formed in each of the plurality of semiconductor layers constituting the inverter circuit so as to overlap with each other. The area can be reduced to approximately i of the conventional one.

Furthermore, since the dimensions of each transistor are the same as those of the prior art, high integration of the integrated circuit in the semiconductor device can be achieved without any loss in characteristics.

As described above, the semiconductor device of the present invention can be highly integrated. It has high industrial utility value.

[Brief explanation of the drawing]

FIG. 1 is a sectional view of a main part of a conventional semiconductor device, FIG. 2 is an equivalent circuit diagram of the same device, and FIG. 3 is a sectional view of a main part of a semiconductor device according to an embodiment of the present invention. 11...First semiconductor layer, 12...n+
Diffusion layer (drain of load transistor), 13, 16°2o 22... Insulating film, 14... Second
semiconductor layer, 15... p diffusion layer (gate of load transistor), 17... third semiconductor layer, 1
8...n+ diffusion layer (drain of load transistor and sheath of drive transistor), 19...
・N+ diffusion layer (source of drive transistor), 21 ・
...Gate electrode (gate of drive transistor). Name of agent: Patent attorney Toshio Nakao and 1 other person 2nd
Figure DD Figure 3 Vo.

Claims (2)

[Claims] (1) The first through an insulating layer having an opening. A drive transistor is configured by stacking second and third semiconductor layers, forming a channel region, one electrode, and the other electrode in the first semiconductor layer, and forming one electrode in the first semiconductor layer and forming the other electrode in the first semiconductor layer. A load transistor is formed by forming a channel region in the second semiconductor layer and the other electrode in the third semiconductor layer, and the drive transistor and the load transistor are electrically connected through an opening in the insulating layer. A semiconductor device configured with an inverter circuit. (2) The semiconductor device according to claim 1, wherein one electrode of the drive transistor and one electrode of the load transistor are common.