JP2008010565A - Semiconductor device - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a semiconductor device employing a plurality of vertical organic transistors and exhibiting inverter characteristics. <P>SOLUTION: The semiconductor device is provided with a first electrode 21; first semiconductor layers 22, 24 on the first electrode 21; a third electrode 25 on the first semiconductor layers 22, 24; second semiconductor layers 26, 28 having the same conductivity type as that of the first semiconductor layers 22, 24, and provided on the third electrode 25; a fifth electrode 29 inserted between the second semiconductor layers 26, 28; a second electrode 23 inserted between the first semiconductor layers 22, 24; and a fourth electrode 27 inserted in the second semiconductor layers 26, 28. <P>COPYRIGHT: (C)2008,JPO&INPIT

Description

The present invention relates to a semiconductor device, and more particularly to a semiconductor device exhibiting inverter characteristics, characterized by using a plurality of vertical organic transistors.

  Conventionally, for example, a MOS (Metal Oxide Semiconductor) transistor is generally used as a field effect transistor (FET) in a device that requires high performance. On the other hand, a vertical transistor (SIT, Static Induction Transistor) has been proposed as a field effect transistor capable of flowing a large current and realizing a high operation speed.

FIG. 1 is a schematic cross-sectional view illustrating the operating mechanism of a vertical transistor (SIT). A vertical transistor generally has a structure in which a p + gate 103 is inserted in a semiconductor layer 104 sandwiched between an n + source electrode 101 and an n + drain electrode 102. When a voltage is applied to the p + gate electrode 103, a depletion layer (portion indicated by a dotted line) 105 extending from the p + gate 103 on both sides into the semiconductor layer 104 is just in contact with each other. When the gate voltage is small, it is turned on. In order to enter the off state, a negative voltage is applied between the p + gate 103 and the n + source electrode 101 to raise the potential level. That is, the current _Ids flowing between the n + source electrode 101 and the n + drain electrode 102 is determined by the potential applied by the p + gate 103 and the height of the potential barrier generated by the drain voltage _Vdr . A vertical transistor that operates in this manner is called a normally-on transistor, but can be formed to have a normally-off characteristic.

  Such a vertical transistor is a vertical type in which current flows in the vertical direction of the conductive layer, compared to a horizontal type in which current flows in the horizontal direction of the conductive layer, as compared with a field effect transistor such as MOS. The channel length, which is the current path, can be shortened to the thickness of the conductive layer, and the drain current can be increased, so that the transistor can be operated at high speed. In addition, the device structure is simple and the device size can be reduced.

  Since the vertical transistor has such characteristics, for example, when used as a control element (also referred to as a switching element) of a light emitting layer such as an organic EL layer, a display using the organic EL layer is used. Since the device is required to have high-speed response, it can be said that the device is more suitable than the lateral transistor.

  On the other hand, in recent years, it has been proposed to use organic materials in the field of electronics because of the need for weight reduction, portability, and flexibility. For this reason, various vertical transistors using organic materials have been proposed. .

Thus, by combining a transistor made of an organic material and a light emitting layer made of an organic material, a light emitting element in which both the light emitting layer and the control element of the light emitting layer are formed of an organic material can be realized (see Non-Patent Document 1). . In addition, as a vertical transistor using an organic semiconductor, a transistor in which CuPc (copper phthalocyanine) is sandwiched between a source electrode and a drain electrode and a slit-like aluminum thin film is embedded in a CuPc layer in a gate electrode has been reported ( Non-patent document 2). Moreover, as a light emitting element having an organic transistor, α-NPD (bis-1-Nnaphthyl N phenylbenzidine) is used as a hole transport material, and Alq ₃ (8-hydroxyquinolate aluminum complex compound) is used as a light emitting material. The performance of a vertical organic light emitting transistor in which a gate electrode is disposed in an α-NPD layer has been reported (see Non-Patent Document 3).
Thin Solid Films 331 (1998) 51-54 Kudo et al. IEEE Japan, Vol. 118-A, no. 10, (1998) P1166-1171 Ikegami et al., IEICE, OME2000-20, P47-51

  Thus, it has been found that the vertical organic transistor can be sufficiently used as a control element for a light emitting layer such as an organic EL layer. Currently, active research and development for realizing a flexible sheet display is underway. In order to realize a flexible sheet display, an element (logic element) that collectively controls individual transistors corresponding one-to-one to a light emitting layer as a light emitting layer control element is required.

  The present invention has been made in view of the above points, and an object thereof is to provide a semiconductor device that can exhibit inverter characteristics.

  In order to solve the above-described problems, the present invention is characterized by the following measures.

  The invention of claim 1 includes a first electrode, a first semiconductor layer on the first electrode, a third electrode on the first semiconductor layer, and a conductivity type of the first semiconductor layer. A second semiconductor layer on the third electrode having the same conductivity type, a fifth electrode on the second semiconductor layer, and a second electrode inserted in the first semiconductor layer, And a fourth electrode inserted in the second semiconductor layer.

  According to a second aspect of the present invention, the second electrode and the fourth electrode described in the second aspect are comb-shaped, mesh-shaped, or perforated plate-shaped.

  According to a third aspect of the present invention, the first semiconductor layer and the second semiconductor layer described in the first or second aspect are independently (1) naphthalene, anthracene, tetracene, pentacene, hexacene, and And (2) phthalocyanine compounds, azo compounds, perylene compounds, and derivatives thereof, and (3) hydrazone compounds, triphenylmethane compounds, diphenylmethane compounds, stilbene compounds, arylvinyl compounds , Pyrazoline compounds, triphenylamine compounds, triarylamine compounds, and derivatives thereof, and (4) poly-N-vinylcarbazole, halogenated poly-N-vinylcarbazole, polyvinylpyrene, polyvinylanthracene, pyreneformaldehyde Resin, ethyl cal Tetrazole formaldehyde resins, and modified compounds thereof, and (5) are those, wherein fullerenes, and in that it consists of at least one organic compound selected from the group consisting of carbon nanotubes.

  According to a fourth aspect of the present invention, the first electrode, the second electrode, the third electrode, the fourth electrode, and the fifth electrode described in any one of the first to third aspects are respectively Independently conductive metal oxide such as chromium, thallium, titanium, copper, aluminum, molybdenum, tungsten, nickel, gold, palladium, platinum, silver, tin, lithium, calcium, indium tin oxide, zinc oxide, conductive It contains at least one material selected from the group consisting of polyaniline, conductive polypyrrole, conductive polythiazyl, and conductive polymer.

  According to a fifth aspect of the present invention, the first power supply voltage is applied to the first electrode according to any one of the first to fourth aspects, and the input voltage is applied to the second electrode. The output voltage is taken out from the third electrode, and the second power supply voltage is applied to the fifth electrode.

  The invention according to claim 6 is characterized in that the second voltage is applied to the fourth electrode and the fifth electrode according to claim 5.

  The invention of claim 7 is characterized in that an output voltage is taken out from the third electrode and the fourth electrode described in claim 5.

  As described above, according to the present invention, it is possible to provide a semiconductor device exhibiting inverter characteristics using a plurality of vertical organic transistors.

  Next, the best mode for carrying out the present invention will be described with reference to the drawings.

  FIG. 2A is a cross-sectional view schematically showing a basic unit (vertical transistor single element) for explaining the vertical transistor according to the first embodiment of the present invention. FIG. 2A is a cross-sectional view taken along the line aa of the vertical transistor illustrated in FIG.

  In general, the vertical transistor shown in FIG. 2 includes a source region 3 that emits carriers, a drain region 5 that receives the carriers from the source region 3, and a gate electrode formed between the source region 3 and the drain region 5. 4 and so on.

  In the vicinity of the gate electrode 4, the material is configured to have Schottky junction at the interface with the material constituting the source region 3 and the drain region 5. The effect will be described later.

  A source electrode 2 electrically connected to the source region 3 and a drain electrode 6 electrically connected to the drain region 5 are provided, and the contact resistance is reduced and the source region 3 and the drain region 5 are efficiently connected. A voltage can be applied between them. In this case, it is preferable that the source electrode 2 and the drain electrode 6 are formed so as to face each other with the gate electrode 4 interposed therebetween.

  The source electrode 2 is made of a conductive material such as indium tin oxide (ITO) and is formed on the substrate 1. The substrate 1 is made of glass or the like, but is not limited thereto, and is formed using at least one material of plastic, quartz, undoped silicon, highly doped silicon, mica, and the like. In addition, as the plastic, polyethylene-based, polycarbonate-based, mylar-based, and polyimide-based materials are used.

  The source region 3 is formed on the source electrode 2 so as to cover the source electrode 2, a gate electrode 4 is formed on the source region 3, a drain region 5 is formed on the gate electrode 4, and A drain electrode 6 is formed on the drain region 5.

  FIG. 3 is a graph showing the height of the potential energy of carriers in the vertical transistor single element used in this example.

When a bias voltage (V _DS ) is applied between the source electrode 2 and the drain electrode 6, the potential energy of carriers can be expressed by a linear gradient (in the figure, S: from the source electrode 2 to D: the drain electrode 6). The dashed line). In this case, the inclination becomes steep when the voltage difference between the source electrode 2 and the drain electrode 6 is increased. On the other hand, when gradually added to the gate voltage V _G to the gate electrode 4, a depletion layer around the gate electrode 4 is gradually widened, the carrier (in the figure, indicated by black circles) energy barrier (saddle point potential) gradually increases with respect to ( growing.

In the vertical transistor, the amount of carriers moving from the source region 2 to the drain region 6 is controlled by controlling the increase / decrease in the saddle point potential due to the application of the bias voltage V _DS and the gate voltage V _G in this way. In this case, carriers move from the source region 2 to the drain region 5 through the gap of the gate electrode 4. Therefore, it is preferable to form a spatial gap in which carriers move in the gate electrode 4. For example, the gate electrode 4 is formed in a comb shape, and the carrier is depleted in the gap in the comb gate electrode. Move through an effective spatial gap. The gate electrode 4 is not limited to this shape, and can be used, for example, formed in a mesh shape or a porous plate shape.

  4A to 4C are plan views schematically showing an example of the shape of the gate electrode used in the vertical transistor. In these drawings, the gate electrode is viewed from the source electrode 2 or the drain electrode 6 side.

  First, in FIG. 4A, the gate electrode 74 is formed in a comb shape, and a path in which carriers move, that is, a current path 74a is formed in the gap between the comb electrodes.

  The gate electrode may be formed as shown in FIG. The gate electrode 84 shown in FIG. 4B is formed in a so-called mesh shape in which a plurality of conductors are combined so as to be orthogonal to each other, and carriers move to mesh eyes (holes). A current path 84a is formed.

  Further, the gate electrode may be formed as shown in FIG. The gate electrode 94 shown in FIG. 4C is formed in a so-called perforated plate shape, and has a shape in which a large number of current paths 94a through which hole-like carriers move are formed in a flat plate-like conductor. As described above, the gate electrode can be formed in various shapes, but each has a voltage application portion made of a conductive material to which a gate voltage is applied, and a current path adjacent to the voltage application portion. Is formed.

  The present invention is a combination of a plurality of vertical transistors having the above-described configuration, and the length of a channel (current path including the above 74a, 84a, 94a) which is a current path of a transistor adjacent to a gate electrode is set as a source region. 3 and the film thickness of the drain region 5. For this reason, it is possible to make the structure thin, to improve the operating speed by lowering the operating resistance, and to improve the current density.

  When the contact between the gate electrode 4 and the source region 3 and the drain region 5 is a Schottky contact, the source region 3 and the drain are utilized by utilizing the energy barrier (the height of the buttock potential) formed by the Schottky contact. The leakage current between the regions 5 can be reduced, and the response speed can be further improved by improving the on / off ratio.

  When the contacts between the source electrode 2 and the source region 3 and between the drain electrode 6 and the drain region 5 are ohmic contacts, the contact resistance is reduced and the characteristics of the transistor are improved.

  Source electrode 2, gate electrode 4, and drain electrode 6 are made of chromium (Cr), thallium (Ta), titanium (Ti), copper (Cu), aluminum (Al), molybdenum (Mo), tungsten (W), nickel (Ni), gold (Au), palladium (Pd), platinum (Pt), silver (Ag), tin (Sn), lithium (Li), calcium (Ca), conductive oxides such as ITO, and conductive It is made of at least one material selected from the group consisting of conductive polymers such as conductive polyaniline, conductive polypyrrole, and conductive polythiazyl. When the source electrode 2, the gate electrode 4, and the drain electrode 6 are made of the above materials, the contact resistance can be reduced to improve the electrical characteristics. These electrode materials are formed by a method selected from the group consisting of vapor deposition, sputtering, chemical vapor deposition, electrodeposition, electroless plating, spin coating, printing, and application.

  Further, at least one layer of a charge transport layer (or charge injection layer) (not shown) is provided at the electrode / semiconductor interface. This makes it possible to reduce the dipole between the electrode and the semiconductor interface, improve the charge injection efficiency from the electrode to the organic semiconductor layer, increase the on / off ratio of the vertical transistor, and further increase the current and increase the operation speed. It becomes possible.

The candidate materials for the charge transport layer (and charge injection layer) are: (a) at least one acene molecular material selected from naphthalene, anthracene, tetracene, pentacene, hexacene, and derivatives thereof; or (b) At least one pigment selected from copper phthalocyanine compounds (CuPc), azo compounds, perylene compounds, and derivatives thereof, or (c) hydrazone compounds, triphenylmethane compounds, diphenylmethane compounds, stilbenes Compounds, arylvinyl compounds, pyrazoline compounds, triphenylamine derivatives (TPD), triarylamine compounds, (2,2 ′, 7,7′-diphenylamino-spiro-9,9′bifluorene (Spiro- TAD), N, N-7-di-1-naphthyl-N, N′-diphe Nyl-4,4′-diamino-biphenyl (Spiro-NPB), 4,4 ′, 4 ″ -tris [3-methylphenyl- (phenyl) -amino] -triphenyl-amine (mMTDATA), 2,2 ′ , 7,7'-tetrakis (2,2-diphenylvinyl) spiro-9,9'-bifluorene (Spiro-DPVBi), 4,4 ', bis (2,2-diphenylvinyl) biphenyl (DPVBi), aluminum At least one low selected from trisoxyquinoline (Alq), 8-hydroxyquinoline aluminum (Alq ₃ ), tris (4-methyl-8-hydroxyquinolate) aluminum complex (Almq ₃ ), and derivatives thereof Molecular compound or (d) poly-p-phenylene vinylene (PPV), polymer having biphenyl group ( Biphenyl-Polymers), polymers having dialkoxy groups (Dialoxy-Polymers), alkoxy-phenyl-PPV, phenyl-PPV, phenyl-dialkoxy-PPV copolymers, poly (2-methoxy-5- (2′-ethyl-hexyl) Oxy) -1,4-phenylene vinylene) (MEH-PPV), PEDOT: poly (ethylenedioxythiophene) (PEDOT), polystyrene sulfonic acid (PSS), polyaniline (PANI), poly-N-vinylcarbazole, halogenated At least one polymer compound selected from poly-N-vinylcarbazole, polyvinylpyrene, polyvinylanthracene, pyreneformaldehyde resin, ethylcarbazole formaldehyde resin, and modified products thereof Or (e) a triphenylamine derivative (TPD), a triarylamine compound, (2,2 ′, 7,7′-diphenylamino-spiro-9,9′bifluorene (Spiro-TAD), N, N— 7-di-1-naphthyl-N, N'-diphenyl-4,4'-diamino-biphenyl (Spiro-NPB), 4,4 ', 4 "-tris [3-methylphenyl- (phenyl) -amino] -At least one low molecular weight compound selected from triphenyl-amine (mMDATA) and derivatives thereof, or (f) poly (ethylenedioxythiophene) (PEDOT), polystyrene sulfonic acid (PSS), polyaniline (PANI) and a material containing any one of at least one polymer compound selected from modified products thereof.

  Next, a method for manufacturing a vertical transistor according to this embodiment will be described. 5 (I) to (IX) will be described step by step.

  In the step shown in FIG. 5I, an electrode material is formed on the upper surface of the substrate 20 to form the source electrode 21 as the first electrode. For example, an ITO transparent electrode made of In oxide and Sn oxide is formed on the upper surface of a transparent 0.7 mm thick glass substrate (non-alkali glass 1737F manufactured by Corning) by RF sputtering, and the film thickness is 110 nm. A source electrode 21 is formed.

In the step shown in FIG. 5 (II), the source region 22 which is the first semiconductor layer is formed so as to cover the source electrode 21. For example, the pentacene layer is formed to a thickness of 60 nm by film formation by vacuum deposition under a vacuum condition of 1.3 to 3.9 × 10 ⁻³ Pa at room temperature, and the source region 22 is formed. .

In the step shown in FIG. 5 (III), a comb-shaped metal mask having a line and space of 20 μm each is disposed on the upper surface of the source region 22 and Al as the material of the gate electrode 23 as the second electrode is placed. At a room temperature of 6.5 × 10 ⁻³ Pa, the film is formed by vacuum deposition so that the film thickness is 30 nm.

In the step shown in FIG. 5 (IV), the pentacene layer is formed to a thickness of 70 nm by vacuum deposition at room temperature and 1.3 to 3.9 × 10 ⁻³ Pa under vacuum conditions. Then, the drain region 24 which is the first semiconductor layer is formed.

  In the step shown in FIG. 5V, an electrode material is deposited on the drain region 24 to form the drain electrode 25 as the third electrode. As the electrode material, Au is deposited to a thickness of 50 nm to form the drain electrode 25.

In the step shown in FIG. 5 (VI), the pentacene layer 26, which is the second semiconductor layer and the next source region layer, is formed on the drain electrode 25 at room temperature, 1.3 to 3.9 × 10 ^−3. The film is formed to a thickness of 70 nm by a film formation by a vacuum evaporation method under a vacuum condition of Pa.

Next, in the step shown in FIG. 5 (VII), the upper surface of the pentacene layer 26 becomes the second gate electrode 27 which is the fourth electrode. For example, the comb and the line and the space are each 20 μm. In this case, Al, which is the material of the second gate electrode 27, is deposited by vacuum deposition under a vacuum condition of 6.5 × 10 ⁻³ Pa at room temperature, resulting in a film thickness of 30 nm. Formed as follows.

In the step shown in FIG. 5 (VIII), the pentacene layer 28, which is the second semiconductor layer and the second drain region layer, is subjected to vacuum conditions at room temperature and 1.3 to 3.9 × 10 ⁻³ Pa. The film is formed so as to have a film thickness of 70 nm by film formation by vacuum evaporation.

  Finally, in the step shown in FIG. 5 (IX), the electrode material is Au with a thickness of 50 nm to form the drain electrode 29 as the fifth electrode.

  As a result, the vertical transistor having the structure shown in FIG. 6 is formed.

  FIG. 7 is a diagram showing the static characteristics of the pentacene vertical transistor. This vertical transistor has the basic unit (vertical transistor single element) structure shown in FIG. In this vertical transistor, the substrate 1 is made of a transparent 0.7 mm thick glass substrate (Corning non-alkali glass 1737F), the source electrode 2 is made of an ITO film, the source region 3 is made of pentacene, and the gate electrode 4 is made of Al. The drain region 5 is made of pentacene and the drain electrode 6 is made of Au under the conditions shown in FIGS. In the source-drain voltage range of 0V to -3V, a current of the order of several hundreds μA is well modulated in 0.2V steps by the gate voltage of 0.8V to -0.8V. The vertical transistor of FIG. 6 according to the present invention obtained in the device manufacturing process of FIGS. 5I to 5X is a stack of two vertical transistors having the electrical characteristics shown in FIG. It is.

Next, the result of examining the transfer characteristics of the inverter of the vertical transistor according to this example is shown in FIG. FIG. 9 shows the output voltage (V _out ) when the input voltage (V _in ) is changed within the range of −2V to 1V with respect to the power supply voltage (V _DD ) (supply voltage (V _supply )) − 1.2V. Relationship (transfer characteristics). When the input voltage (V _in ) is low, the drive-side vertical transistor operates, and as the input voltage (V _in ) gradually increases, the drive-side vertical transistor gradually turns off, and this time the load side As a result of the vertical transistor starting to operate, such characteristics are obtained. In this way, inverter operation is realized.

The transmission of the inverter shown in FIG. 9 was measured by configuring the circuits shown in FIGS. 8A and 8B. FIG. 8A shows a circuit configuration for realizing an inverter operation in which a first electrode is grounded, a comb-like, mesh-like or perforated plate-like second electrode is an input voltage (V _in ) terminal, Electrode is an output voltage (V _out ) terminal, a fifth electrode is a supply voltage (V _supply ) terminal, and a fourth electrode terminal in a comb shape, mesh shape or perforated plate shape is a supply voltage (V _supply ) terminal. Each of the five electrodes is electrically connected. FIG. 8B shows a circuit configuration for realizing an inverter operation in which a first electrode is supplied with a supply voltage (V _supply ) terminal, a comb-like, mesh-like, or porous plate-like second electrode is supplied with voltage. (V _supply ) terminal is commonly fixed to the first electrode, the third electrode is the output voltage (V _out ) terminal, the comb-like, mesh-like, or porous plate-like fourth electrode terminal is the input voltage (V _in ) terminal and the fifth electrode are electrically connected to the ground. As a result, the enhancement type drive / enhancement type load type inverter shown in the circuit diagram at the bottom of FIG. 8A can be realized. The output voltage can be determined by the content of the supply voltage by the equivalent resistance Rd of the load resistor RL and the transistor (transistor that becomes conductive by the input voltage), that is, the resistance ratio, and as shown in FIG. It was confirmed that the type transistor was operating normally.

In the vertical transistor according to the present invention shown in FIG. 7, the circuits shown in FIGS. 10A and 10B are configured. That is, in FIG. 10A, the first electrode is grounded, the comb-like, mesh-like or perforated plate-like second electrode is the input voltage (V _in ) terminal, and the third electrode is the output voltage (V _out ). The terminal, comb-like, mesh-like or perforated plate-like fourth electrode terminal is commonly fixed to the third electrode which is the output voltage (V _out ) terminal, and the fifth electrode is used as the supply voltage (V _supply ) terminal. Connect each one electrically. FIG. 10B shows a supply voltage (V _supply ) terminal for the first electrode, an output voltage (V _out ) terminal for the third electrode, and an output voltage for the second electrode in the shape of a comb, mesh, or porous plate. (V _out ) terminal is commonly fixed to the third electrode, and the comb-like, mesh-like or perforated plate-like fourth electrode terminal is electrically connected to the input voltage (V _in ) terminal and the fifth electrode is grounded. Connect.

FIG. 11 shows the result of examining the inverter transfer characteristics of the vertical transistor according to this example. Similarly, FIG. 11 shows the output voltage (V _out ) when the input voltage (V _in ) is changed within the range of −2V to 1V regarding the power supply voltage (V _DD ) (supply voltage (V _supply )) − 1.2V. ) Relationship (transfer characteristics).

A sharper conversion of the output voltage (V _out ) than the characteristics of the inverter transfer characteristics shown in FIG. 9 was observed. As a result, an enhancement type drive / depletion type load type inverter as shown in the circuit diagram at the bottom of FIG. 10A can be realized. In addition, it has been shown that higher speed operation is possible than the enhancement type drive / enhancement type load type inverter shown in FIGS. 8 (A) and (B).

  5 (I) to (IX), copper phthalocyanine was formed in place of pentacene to form source regions 22 and 26 and drain regions 24 and 28, respectively. Also in this case, the above-described transistor static characteristics were obtained.

  5 (I) to (IX), in place of pentacene, α-NPD (bis-1-N naphthyl N phenylbenzidine) is formed to form source regions 22 and 26 and drain regions 24, respectively. 28 were formed. Also in this case, the above-described transistor static characteristics were obtained.

  5 (I) to (IX), fullerene was formed in place of pentacene to form source regions 22 and 26 and drain regions 24 and 28, respectively. Also in this case, the above-described transistor static characteristics were obtained.

  In the steps shown in FIGS. 5I to 5X, gate electrodes 23 and 27 were formed using Pt instead of Al. In this case as well, the above-described transistor static characteristics were obtained.

  5 (I) to (IX), gate electrodes 23 and 27 were formed using Au instead of Al. In this case as well, the above-described transistor static characteristics were obtained.

  5 (I) to (IX), the source electrode 21 and the drain electrodes 25 and 29 were formed using ITO or ZnO instead of Au. In this case as well, the above-described transistor static characteristics were obtained.

  5 (I) to (IX), the source electrode 21 was formed using conductive polyaniline instead of ITO. Also in this case, the above-described transistor static characteristics were obtained in the same manner.

  8A and 8B and FIG. 10A are also applied to the vertical transistors shown in Embodiments 3 to 9 as in the case of the vertical transistors described in Embodiments 1 and 2. ) And (B) were used to measure the transfer characteristics of the inverter. As a result, almost the same measurement results were obtained, and it was confirmed that the same effects as those of Example 1 and Example 2 were obtained.

  The vertical transistors according to the present invention described in the first to tenth embodiments are organic inverter devices having a structure in which a plurality of (two) vertical transistors are sequentially stacked as described above. The transfer characteristics of the inverter were obtained even in a configuration in which a plurality of basic unit (vertical transistor single element) vertical transistors shown in FIG. 2 are arranged adjacent to each other on the same substrate without being stacked.

  The present invention is not limited to the specifically disclosed embodiments, and various modifications and embodiments are possible without departing from the scope of the claimed invention. For this reason, the above-described embodiments are merely examples in all respects and should not be interpreted in a limited manner. The scope of the present invention is indicated by the scope of claims, and is not restricted by the text of the specification.

  The present invention relates to a vertical transistor having high carrier mobility, steep rising and falling waveforms of output voltage, and high operating speed, and an inverter device and a circuit configuration using a plurality of vertical transistors. Of course, it is possible to realize a logic element product using an organic transistor.

It is a schematic sectional drawing explaining the operation mechanism of a vertical transistor (SIT). (A) is a schematic sectional view of a vertical transistor that is the basis of the present invention, and is an aa sectional view of the vertical transistor shown in (B). FIG. 3 is a diagram showing carrier potential energy of the vertical transistor of FIG. 2. (A)-(C) are top views which show the example of the shape of a gate electrode. (I)-(IX) is a figure which shows the manufacturing method of the inverter apparatus by this invention. It is sectional drawing of the inverter apparatus by this invention. It is a figure which shows the static characteristic of a pentacene vertical transistor. (A) And (B) is the connection diagram of the inverter apparatus by this invention, and is the figure shown with the circuit. It is the transfer characteristic of the inverter apparatus by this invention which comprised and measured the circuit shown to FIG. 8 (A) and (B). (A) And (B) is the connection diagram of another inverter apparatus by this invention, and is the figure shown with the circuit. 10 is a transmission characteristic of another inverter device according to the present invention, in which the circuit shown in FIGS. 10A and 10B is configured and measured.

Explanation of symbols

1, 20 Substrate 2, 21 Source electrode 3, 22 Source region 4, 23 Gate electrode 5, 24 Drain region 6, 25 Drain electrode 26 Pentacene layer 27 Second gate electrode 28 Pentacene layer 29 Drain electrodes 74, 84, 94 Gate electrode 74a, 84a, 94a Current path 101 n + source electrode 102 n + drain electrode 103 p + gate 104 Semiconductor layer 105 Depletion layer

Claims (7)

A first electrode;
A first semiconductor layer on the first electrode;
A third electrode on the first semiconductor layer;
A second semiconductor layer on the third electrode having the same conductivity type as the first semiconductor layer; and
A fifth electrode on the second semiconductor layer;
A second electrode inserted in the first semiconductor layer;
And a fourth electrode inserted into the second semiconductor layer.   The semiconductor device according to claim 1, wherein the second electrode and the fourth electrode have a comb shape, a mesh shape, or a perforated plate shape.   The first semiconductor layer and the second semiconductor layer are each independently (1) naphthalene, anthracene, tetracene, pentacene, hexacene, and derivatives thereof, and (2) phthalocyanine compounds, azo compounds, and perylene systems. Compounds, and derivatives thereof, and (3) hydrazone compounds, triphenylmethane compounds, diphenylmethane compounds, stilbene compounds, arylvinyl compounds, pyrazoline compounds, triphenylamine compounds, triarylamine compounds, And their derivatives, and (4) poly-N-vinylcarbazole, halogenated poly-N-vinylcarbazole, polyvinylpyrene, polyvinylanthracene, pyreneformaldehyde resin, ethylcarbazole formaldehyde resin, and modifications thereof And (5) the fullerene, and a semiconductor device according to claim 1 or 2, characterized in that it consists of at least one organic compound selected from the group consisting of carbon nanotubes.   The first electrode, the second electrode, the third electrode, the fourth electrode, and the fifth electrode are each independently chromium, thallium, titanium, copper, aluminum, molybdenum, tungsten, nickel, gold, palladium At least one selected from the group consisting of conductive metal oxides such as platinum, silver, tin, lithium, calcium, indium tin oxide, zinc oxide, conductive polyaniline, conductive polypyrrole, conductive polythiazyl, and conductive polymer The semiconductor device according to claim 1, comprising a seed material.   A first power supply voltage is applied to the first electrode, an input voltage is applied to the second electrode, an output voltage is extracted from the third electrode, and the fifth electrode The semiconductor device according to claim 1, wherein a second power supply voltage is applied to the electrode.   The semiconductor device according to claim 5, wherein the second voltage is applied to the fourth electrode and the fifth electrode.   6. The semiconductor device according to claim 5, wherein an output voltage is extracted from the third electrode and the fourth electrode.

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