JPS5835979A - Semiconductor device - Google Patents

Abstract

PURPOSE:To reduce the plane occupied area of an FET by arranging source and channel drain regions to each Si layer laminated through an insulating layer. CONSTITUTION:The SiO2 22 with an opening 33, an N type Si layer 23, SiO2 24 opposite to the opening 33 and a P type Si layer 25 are laminated onto a P type Si layer 21. An N<+> layer 26 is formed near the window 33 of the P layer 21 and used as a source electrode 30, and an N<+> layer 29 is shaped near the window 34 of the P layer 25 and employed as a drain electrode. P layers 27, 28 are formed to the N layer 23, and used as the gate electrode 34. A semiconductor layer is shaped through a CVD method, and the insulating layer is obtained through oxidation treatment or the evaporation of an insulator. According to this constitution, the FET can be arranged at high density.

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a semiconductor device, and particularly provides a semiconductor device having a transistor suitable for high integration.

MOB is the most commonly used MOB for semiconductor integrated circuits.
As shown in FIG. 1, a type transistor has a source diffusion region 2 and a drain diffusion region 3 disposed two-dimensionally on the entire surface of a semiconductor substrate 1. A gate 6 is arranged between the diffusion region 3 and the insulating film 4 on substantially the same plane as these regions,
The current flowing through the current path between the source electrode e and the drain electrode 8 formed corresponding to the source diffusion region 2 and the drain diffusion region 3 is applied to the gate electrode 7 applied to the substrate electrode 9. It is controlled to be in a conductive state or a non-conductive state by voltage.

Furthermore, as another conventional example, there is a single FET type transistor as shown in FIG. This transistor has a channel region 13 in which impurities of the opposite conductivity type are diffused on the entire surface of a semiconductor substrate 10 of one conductivity type, and a source diffusion region in which impurities of the same type as the channel region 13 are diffused at a high concentration. 11 and the drain diffusion region 12 are formed separately,
A gate region 14 is formed by diffusing high concentration impurities of the same conductivity type as the channel region 13 between these regions, and tooth electrodes 16 are formed corresponding to the source diffusion region 11 and the drain diffusion region 12, respectively. The current flowing through the current path between the drain electrodes 17 is controlled to be in a conductive state or a non-conductive state by a voltage applied to the gate electrode 16 with respect to the substrate electrode 18.

In each of the conventional transistors, a source diffusion region, a gate region, and a drain diffusion region are arranged in a plane on one main surface side of a semiconductor substrate, so that each transistor occupies a large area. In order to reduce the area occupied by transistors, various efforts have been made to reduce the dimensions of various parts, but there is a limit to increasing the degree of integration from this point alone.

For example, using photolithography technology with a dimensional accuracy of 2μ at the current state of the art, the source, region, and drain/region are each 6×6μ2. Gate area is 5μ wide
, the length is about 2μ, and the area occupied by one transistor is about 60μ2.

The present invention has been made in order to further increase the integration of conventional transistors.The present invention has been made in order to further increase the degree of integration of conventional transistors. In addition, the planar area occupied by the transistor is reduced and the integration of the semiconductor device is increased.

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 3 shows a sectional view of essential parts of a semiconductor device according to an embodiment of the present invention. The semiconductor device has a stacked structure consisting of a plurality of semiconductor layers, and a part of the main surface of the semiconductor layer 21 is exposed above the first semiconductor layer 21 (for example, p-type). Forming a first insulating layer (or a high resistance layer with a specific resistance of 100 sub or more) 22 having an opening 33,
A second semiconductor layer 23 (for example, n-type) is formed on this insulating layer 22, a second insulating layer (or high resistance layer) '24 is further formed on this semiconductor layer 23, and A third semiconductor layer 26 (for example, p-type) is formed on layer 24.

Further, an impurity diffusion region 26 (for example, n+ impurity) is formed in the first semiconductor layer 21 near the opening 33 of the first insulating layer 22, and this is used as the source electrode 30. Similarly, in the third semiconductor layer 25, there is an impurity diffusion region 29 (for example, n+ impurity) near the opening 34 of the second insulating layer 24.
is formed, and this is used as the drain electrode 31. moreover,
The second semiconductor layer 23 includes the impurity diffusion regions 26 and 2.
Impurity diffused gate regions 27 and 28 (for example, p-type) to which a voltage is applied to control the conductivity of the region 32 between the regions 9 and 9 are formed, and these are used as gate electrodes 34.

In a semiconductor device having such a structure, a current flowing from the source electrode 3o to the drain electrode 31 through the current path (region 32) is controlled to be in a conductive state or a non-conductive state by a voltage applied to the gate electrode 34.

In this example, in order to control the current flowing through the current path (region 32), impurity diffusion gate regions are placed on both sides of the current path, and a voltage is applied to the impurity diffusion gate regions to control the current. Alternatively, an insulating film may be provided between the current path (region 32) and the impurity diffusion gate region t#7, and a voltage may be applied to the current path through this insulating film. In addition, the first and second insulating layers 22 and 24 may be subjected to oxidation treatment, vapor deposition of an insulator, etc.! It can be formed with. Furthermore, when each semiconductor layer 21, 23.25 is made of silicon, the first and second insulating layers 22.
24 can be formed.

Further, each semiconductor layer 21, 23, 25 is formed by vapor phase growth (CVD).
) method, vapor deposition method, or the like. Semiconductor layers formed by vapor deposition have low carrier mobility;
It is crystallized by electron beams, laser beams, etc., and has a mobility comparable to that of a single crystal.

The semiconductor device having the above structure has a stacked structure in which semiconductor layers are stacked. In other words, since each semiconductor layer has a three-dimensional arrangement structure in which a source region, gate region, and drain region are formed, the area occupied by each element is reduced compared to conventional planar semiconductor devices. Can be made smaller. For example, if we use photolithography technology with a dimensional accuracy of 2μ and make the source region and drain region each about 6μ x 6μ, the area occupied by 21 troughs will be 5μ x 5μ or about 26μ2. , in the conventional case (
60μ2), the degree of integration on the plane of the semiconductor substrate is 2
It will be about double.

FIG. 3 shows a sectional view of essential parts of a semiconductor device according to another embodiment of the present invention. In this embodiment, the semiconductor device of the previous embodiment shown in FIG. 3 is further multilayered. That is, in addition to each layer of the semiconductor device shown in FIG. 3, a semiconductor layer 41 and an insulating layer 42 are added. semiconductor layer 41
Impurity diffusion gate regions 43 and 44 are formed to surround a region 46 serving as a current path, and these are used as gate electrodes 46. The other parts are the same as the semiconductor device shown in FIG.

In a semiconductor device having such a configuration, a current path is formed from the source electrode 30 through the regions 32 and 45 to the drain electrode 3.
1, the current flowing through each different gate electrode a4.4
The conductive state and non-conductive state are controlled by the voltage applied to 5.

Even when the semiconductor device of this embodiment is multilayered, the occupied area does not increase and is the same as the case of FIG. 3. Note that the thickness of each semiconductor layer and insulating layer is extremely small compared to the dimension in the direction of the main surface, so even if the device is multilayered, the thickness of the device only increases slightly.

As described above, in the semiconductor device of the present invention, the source, gate, and drain are formed in each of the plurality of semiconductor layers so as to overlap with each other, so that the planar area occupied by the transistor can be significantly reduced compared to the conventional one. Furthermore, since the dimensions of each part of the transistor are the same as those of the conventional transistor, no deterioration of characteristics occurs.

As described above, since the semiconductor device of the present invention allows transistors to be arranged at high density, it can be highly integrated and has high industrial utility value.

[Brief explanation of drawings]

1 and 2 are sectional views of main parts of a semiconductor device having a conventional transistor, FIG. 3 is a sectional view of main parts of a semiconductor device according to an embodiment of the present invention, and FIG. 4 is a sectional view of main parts of a semiconductor device according to another embodiment of the present invention. 1 is a sectional view of a main part of a semiconductor device in an example. 21 23 25 41 --- Semiconductor layer, 22
゜24.42... Insulating layer, 26... Impurity diffusion region (source region), 27, 28, 43, 44
... Impurity diffusion gate region, 29 ... Impurity diffusion region (source region) 0 Name of agent Patent attorney Toshio Nakao and 1 other person 1st
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Claims (1)

[Claims] stacking at least a first second and third semiconductor layer through an insulating layer having an opening, forming a source region in the first semiconductor layer, and forming a gate region in the M2 semiconductor layer; forming a drain region in the third insulating layer;
A semiconductor device including a transistor in which the source region, gate region, and drain region are electrically connected through an opening in the insulating layer.