JP3061907B2 - Semiconductor device and manufacturing method thereof - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor device and a method of manufacturing the same, and more particularly to a semiconductor device having a single-gate electrode and a double-channel thin film transistor and a method of manufacturing the same.

[0002]

2. Description of the Related Art Many conventional thin film transistors use amorphous silicon as an active layer. However, amorphous silicon has lower electron mobility and lower operation ON current than crystalline silicon or polysilicon.
For this reason, there have been examples in which a circuit is driven by a plurality of transistors, a transistor structure having a large channel width, or a transistor structure having a double channel structure is used.

Further, the yield of the manufacturing process of the thin film transistor is not high, and the thin film transistor has many defects. For this reason, there is a case where a pair of transistors is redundantly provided.

[0004] Such a conventional thin film transistor includes:
The use of a plurality of transistors and a transistor having a large channel width increases the occupied area, which is disadvantageous for a high-definition circuit.

On the other hand, in the case of a thin film transistor having a double channel structure as shown in FIG. 3, the gate electrode is doubled, and the first layer gate electrode 31 and the second layer gate electrode 3 are formed.
2 can form upper and lower double channels in the amorphous silicon active layer 11 via the silicon nitrides 12 and 14. Therefore, the ON current could be increased while keeping the occupied area smaller than that of the planar double transistor. The gate electrode 31 and the source / drain electrode 18 had a structure having an overlap. The overlap distance w 'is usually 3 to 5 μm. This is because not only the accuracy of the patterning process but also the ON current can be easily obtained with the overlap.

However, such a gate electrode and a source
In a thin film transistor having an overlapped structure with a drain electrode, there has been a problem that the electric field is concentrated between the gate and the source / drain, or the thin film transistor is damaged by an electric field caused by sudden electrostatic application.

[0007] Therefore, as in the case of the thin film transistor shown in FIG. 4, although the structure of the offset between the gate electrode and the source and drain electrodes are considered, simply release the inter-electrode
Since the the offset, it is difficult to prevent and takes no offset distance w than 3μm corruption above. However, when the offset distance is set to 4 to 5 μm for safety, there is a problem that the ON current becomes one digit smaller than the desired ON current.

[0008]

As described above, in the conventional double channel thin film transistor, the gate and the source
There are many defects between the drains, and there is a problem that it is difficult to obtain an ON current when an offset distance is set to prevent the destruction. In addition, the structure and manufacturing
There was also a problem that it was difficult to obtain a method.

[0009]

According to the present invention, a first amorphous silicon semiconductor layer is provided on a substrate, and a first insulating film is provided on the first amorphous silicon semiconductor layer. A gate electrode on the first insulating film, and contacts the first insulating film on the gate electrode at an end of the gate electrode;
A second insulating film connected to the second insulating film;
And a source / drain electrode electrically connected to the first amorphous silicon semiconductor layer and the second amorphous silicon semiconductor layer, wherein the source / drain electrode is at least
The first amorphous silicon half from the gate electrode end.
Between the conductor layer and the second amorphous silicon semiconductor layer
A semiconductor device characterized in that it does not overlap with the portion up to the connection portion is obtained.

Further, according to the present invention, a first amorphous silicon semiconductor layer is provided on a substrate, a first insulating film is provided on the first amorphous silicon semiconductor layer, and the first insulating film is provided. A gate electrode, a second insulating film on the gate electrode, and a second amorphous silicon semiconductor layer on the second insulating film and on a peripheral portion of the first amorphous silicon semiconductor layer. The end of the gate electrode
The first amorphous silicon semiconductor layer and the second amorphous silicon semiconductor layer.
To the connection with the amorphous silicon semiconductor layer
Is not less than 0.5 μm and not more than 3 μm .

Furthermore, according to the present invention, the first substrate is provided on the substrate.
Forming a first semiconductor layer; and forming a first semiconductor layer on the first semiconductor layer.
Forming a second insulator film on the gate electrode and the first insulator film, forming a second insulator film on the first insulator film, forming a second insulator film on the first insulator film, Etching the first insulating film and the second insulating film, excluding the region including the gate electrode, to expose the first semiconductor layer; and forming a second insulating film on the second insulating film and the first semiconductor layer. Thus, a method for manufacturing a semiconductor device including a step of forming two semiconductor layers and a step of forming a source electrode and a drain electrode on the second semiconductor film is obtained.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

FIG. 1 is a sectional view of a thin film transistor showing one embodiment of the present invention.

Amorphous silicon (a-Si) is laminated on a transparent insulating substrate 10 such as glass by plasma CVD, and the first layer a-Si film 11 is patterned as a first active layer. Next, silicon nitride (SiN) is similarly stacked by plasma CVD to form a first-layer SiN film 12 serving as a first gate insulating film. Next, a chromium (Cr) film is laminated by sputtering, and the gate electrode 13 is patterned. Next, SiN is stacked by plasma CVD, and the offset distance w from the gate electrode end is set to 0.
Patterning the opening of the source / drain electrode portion having 5 μm through the first layer SiN and the second layer SiN film;
The first layer a-Si film is exposed. in addition,
A-Si is laminated by plasma CVD, and a second layer a-S
The i-film 15 is patterned as a second active layer, so that the second layer a-Si film is bonded to the first layer a-Si at the opening. Further, SiN is laminated on the upper layer by plasma CVD, and a third SiN film 16 is formed as a passivation film.
Are patterned by opening the source / drain electrode portions. Thereafter, the n ⁺ a-Si film 17 is formed by plasma CVD.
Then, a Cr film is laminated by sputtering, and the source / drain electrodes 18 are patterned.

The first and second layers a-Si films 11 and 15 are structured by the above-described lamination order and patterning.
As a result, a thin film transistor in which the channel can be formed double by the single gate electrode 13 is obtained.

In the thin film transistor having such a structure, there is no overlap w ' between the gate electrode 13 and the source / drain electrodes 18, and it is possible to prevent electric field concentration and destruction due to static electricity. Also, unlike the conventional case, the offset width w
Open the source / drain electrodes of the insulating film from the gate electrode end.
The offset distance between electrodes defined by the distance to the end of the mouth
The ON voltage of the thin film transistor
The current can be set to 10 ⁻⁷ A necessary for driving the circuit .

Next, thin film transistors having basically the same structure as described above but having variously changed offset distances were produced. As a result of evaluating the ON current of the thin film transistor using the offset distance as a parameter, a result as shown in FIG. 2 was obtained.

According to FIG. 2, if the offset distance is 3 μm or less, an ON current of 10 ⁻⁷ A can be obtained, and the level can be set to a level at which the circuit can be driven.

That is, as compared with the conventional thin film transistor, the offset distance can be made smaller and the structure can be more resistant to destruction. The advantages of the double channel structure can be fully utilized.

[0020]

As described above, according to the present invention,
There is an effect that a sufficient ON current can be obtained even if an offset distance for reducing the destruction defects between the source and the drain and preventing the destruction is set.

Further, the offset distance is set to 0.5 μm or more and 3
By setting the thickness to μm or less, a highly reliable semiconductor device having improved breakdown resistance and sufficient ON current can be obtained.

Further, according to the manufacturing method of the present invention, a thin film transistor having a double channel structure can be manufactured with a single gate electrode, and there is an effect that the breakdown resistance and the yield of the product are improved.

[Brief description of the drawings]

FIG. 1 is a sectional view showing one embodiment of a thin film transistor according to the present invention.

FIG. 2 is a characteristic diagram of an embodiment of a thin film transistor according to the present invention.

FIG. 3 is a cross-sectional view showing a conventional thin film transistor.

FIG. 4 is a cross-sectional view showing a conventional thin film transistor.

[Explanation of symbols]

Reference Signs List 10 substrate 11 first layer amorphous silicon film 12 first layer silicon nitride film 13 gate electrode 14 second layer silicon nitride film 15 second layer amorphous silicon film 16 third layer silicon nitride film 17 N ⁺ type amorphous silicon film 18 source Drain electrode 31 First layer gate electrode 32 Second layer gate electrode W Gate length w Offset distance w 'Overlap width

Claims (3)

(57) [Claims] A first amorphous silicon semiconductor layer on the substrate; a first insulating film on the first amorphous silicon semiconductor layer; and a gate electrode on the first insulating film. Forming a first insulating film on the gate electrode;
A second insulating film connected at an end of the gate electrode, a second amorphous silicon semiconductor layer on the second insulating film, the first amorphous silicon semiconductor layer and the second amorphous silicon semiconductor a layer and the source and drain electrodes electrically connected the source-drain conductive
The pole is at least from the gate electrode end to the first
Rufus silicon semiconductor layer and the second amorphous silicon
A semiconductor device, which does not overlap with a portion up to a connection portion with a recon semiconductor layer . 2. The first amorphous semiconductor device according to claim 1, wherein said first amorphous electrode extends from said gate electrode end.
Silicon semiconductor layer and the second amorphous silicon
The distance to the connection with the semiconductor layer is 0.5 μm or more and 3 μm.
2. The semiconductor device according to claim 1, wherein m is equal to or less than m . 3. A step of forming a first semiconductor layer on a substrate, a step of forming a first insulating film on the first semiconductor layer, and forming a gate electrode on the first insulating film. And forming a second insulating film on the gate electrode and the first insulating film, and exposing portions of both ends of a portion of the first semiconductor layer under the gate electrode. Process and
Forming a second semiconductor layer on the second insulating film and the first semiconductor layer; and forming a source electrode and a drain electrode on the second semiconductor layer. A method for manufacturing a semiconductor device.