JPS58170064A - Manufacture of thin film field effect transistor - Google Patents

Abstract

PURPOSE:To improve the operating speed of a TFT circuit and to enable to microminiaturize and integrate an element by self-aligning a gate electrode with source and drain electrodes. CONSTITUTION:A gate electrode 12 is formed by sputtering and patterning of A in thickness of 1,000Angstrom on a transparent glass substrate 11, and an oxidized silicon film 13 of 3,000Angstrom thick is then formed by sputtering as a transparent gate insulating film. Subsequently, an amorphous silicon film 15a of approx. 1,000Angstrom is accumulated by the glow discharge of SiH4. An amorphous silicon film 14 is formed in the prescribed pattern. Then, a positive type resist 16 is coated in approx. 1.2mum, ultraviolet ray is exposed with the electrode 12 as a mask from the back surface of the substrate 11, a development is performed, and the resist 16 is patterned. After Mo 15b is deposited in approx. 500Angstrom on the resist and Al 15c is deposited in approx. 500Angstrom , the resist 16 is then removed. Wirings out of the source and drain regions of an element are eventually formed in the desired pattern, thereby completing a TFT.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical field to which the invention pertains] The present invention describes a method of manufacturing nine field effect transistors using four semiconductor films.

[Conventional ML# and electrical point between]

In 2013, Takabatake transistors (Tl'T) made of amorphous semiconductors (C) have been attracting attention. In particular, the semiconductor thin film mentioned above can be formed at low temperature.
R has the advantage that it is not limited to the substrate used to construct the thin semiconductor #& filter, and that pattern forming methods such as conventional exposure technology and etching technology can also be used in many cases. Finally, semiconductor devices with a wide variety of structures can be realized depending on the purpose. In order to fully demonstrate the functions of the semiconductor device using these semiconductor thin films, a TjFI't formed by the above semiconductor device is provided as a switching element or an active circuit element within the same substrate.
many.

FIG. 41 and FIG. 2 are diagrams schematically showing two basic structures of a conventional TPT. In these figures, 1 is the substrate, 2 is the semiconductor material, 4 is the gate insulator, 3 is the gate insulating film, 4 is the gate electrode, and 5-6 are the north terminals, respectively.
Binyin gold electrode. The one in Figure 1 is a semiconductor 4g2
Gate electrode 4. on the same side of the gate electrode 4. A source IIE electrode 5 and a drain electrode 6 are provided, and the one in FIG.
A gate electrode 4 is provided on the lower surface of the electrode, and a north electrode 5 and a drain polarization 6 are provided on the upper surface. These TF'r are #! It exhibits electrical characteristics similar to the so-called MO8Fg'r using F crystal 7-lipun, but the fundamental difference in operating principle from MO8FBT is that (4) the condition for interrupting the channel of the transistor is PN 11 in 8FgT. In contrast, TPT utilizes the high resistance of the semiconductor 11fi2, whereas TPT utilizes the reverse direction characteristic of the semiconductor 11fi2. The conduction state of the channel both utilizes the inversion or carrier accumulation of the semiconductor IIEI due to one field effect. Therefore, these Tl'T are 41
In order to achieve this, the resistance at the non-conducting portion of the semiconductor 1 and 2 must be seven times higher than the resistance at the time of channel formation.

Now, these TI'r are unique in amorphous semiconductors at 0, when the mobility of holes in electrons, which serve as carriers, is lower than that of polycrystalline or amorphous semiconductors. . For this reason, using a crystalline semiconductor material, 9ff8FgT
Compared to this, the operating frequency limit of TPT is considerably lower. Nine, like this, Ti? For a 16m T integrated on a substrate, its operating train will generally be much slower than the operating frequency limit mentioned above. this is,
This is mainly caused by a time delay due to parasitic capacitance due to the wiring and the four transistors. In TPT, an insulating substrate can be used, so it is easy to avoid parasitic interference between the wiring and the substrate. In the case of 4dl, the influence of one parasitic capacity is large due to the weight t of the electrode between the north gate or between the drain and gate. In general, parasitic capacity III
In order to increase the operating speed of the circuit including TI'r with TI'r, it is necessary to lower the resistance in the ON state of Tn. ) needs to be increased. In this case, in the conventional structure of TFvr, the parasitic capacitance also has channel width: ζ
Since it increases proportionally, the operating speed t does not essentially improve.

[Purpose of the invention]

In view of the above-mentioned point, the present invention aims to improve the operating speed (f) of the TPT circuit by self-aligning one gate pole and one north drain, and enables TPT circuits to be miniaturized and integrated.
It provides a manufacturing method for.

The first and second purposes are to reduce the contact resistance of the North 1 drain solder electrode and improve its characteristics.

[Summary of the invention]

In the present invention, a fixed putter is printed on the substrate.
＠+blood is passed through the gate insulation layer, and the north-drain electrode is passed through the gate insulation layer, and four resistor semiconductor films are deposited thereon. The 4&s substrate and the gate insulation film are made of transparent materials, and the gate is made of an opaque material.Then, a low resistance medium 4Iil which serves as north-drain polarization is formed.This north-drain quadrupole is Using the I! element from the substrate AIjj, the gate is self-aligned to the pole and patterned. That is, a resist is applied on the top of the gate # and the gate # is patterned as a gold mask from the board protection surface using a photo-etching process. Then, IJ imaged this, and the low-resistance medium 4-body film was set to the 4I self-pole and was buttered as the 9-north I drain wire.

〔Effect of the invention〕

$,! According to @Ming, the parasitic capacitance between the gate tfM and the north-drain is small and high! ! Not only is the operation simple, but it is also possible to miniaturize the circuit and increase the size of the circuit, and it is also possible to make good ohmic contact using a low-resistance semiconductor thin film.

[Central example IIa of the invention]

First, an embodiment of the present invention will be described with reference to FIGS. 1a to 1e. First, the thickness of the a-light glass substrate 11 is 10 mm.
Goo due to sputtering and buttering of OK bottom) (
12 was formed, and then sputtered with a thickness of 3 o'oox as an f1 #4 gate tank model.
Amorphous silicon film 15a of about xooooX is deposited on the grain by glow-spraying SiH4. Amorphous silicon yr@14 is formed into a predetermined pattern. Next is a positive type instrument (Hefely AZ13
50J) 16 to about 1.2. am j −) L, conductive plate 1
1'? ) Using the backside gate area 112 as a mask 'C$4
#: The resist 16 is patterned by being exposed to light and developed. On top of this, remove the resist 16 after applying approximately 5ooXtsb and Ae total of approximately 25ooKtsc.
I am busy completing 'rF'r by forming the connecting part into the desired pattern.

Although conductive films such as global warming silicon and indium-tin oxide films are transparent, the amorphous silicon film described above can also transmit light spectroscopy. That is, the spectral sensitivity range of a normal positive resist is less than soooXm degrees, but ~3ooo'A
- If we use amorphous silicon, we can improve the optical contrast (we were able to expose the resist to light). In order to obtain a good ohmic contact, it is sufficient that the low resistance layer has a thickness of 30 to xooooX, and therefore, a low resistance layer can be formed with excellent resistance. Furthermore, since the thickness of the channel is several orders of magnitude or less, it is sufficient that the thickness of the high-resistance semiconductor 4 pattern is between 100 and 2000 times.

As is clear from the above explanation, according to the present invention, the direct second part between the north T drain ((ii) and the gate voltage can be almost eliminated, so the parasitic capacitance between these electrodes can be minimized, and Tl The operating speed of the 'T circuit can be significantly improved.Also, the north-1 drain (gate polarization) can be easily gate polarized (self-aligned) by exposure from the surface of the substrate using the gate electrode as a mask. Therefore also'
It is possible to miniaturize the rFvrl path elements and increase their II[I integration.

Furthermore, it is possible to make good ohmic contact between the north drain electrode and the semiconductor thin film in the channel region.

However, the present invention is not limited to the above-mentioned example. For example, 14b is 1ooOXIll! It is possible to expose the resist through the semiconductor 41 layer. Amorphous semiconductor thin II 14b is less than 1 longer than Si, and contains
Sil, #st.

It may be a compound such as CI-X, and furthermore, a semiconductor thin film such as Cd8pZn8eeZn8 having a high specific resistance,
These polycrystalline semiconductors 4- such as multiple 6st may be used.

Further, the gate insulating material may be made of 8l, N, or other transparent insulators, and the gate electrode may be made of any opaque material.

[Brief explanation of drawings]

Figures 1 and 2 are cross-sectional views of TPT with conventional structure;
Figures (a) to (6) are diagrams showing the manufacturing process of TFvl' in one example of this @beak. In the figure, 11・"a'147'/? x, t z-! -to 41i (AI), 13... gate insulating film, 14...
-Bird resistance amorphous silicon film, 15t...Low resistance amorphous silicon film, 15b...Mo, 15c...Aj%
151... Nance electric kettle, 152... Drain electrode,
15... Regis) membrane. Agent: Patent attorney: Yu Chikasa (and 1 other person) Figure l Figure 2

Claims (1)

[Claims] A process of forming a gate electrode on a transparent substrate and forming a gate insulating film to cover the gate electrode, and then forming a high resistance semiconductor, a low resistance semiconductor thin film to serve as a north layer, a drain/electrode, and a resist film on top of the gate electrode. This process comprises a step of forming a horizontal layer in this one ridge, and a step of buttering the impurity-doped semiconductor thin film by self-assembling the gate tliK by 7t etching exposed from the back side of the process layer plate. A method for manufacturing effect transistors is a thin fusuma electric current modeled on ¥f.