JP2956380B2 - Thin film transistor array and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor array having an inverted staggered channel using amorphous silicon, and more particularly to a thin film transistor array used as a driving element of an active matrix liquid crystal display.

[0002]

2. Description of the Related Art FIG. 5 is a longitudinal sectional view showing the structure of a conventional thin film transistor array. In a conventional thin film transistor array, a metal such as aluminum, chromium, or tantalum is formed on a glass substrate 301 constituting an insulating substrate by a sputtering method, and a gate electrode 302 is formed and patterned by a method of photolithography and wet etching. . Next, a gate insulating layer (1) in which silicon nitride (100 nm) and a silicon oxide film (300 nm) are stacked
309 (400 nm) and an amorphous silicon film (3
(00 nm) and a gate insulating layer (2) 310 formed of an n-type amorphous silicon film (60 nm) doped with phosphorus are continuously formed in a vacuum by a plasma CVD method.

Next, an amorphous silicon semiconductor layer 303 is formed by processing an n-amorphous silicon film of amorphous silicon into stripes by the method of photolithography and dry etching, and the same applies to the gate insulating layer (1) 309. A contact hole for connecting an electrode is formed by the method described above. After that, a metal such as aluminum, chromium, or the like is formed again on these, and the wiring of the source electrode 305 and the drain electrode 306 is patterned by photolithography.

Then, the n-amorphous silicon film remaining on the amorphous silicon semiconductor layer 303 for forming a channel is removed by dry etching (hereinafter referred to as channel etching) to protect the last dug channel. A silicon nitride film is formed as a passivation film 308 by a plasma CVD method, and a contact hole for connecting an electrode is formed by a photolithography method.

[0005]

In the above-mentioned conventional thin film transistor array, the gate insulating layer is doubled in order to prevent interlayer short-circuit at the intersection of the gate electrode and the source and drain electrodes or to protect the gate electrode. . Therefore, the thickness of the gate insulating layer in the transistor portion is increased, the characteristics of the transistor are degraded, and interface states and charge traps are easily generated in the gate insulating layer.

An object of the present invention is to provide a thin film transistor array capable of improving operating characteristics and stability by reducing the thickness of a gate insulating layer and eliminating a complicated interface. .

[0007]

According to the present invention, there is provided a semiconductor device comprising a gate electrode, a gate insulating layer, an amorphous silicon semiconductor layer processed in a strip shape, an ohmic contact layer, a source and a drain electrode which are sequentially laminated and patterned on an insulating substrate. In the thin film transistor array formed by etching the ohmic contact layer in the channel portion, laminating a passivation film, and further patterning, the gate insulating layer on the gate electrode is formed of a first material.
A structure formed by laminating a second insulating film on the insulating film, and <br/> the lower portion of the amorphous silicon semiconductor layer before
It is characterized in that it has a single-layer structure of only the second insulating film .

[0008] The gate insulating layer having the multilayer structure may be formed in a laminated structure of an insulating film including at least a silicon nitride film, and the silicon nitride film may be in contact with the amorphous silicon semiconductor layer.

[0009]

The effective mobility of a thin film transistor greatly depends on the dielectric constant and the film thickness of the gate insulating layer, and its operational stability is also greatly related to impurities in the gate insulating layer, the level of structure formation, and traps. In the present invention, the gate insulating layer on the gate electrode is made a single layer for a portion where the amorphous silicon semiconductor layer which is an operation part of the transistor is to be formed , and the gate insulating film layer is thinned to form a complicated interface. Not to have. Thereby, operation characteristics and stability can be improved.

[0010]

Next, an embodiment of the present invention will be described with reference to the drawings.

(First Embodiment) FIG. 1 is a longitudinal sectional view showing the structure of a first embodiment of the present invention.

In the first embodiment of the present invention, a metal chromium (100 nm) is formed on a low alkali glass substrate 101 having a thickness of about 1 mm.
m) is formed by a sputtering method, and is processed into a predetermined pattern by a method of photolithography and wet etching to form a gate electrode 102. Next, a silicon oxide film (150 nm) was formed on the glass substrate 10 by sputtering.
After deposited and formed on one entire surface, forming a photolithography and the gate insulating layer a silicon oxide film is removed portion that will be formed of an amorphous silicon semiconductor layer 103 by a dry etching technique (1) 109.

Further, a silicon nitride film (300 nm) and an amorphous silicon film (30 nm) are formed by plasma CVD.
0 nm) and an n-amorphous silicon film (60 nm) is continuously formed in a vacuum. The silicon nitride film becomes the gate insulating layer (2) 110. Next, the amorphous silicon film and the n-amorphous silicon film are processed into a predetermined pattern on the gate electrode 102 and a necessary portion thereof by photolithography and dry etching to form an amorphous silicon semiconductor layer 103. A contact hole for connecting an electrode is formed in a predetermined position of the layer (1) 109 by a method of photolithography and dry etching.

On top of this, a metal chromium film (20
0 nm) is formed by a sputtering method, and processed into a predetermined pattern by a method of photolithography and dry etching to form a source electrode 105 and a drain electrode 106. Next, the n-amorphous silicon film remaining on the amorphous silicon semiconductor layer 103 for channel formation is removed by about 150 nm by dry etching using the source electrode 105 and the drain electrode 106 as a mask. The n-amorphous silicon film remaining under the source electrode 105 and the drain electrode 106 becomes the ohmic contact layer 107.

Finally, a silicon nitride film is formed by plasma CVD as a passivation film 108 for protecting the dug channel, and then contact holes for connecting electrodes are formed at predetermined positions by photolithography. .

FIG. 3 shows the operation characteristics of the thin film transistor array according to the first embodiment of the present invention. In the thin film transistor array according to the present invention, since the gate insulating layer is a single layer and is thin, favorable transistor array characteristics with higher mobility than in the conventional example can be obtained. FIG. 4 shows the shift amount of the threshold voltage when a ± 30 V stress voltage is applied to the gate. It can be seen that the operation stability of the transistor according to the present embodiment is improved as compared with the conventional example.

(Second Embodiment) FIG. 2 is a longitudinal sectional view showing the structure of a second embodiment of the present invention.

In the second embodiment of the present invention, a metal chromium (100 nm) is formed on a low alkali glass substrate 201 having a thickness of about 1 mm.
m) is formed by a sputtering method, and is processed into a predetermined pattern by a method of photolithography and wet etching to form a gate electrode 202. Further, a silicon nitride film (300 nm) and an amorphous silicon film (100 nm) are continuously formed in a vacuum by a plasma CVD method. The silicon nitride film becomes the gate insulating layer (1) 209.

Next, the amorphous silicon film is processed into a predetermined pattern on the gate electrode 202 and other necessary parts by a method of photolithography and dry etching to form an amorphous silicon semiconductor layer 203. A silicon nitride film (200 nm) is formed thereon again by a plasma CVD method, and a contact hole for connecting the gate electrode 202 and the amorphous silicon semiconductor layer 203 is opened by a photolithography and dry etching method to form a gate insulating layer (2). Form 210. Further, the amorphous silicon semiconductor layer 20 is formed by ion implantation using the gate insulating layer (2) 210 as a mask.
3 is doped with phosphorus to form an ohmic contact layer 20.
7 is formed. A metal chromium film (2
(00 nm) is formed by a sputtering method and processed into a predetermined pattern by a method of photolithography and dry etching to form a source electrode 205 and a drain electrode 206, and further a passivation film 208 is formed.

In the second embodiment, since there is no channel engraving step and the thickness of the amorphous silicon can be reduced, the operation characteristics can be further improved.

[0021]

According to the present invention as described in the foregoing, the lower portion of the amorphous silicon semiconductor layer is an operation portion of the gate insulating layer of the thin film transistor array transistor
For the to be configured to a single layer, with the thickness of the gate insulating layer, it is possible to eliminate a complicated interface, there is an effect that it is possible to improve the operating characteristics and stability.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view showing a configuration of a first embodiment of the present invention.

FIG. 2 is a longitudinal sectional view showing the configuration of a second embodiment of the present invention.

FIG. 3 is a characteristic curve diagram of a current with respect to a gate voltage of a thin film transistor array showing an effect in the embodiment of the present invention.

FIG. 4 is a characteristic curve diagram of a threshold voltage change amount with respect to a gate stress application voltage of a thin film transistor showing an effect in the embodiment of the present invention.

FIG. 5 is a longitudinal sectional view showing a configuration of a conventional example.

[Explanation of symbols]

101, 201, 301 Glass substrate 102, 202, 302 Gate electrode 103, 203, 303 Amorphous silicon semiconductor layer 105, 205, 305 Source electrode 106, 206, 306 Drain electrode 107, 207, 307 Ohmic contact layer 108, 208, 308 Passivation film 109, 209, 309 Gate insulating layer (1) 110, 210, 310 Gate insulating layer (2)

Continuation of the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) H01L 29/786 H01L 21/336 G02F 1/136 500

Claims (3)

(57) [Claims] 1. A gate electrode, a gate insulating layer, an amorphous silicon semiconductor layer processed in a stripe shape on an insulating substrate,
After the ohmic contact layer, the source and the drain electrodes are sequentially laminated and patterned, the ohmic contact layer in the channel portion is removed by etching, a passivation film is laminated, and further patterned to form a thin film transistor array. The gate insulating layer is the first insulating film
It has a structure in which a second insulating film is laminated thereon , and the lower part of the amorphous silicon semiconductor layer is the second insulating film .
Thin film transistor array, characterized in that a single-layer structure of only an insulating film. 2. The multi-layered gate insulating layer is formed in a laminated structure of an insulating film including at least a silicon nitride film, and the silicon nitride film is in contact with the amorphous silicon semiconductor layer. Thin film transistor array. Forming a gate electrode of a predetermined pattern on an insulating substrate; forming a first insulating film on the gate electrode and on the insulating substrate; and forming the first insulating film on the gate electrode. Ammo membrane
The part where the Rufus silicon semiconductor layer is to be formed
A step of stomach removed, further the second gate insulating film and the amorphous silicon semiconductor film and the n ⁺ ammo on said first gate insulating film
Forming a Rufasu silicon semiconductor film, the n ⁺ Amorphous silicon semiconductor film and said amo
By the etching the Rufasu silicon semiconductor film interest or like
And forming a pattern, the n ⁺ Method of manufacturing a thin film transistor array which comprises a step of forming a source electrode and a drain electrode, an amorphous silicon semiconductor film as an ohmic contact layer.