JP2919369B2 - Liquid crystal display device and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a liquid crystal display device and a method of manufacturing the same, and more particularly, to an active matrix type liquid crystal display device and a method of manufacturing the same.

[0002]

2. Description of the Related Art An active matrix type liquid crystal display device has a thin film transistor (TFT) as a switching element for each pixel. Since the thin film transistor can be formed of amorphous silicon (a-Si), it is inexpensive and large. A display device having an area can be realized. FIG.
A conventional active matrix type liquid crystal display device will be described with reference to FIG. FIG. 4A is a plan view, and FIG.
FIG. 4A is a cross-sectional view taken along the line aa ′, and FIG. 4C is a cross-sectional view of the TFT portion of FIG. As shown in FIG.
The TFT 19 is formed between the source electrode 16 and the drain electrode 15 connected to the transparent pixel electrode 17, and is switched by the potential of the gate electrode 11. The details will be described below with reference to FIGS. 4B and 4C.

First, a Cr film is formed on a glass substrate 10 by a sputtering method, and a gate electrode 11 is formed by photolithography. Next, plasma chemical vapor deposition (P-CV)
D), SiN, amorphous silicon, and N ⁺ type amorphous silicon are sequentially deposited to form the gate insulating layer 12,
An I-type amorphous silicon layer 13 and an N ⁺ -type amorphous silicon layer 14 are stacked. Next, the predetermined pattern of the N ⁺ -type amorphous silicon layer 14 is removed by dry etching, and the I-type amorphous silicon layer 13 having the same pattern is removed except for a necessary portion. Further, thereafter, the gate insulating layer 12 is removed by dry etching in a predetermined pattern (not shown) for conduction with the gate electrode 11 and the drain electrode 15 at the peripheral terminal portion and the like by dry etching. At this time, the recess 2 is formed by simultaneously etching and removing the gate insulating layer 12 between the electrode formation region and the drain electrode formation region.

[0004] Next, Cr, Mo-Ta, Al or A
A single layer or multilayer structure such as 1 / Ta is formed and patterned to form the source electrode 16 and the drain electrode 15. Next, ITO is deposited by sputtering and patterned to form a transparent pixel electrode 17. Further, the N ⁺ type amorphous silicon layer 14 is formed by dry etching.
Then, a channel is dug in the I-type amorphous silicon layer 13, and a TFT protective film 18 is formed thereon. Thus, an active matrix type liquid crystal display device is completed (for example, refer to Japanese Patent Application Laid-Open No. 7-199223).

As described above, in the prior art, when a contact is formed in the gate insulating layer 12 by dry etching, the gate insulating layer 12 in a predetermined pattern portion between the drain electrode 15 and the pixel electrode 17 is simultaneously removed by etching. By doing so, even if the amorphous silicon residue due to the poor patterning of the amorphous silicon layer in the previous step is between the drain electrode 15 and the pixel electrode 17 or between the adjacent pixel electrodes 17, the number of steps is not increased.
This can be removed by etching.

[0006]

As described above, in the prior art, the concave portion is formed by removing the gate insulating layer 12 between the drain electrode 15 and the pixel electrode 17 by dry etching. However, this concave portion is formed in the subsequent step of forming the drain electrode 15 and the source electrode 16 and the pixel electrode 17.
There is a problem that dust and liquid pools are liable to be generated in the process of forming the film, thereby causing a residue of each film to be generated and causing a short circuit.

An object of the present invention is to provide a liquid crystal display device and a manufacturing method capable of preventing a short circuit between a signal wiring (drain electrode wiring) and a pixel electrode and a short circuit between a signal wiring and a signal wiring.

[0008]

SUMMARY OF THE INVENTION The present invention comprises a step of forming a gate insulating layer on a glass substrate, a step of forming a signal wiring on a gate insulating layer in a signal wiring area, and a step of forming a gate insulating layer in a pixel electrode forming area. Forming a pixel electrode on the layer; and forming an insulating protective layer for protecting the signal wiring and the pixel electrode layer. A step of half-etching a portion of the gate insulating layer to form a step higher than the pixel electrode forming region and the signal wiring region in the gate insulating layer around the pixel electrode forming region and the signal wiring region.

Further, according to the present invention, a liquid crystal display device in which a step higher than the pixel electrode and the signal wiring is formed in the gate insulating layer around the pixel electrode and the signal wiring is obtained.

According to the above-described present invention, even when an amorphous silicon etching residue exists on a gate insulating layer between a signal wiring and a pixel electrode or between adjacent pixel electrodes, the etching residue is simultaneously etched and removed. In addition, in the case where the signal wiring is left unetched and the pixel electrode is left unetched, the etching property is improved due to the step of the gate insulating layer, and the short circuit between the signal wiring and the pixel electrode can be prevented.

[0011]

Next, the present invention will be described in detail with reference to the drawings. 1A and 1B show an embodiment of the present invention. FIG. 1A is a plan view, and FIG.
1 (a) is a sectional view taken along line aa 'of FIG.
It is a sectional view taken on line b '. FIGS. 2A to 2G are cross-sectional views taken along the line cc 'of FIG. 1A in accordance with the manufacturing process.

Hereinafter, the manufacturing method will be described with reference to FIGS.
This will be described in detail with reference to FIG. First, a 2000 mm thick transparent glass substrate 10 having a thickness of 1.1 mm was sputtered.
An Angstrom Cr film is formed. Since this Cr film serves as a gate electrode, a thickness of 10
It must be at least 00 Å. Next, the gate electrode 11 is formed by patterning to predetermined dimensions by photolithography (FIG. 2A).

Next, plasma chemical vapor deposition (P-CV)
D) A 5000 angstrom thick SiN,
A 4000 Å thick amorphous silicon and a 1000 Å thick N ⁺ type amorphous silicon are sequentially deposited, and a gate insulating layer 12, an I type amorphous silicon 13 and an N ⁺ type amorphous silicon 14 are laminated. Then, N ⁺ type amorphous silicon 1 is formed by photolithography and dry etching.
4, the I-type amorphous silicon 13 is patterned into a predetermined size to form a semiconductor layer (FIG. 2B).

Next, the gate insulating layer 12 having a predetermined size is removed by photolithography and dry etching for conduction with a drain electrode 15 and a source electrode 16 to be described later at peripheral terminals and the like (not shown). . next,
The gate insulating layer 12 below the drain electrode formation region and the pixel electrode formation region, which will be described later, is patterned into predetermined dimensions by photolithography and dry etching to form the projections 1. At this time, the step due to the dry etching at the time of forming the convex portion 1 of the gate insulating layer 12 is set to 3000 angstroms to be smaller than the step of the I-type amorphous silicon 13 (FIG. 2C).

Next, a 2,000 angstrom thick Cr film is formed by sputtering and patterned to predetermined dimensions by photolithography to form a drain electrode 15 and a source electrode 16 (FIG. 2D). The thickness of the drain electrode 15 and the source electrode 16 is
For the same reason as the film thickness. Next, an ITO film having a thickness of 500 angstroms is formed by a sputtering method, and is patterned to a predetermined size by photolithography to form a transparent pixel electrode 17 (FIG. 2E). Next, channel etching of the N ⁺ type amorphous silicon 14 and the I type amorphous silicon 13 is performed by dry etching. The channel excavation amount is set to 2000 Å in consideration of the remaining film of the I-type amorphous silicon (FIG. 2).
(F)).

Next, plasma chemical vapor deposition (P-CVD)
A 2,000 angstrom thick SiN film is formed by the method. Thereafter, the TFT protection layer 18 is formed by patterning to a predetermined size by photolithography (FIG. 2).
(G)). Thereby, the active matrix type liquid crystal display device of the present invention is completed.

Next, the operation of the liquid crystal display device according to the embodiment of the present invention will be described in detail with reference to FIG. First,
The gate insulating layer 12 formed on the glass substrate 10 is shown in FIG.
As shown in FIG. 3A, a convex shape is formed by dry etching.
Here, the reason why the gate insulating film 12 is patterned in a convex shape is, for example, to remove the amorphous silicon residue by dry etching when the amorphous silicon residue is present. In addition, for example, when the Cr residue and the ITO residue 20 after the formation of the convex portion exist as shown in FIG. 3B, the convex corner portion has a property that the upper layer film is formed thinly. This is because the Cr residue and the ITO residue are self-etched and removed from thin portions of the film as in (C) and (D).

In the above embodiment, the gate electrode,
Although the drain electrode and the source electrode were formed of Cr,
Not only that, the gate insulating film may have a single-layer or multilayer structure of Al, Mo-Ta, Al / Ta, etc., and may have a single-layer or multilayer structure of SiO, SiO / SiN, etc., in addition to SiN. It is also possible.

[0019]

As described above, according to the present invention, the gate insulating layer 12 under the drain electrode 15 and the pixel electrode 17 is formed.
Is half-etched, and the drain electrode 15 and the pixel electrode 1 are
Since the convex portion 1 is formed while leaving the gate insulating layer 12 around 7, the etching property is improved, and amorphous silicon,
Short circuit due to Ca and ITO residue can be prevented.

The reason is that the amorphous silicon residue is removed when the convex portion 1 of the gate insulating layer 12 is formed,
This is because the remaining portions of r and ITO are preferentially etched due to the effect of reducing the film thickness at each corner of the convex portion 1, and a short circuit due to the remaining film between the drain electrode 15 and the pixel electrode 17 can be prevented. .

[Brief description of the drawings]

FIGS. 1A to 1C are a plan view and a cross-sectional view of an embodiment of the present invention.

FIGS. 2A to 2G are cross-sectional views illustrating a manufacturing process of the present invention.

FIGS. 3A to 3D are cross-sectional views illustrating the operation of the present invention.

FIGS. 4A to 4C are a plan view and a sectional view showing a conventional example.

[Explanation of symbols]

DESCRIPTION OF SYMBOLS 1 Convex part 2 Concave part 10 Glass substrate 11 Gate electrode 12 Gate insulating layer 13 I type amorphous silicon 14 N ⁺ type amorphous silicon 15 Drain electrode 16 Source electrode 17 Transparent pixel electrode 18 TFT protective layer 20 Upper layer film

──────────────────────────────────────────────────続 き Continued on the front page (58) Field surveyed (Int.Cl. ⁶ , DB name) G02F 1/136 G02F 1/1343 G02F 1/1333 G02F 1/13 101 G09F 9/30 H01L 29/78

Claims (2)

(57) [Claims] 1. A forming a gate insulating layer on a glass substrate, and half-etching the underlying gate insulating layer of the pixel electrode formation region and the signal wiring region to a portion remaining Suyo, pixel electrode formation region and the signal wiring region Forming a step in a gate insulating layer around the step, forming a signal wiring in a region of the signal wiring region surrounded by the gate insulating layer, and forming a step in the pixel electrode forming region surrounded by the gate insulating layer. Forming a pixel electrode layer on the liquid crystal display device. 2. In a liquid crystal display device having a gate insulating layer on a glass substrate and having a pixel electrode and a signal wiring on the gate insulating layer, a pixel electrode is provided on the gate insulating layer around the pixel electrode and the signal wiring. And a step formed higher than the signal wiring.