CN100449716C - Thin film transistor and manufacturing method thereof - Google Patents
Thin film transistor and manufacturing method thereof Download PDFInfo
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- CN100449716C CN100449716C CNB200610068203XA CN200610068203A CN100449716C CN 100449716 C CN100449716 C CN 100449716C CN B200610068203X A CNB200610068203X A CN B200610068203XA CN 200610068203 A CN200610068203 A CN 200610068203A CN 100449716 C CN100449716 C CN 100449716C
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Abstract
The present invention relates to a thin film transistor which is provided with two polycrystalline silicon layers lapped up and down as a channel region. A manufacturing method of the present invention is as follows: firstly, a first polycrystalline silicon layer is formed above a base plate; secondly, a first insulating layer, a gate metal layer and a second insulating layer are orderly formed above the first polycrystalline silicon layer; a second polycrystalline silicon layer is formed above the second insulating layer; then, a part of first insulation layer and the second insulation layer are removed to form two contact holes; finally, a metal level is formed in each contact hole to electrically connect the first polycrystalline silicon layer and the second polycrystalline silicon layer.
Description
Technical field
The present invention system is about a kind of thin-film transistor and manufacture method thereof, particularly about a kind of thin-film transistor and manufacture method thereof of double channel.
Background technology
Active organic electro-luminescent display drives Organic Light Emitting Diode with thin-film transistor and comes display frame.Organic Light Emitting Diode is the luminescence component of current drives.Therefore, when the current density that drives Organic Light Emitting Diode is changed, its brightness also is changed simultaneously.The current density (double current densities) that some active organic electro-luminescent display employing dual-channel film transistor provides twice is selected so that more brightness to be provided, and need not be increased the area that circuit is laid to Organic Light Emitting Diode.
Please refer to Fig. 1, is pixel cell wiring (layout) figure of an active organic electro-luminescent display.Pixel cell 100 comprises assemblies such as one scan line 102, a data wire 104, a switching transistor 106, a driving transistors 108, a power line 110, an Organic Light Emitting Diode 112 and an electric capacity 114.The electrical connection of said modules is known by the technical staff, does not repeat them here.What deserves to be mentioned is that driving transistors 108 has double channel, its section please refer to Fig. 2.
Please refer to Fig. 2, is the profile of driving transistors 108.Two raceway grooves 1084 and 1085 that driving transistors 108 has one source pole metal 1081, a drain metal 1082, a gate metal 1083 and is overlapped in gate metal 1083.Raceway groove 1084 is positioned at gate metal 1083 belows, separates with an insulating barrier 1086 between the two.Raceway groove 1085 is positioned at gate metal 1083 tops, separates with an insulating barrier 1087 between the two.What deserves to be mentioned is that raceway groove 1084 and 1085 all adopts amorphous silicon material to be fit to traditional low temperature process.
Yet, since the electronics of amorphous silicon move usefulness (mobility) comparatively speaking a little less than, for example its electronics moves the one thousandth that usefulness may only have low temperature polycrystalline silicon, so the performance of the usefulness of organic electric exciting light-emitting diode also can be affected.The mode that solves is for increasing by an extra metal 1088 and 1089 in raceway groove 1084 two ends, and is contacted with source metal 1081 and drain metal 1082 respectively.What must emphasize is that source metal 1081 and metal 1088 must some be overlapped in gate metal 1083; Drain metal 1081 and metal 1089 also must some be overlapped in gate metal 1083 and move usefulness to increase electronics.
As mentioned above, increase metal 1088 and 1089 and mean necessary many one photomasks.In addition, metal 1088 and 1089 photomask pattern, and the photomask pattern that the photomask pattern of source metal 1081 and drain metal 1082 must cooperate gate metal 1083 to be to reach overlapping purpose, and so being illustrated in the design of photomask pattern to have strict requirement.
Summary of the invention
The present invention's purpose is to make a dual-channel film transistor with the method for simplifying, and two raceway grooves of this thin-film transistor are all the polysilicon raceway groove.
The present invention's thin-film transistor comprises one first polysilicon layer, one first insulating barrier, a gate metal, one second insulating barrier, one second polysilicon layer and a metal level.This first insulating barrier is positioned at this first polysilicon layer top.This gate metal is positioned at this first insulating barrier top.This second insulating barrier is positioned at this gate metal and this first insulating barrier top.The overlapping part of this first insulating barrier and this second insulating barrier has the two ends that two contact holes correspond respectively to this first polysilicon layer.This second polysilicon layer is positioned at this second insulating barrier top.And this metal level is arranged in each this contact hole, to contact this first polysilicon layer and this second polysilicon layer.
The manufacture method of above-mentioned thin-film transistor is as follows.At first, form one first polysilicon layer in substrate top.Form one first insulating barrier, a gate metal and one second insulating barrier more in regular turn in this first polysilicon layer top.Then, form one second polysilicon layer in this second insulating barrier top.Then, remove this first insulating barrier of a part and this second insulating barrier to form two contact holes.And, form a metal level in each this contact hole to contact this first polysilicon layer and this second polysilicon layer.
In sum, the present invention is than known techniques one photomask less.In addition, owing to adopt polysilicon layer as raceway groove, so source metal and drain metal must not overlap with gate metal, can reduce the last requirement of photomask pattern design.
Description of drawings
Fig. 1 is the pixel cell wiring diagram of known active organic electro-luminescent display;
Fig. 2 is the driving transistors profile of Fig. 1;
Fig. 3 system is according to the dual-channel film transistor of first embodiment of the invention;
Fig. 4 A-4G is the processing step schematic diagram of the present invention's dual-channel film transistor; And
Fig. 5 system is according to the dual-channel film transistor of second embodiment of the invention;
The primary clustering symbol description
100 pixel cells, 308 first polysilicon layers
102 scan lines, 3082 doped regions
104 data lines, 3084 doped regions
106 switching transistors, 3086 channel regions
108 driving transistorss, 309 photoresist layers
1081 source metals, 310 second polysilicon layers
1082 drain metal, 3102 doped regions
1083 gate metals, 3104 doped regions
1084 raceway grooves, 3106 channel regions
1085 raceway grooves, 312 look edge layers
1086 insulating barriers, 314 insulating barriers
1087 look edge layers, 316 contact hole
1088 metals, 318 contact holes
1089 metals, 320 passivation layers
110 power lines, 322 through holes
112 Organic Light Emitting Diodes, 324 cover layers
114 electric capacity, 400 Organic Light Emitting Diodes
300 thin-film transistors, 402 transparency electrodes
301 substrates, 404 organic layers
302 gate metals, 410 luminous zones
303 insulating barriers, 420 non-light-emitting areas
304 drain metal, 500 thin-film transistors
305 first amorphous silicon layers, 504 drain metal
306 source metals, 506 source metals
307 second amorphous silicon layers, 510 second polysilicon layers
Embodiment
Now cooperate icon that thin-film transistor of the present invention and manufacture method thereof are described in detail in detail, and enumerate preferred embodiment and be described as follows:
Please refer to Fig. 3, is the present invention's thin-film transistor.Thin-film transistor 300 comprises a gate metal 302, a drain metal 304, one source pole metal 306 and one first polysilicon layer 308 and one second polysilicon layer 310.Gate metal 302 is folded between first polysilicon layer 308 and second polysilicon layer 310.First polysilicon layer 308 comprises two doped regions 3082 and 3084 and one channel region 3086, is positioned at gate metal 302 belows, and is separated by with insulating barrier 312 and gate metal 302.Second polysilicon layer 310 comprises two doped regions 3102 and 3104 and one channel region 3106, is positioned at gate metal 302 tops, is separated by with insulating barrier 314 and gate metal 302.
Two contact holes 316 and 318 lay respectively at gate metal 302 both sides, and run through insulating barrier 314 and 312 and expose the doped region 3082 and 3084 of first polysilicon layer 308 to the open air.Source metal 306 is formed in the contact hole 316, with the doped region 3082 that is contacted with first polysilicon layer 308, and the doped region 3102 that is contacted with second polysilicon layer 310.Drain metal 304 forms in the contact hole 318, with the doped region 3084 that is contacted with first polysilicon layer 308, and the doped region 3104 that is contacted with second polysilicon layer 310.
During as the active block of organic electroluminescence panel, source metal 306 is to be electrically connected to an Organic Light Emitting Diode 400 with thin-film transistor 300.Because first polysilicon layer 308 and second polysilicon layer 310 be overlapping up and down, therefore not occupying volume outward the panel area and avoid reducing aperture opening ratio.
What deserves to be mentioned is, between source metal 306 and the doped region 3082, or be directly to contact between drain metal 304 and the doped region 3084, need not set up extra metal level and gate metal 302 keeps the overlapping electronics that promotes to move.Reason is that the electronics of first polysilicon layer 308 moves the raceway groove that efficient is better than known amorphous silicon.Hence one can see that, the present invention's thin-film transistor on making than known techniques one photomask less.Detailed processing step is described below.
Please refer to Fig. 4 A-4G, is the processing step schematic diagram of dual-channel film transistor.As Fig. 4 A, on substrate 301, form an insulating barrier 303 earlier and not disturbed by other circuit unit with protective film transistor 300, for example come the electrical interference of self-capacitance or other thin-film transistor.Form one first amorphous silicon layer 305 again in insulating barrier 303 tops, and with first amorphous silicon layer, 305 patternings.Then, form insulating barrier 312 in first amorphous silicon layer, 305 tops.Again gate metal 302 is made in insulating barrier 312 tops, and is overlapped in first amorphous silicon layer 305.Then, form insulating barrier 314 and be covered in gate metal 302 tops.And, form one second amorphous silicon layer 307 in insulating barrier 314 tops, and be overlapped in gate metal 302.Insulating barrier 312 and 314 purposes are to separate gate metal 302 and first amorphous silicon layer 305 and second amorphous silicon layer 307 herein, therefore are commonly referred to as " gate insulator ".
As Fig. 4 B, first amorphous silicon layer 305 of Fig. 4 A and second amorphous silicon layer 307 by crystallization to form first polysilicon layer 308 and second polysilicon layer 310.In the present embodiment, crystallization step adopts field intensity rapid thermal anneal process (FERTA, field enhanced RTA) to carry out.The field intensity rapid thermal anneal process be rapid thermal anneal process (rapid thermal anneal, RTA) a kind of, its characteristic be amorphous silicon layer when carrying out rapid thermal annealing, quicken to help it to crystallize into polysilicon with a highfield.Crystallization step is not defined as the field intensity rapid thermal anneal process, and (SPC solid-phase-crystallization), or directly uses chemical vapour deposition technique (CVD) to come deposit spathic silicon also can to utilize other thermal anneal process, solid-phase crystallization method.
As Fig. 4 C, be the ion injecting program.At first, form second polysilicon layer 310 that a photoresist layer 309 covers a part.Because second polysilicon layer 310 and first polysilicon layer 308 are overlapping, so photoresist layer 309 has also covered first polysilicon layer 308 of a part simultaneously.Then, impose the ion injecting program and make first polysilicon layer 308 and second polysilicon layer 310 not formed doped region 3082,3084,3102 and 3104 by the part that photoresist layer 309 covers, the position is shown in Fig. 4 D.Because first polysilicon layer 308 is positioned at than the depths, and second polysilicon layer 310 is positioned at the surface, is injected to preferred mode so implement the ion of different depth at twice.
As Fig. 4 D, remove photoresist layer 309 after, originally covered by photoresist layer 309 and unadulterated zone promptly as channel region 3086 and 3106.
As Fig. 4 E, remove a part of insulating barrier 312 and insulating barrier 314 forming two contact holes 316 and 318 in second polysilicon layer, 310 both sides, and corresponding to the doped region 3082 and 3084 of first polysilicon layer 308.
As Fig. 4 F, form a metal level on second polysilicon layer 310, and on the exposed surface of each contact hole 316 and 318 and first polysilicon layer 308.This metal level that then removes second polysilicon layer, 310 channel regions, 3106 tops is with definition source metal 306 and drain metal 304.Thus, source metal 306 all is contacted with first polysilicon layer 308 and second polysilicon layer 310 simultaneously with drain metal 304.So far, the structure of dual-channel film transistor 300 completes.
Shown in Fig. 4 G, on the structure shown in Fig. 4 F, increase by a passivation layer 320 again, and form a through hole 322 in passivation layer 320 tops.One transparency electrode 402 is formed at passivation layer 320 tops, and is contacted with source metal 306 by through hole 322.One cover layer 324 is formed at transparency electrode 402 and passivation layer 320 tops to define a luminous zone 410 and a non-light-emitting area 420.Then refer again to Fig. 3, the various organic layers 404 with Organic Light Emitting Diode 400 are formed at transparency electrode 402 and cover layer 324 surfaces again.
Please refer to Fig. 5, is the present invention's second embodiment.Compared to Fig. 3, main discrepancy is the formation position of second polysilicon layer.In the present embodiment, second polysilicon layer 510 of thin-film transistor 500 is formed on source metal 506 and the drain metal 504, and the electronics when not influencing its operation moves efficient.At process aspect, except the formation order of source metal 506, drain metal 504 and second polysilicon layer 510 is different from thin-film transistor shown in Figure 3 300, all the other steps all can be general.
In above two embodiment, the crystallization step of amorphous silicon layer is not limited to adopt rapid thermal anneal process, also can adopt method for crystallising such as low temperature polycrystalline silicon.Two amorphous silicon layers are not limited to crystallization simultaneously, also can carry out crystallization at twice.What deserves to be mentioned is, be not limited to keep overlapping or not overlapping between source metal and drain metal and the gate metal.Therefore, can be comparatively flexible in the used photomask pattern design of source metal, drain metal and gate pole metal.
In sum, the present invention has following advantage at least:
1. than known techniques one photomask less.
2. the used photomask pattern of source metal and drain metal must not cooperate the used photomask pattern of gate metal, can reduce the last requirement of photomask pattern design.
Above-listed detailed description system specifies at preferred embodiment of the present invention, and only the foregoing description is not the claim in order to restriction the present invention, all do not break away from skill spirit of the present invention institute for it equivalence implement or change, all should be contained in the claim of this case.
Claims (9)
1. method for fabricating thin film transistor comprises:
One substrate is provided;
Form one first polysilicon layer in this substrate top;
Form one first insulating barrier in this first polysilicon layer top;
Form a gate metal in this first insulating barrier top;
Form one second insulating barrier in this gate metal top;
Form one second polysilicon layer in this second insulating barrier top;
Impose an ion injecting program in this first polysilicon layer and this second polysilicon layer, the ion of wherein implementing different depth at twice injects;
Remove this first insulating barrier of a part and this second insulating barrier to form two contact holes; And
Form a metal level in each this contact hole form to electrically connect the source metal and the drain metal of this first polysilicon layer and this second polysilicon layer respectively, this source metal and drain metal and this second polysilicon layer are overlapped respectively; And
Form a passivation layer covering this second polysilicon layer and this source metal and drain metal, and in this passivation layer, on source metal, form a through hole.
2. method according to claim 1, wherein above-mentioned ion injecting program more comprises:
Forming a photoresist layer covers the middle section of this first polysilicon layer and this second polysilicon layer and is overlapped in this gate metal;
The two side areas of this first polysilicon layer and this second polysilicon layer is injected a p type alloy.
3. method according to claim 1 more comprises:
Form one the 3rd insulating barrier between this substrate and this first polysilicon layer.
4. method according to claim 1 wherein forms this first polysilicon layer and comprises:
Form one first amorphous silicon layer in this substrate top; And
This first amorphous silicon layer of crystallization is to form this first polysilicon layer.
5. method according to claim 1 wherein forms this second polysilicon layer and comprises:
Form one second amorphous silicon layer in this second insulating barrier top; And
This second amorphous silicon layer of crystallization is to form this second polysilicon layer.
6. as the method as described in claim 4 or 5, wherein said crystallization step is by a rapid thermal anneal process.
7. thin-film transistor comprises:
One first polysilicon layer;
One first insulating barrier is positioned at this first polysilicon layer top;
One gate metal is positioned at this first insulating barrier top;
One second insulating barrier is positioned at this gate metal and this first insulating barrier top, and wherein the overlapping part of this first insulating barrier and this second insulating barrier has the two ends that two contact holes correspond respectively to this first polysilicon layer;
One second polysilicon layer is positioned at this second insulating barrier top; And
One metal level, be arranged in each this contact hole, to contact this first polysilicon layer and this second polysilicon layer, to form source metal and the drain metal that electrically connects this first polysilicon layer and this second polysilicon layer respectively, wherein this second polysilicon layer is formed at this metal level top;
One passivation layer is positioned at the top of this second polysilicon layer and metal level, and has the through hole on source metal.
8. as the thin-film transistor as described in the claim 7, wherein this second polysilicon layer is formed between this metal level and this second insulating barrier.
9. as the thin-film transistor as described in the claim 7, wherein this metal level is an one source pole metal or a drain metal.
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| CNB200610068203XA CN100449716C (en) | 2006-03-20 | 2006-03-20 | Thin film transistor and manufacturing method thereof |
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| CNB200610068203XA CN100449716C (en) | 2006-03-20 | 2006-03-20 | Thin film transistor and manufacturing method thereof |
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| CN100449716C true CN100449716C (en) | 2009-01-07 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11121261B2 (en) | 2019-07-03 | 2021-09-14 | Au Optronics Corporation | Semiconductor substrate |
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| CN107104196B (en) * | 2016-02-22 | 2019-03-26 | 上海和辉光电有限公司 | A kind of OLED device and preparation method thereof, display device |
| CN107808884A (en) * | 2016-08-24 | 2018-03-16 | 中芯国际集成电路制造(上海)有限公司 | The manufacture method of three dimensional NAND flush memory device |
| CN108242507B (en) * | 2016-12-26 | 2020-02-21 | 上海和辉光电有限公司 | Semiconductor device, preparation method thereof and display device |
| CN107393831B (en) * | 2017-07-28 | 2020-04-10 | 武汉天马微电子有限公司 | Thin film transistor, manufacturing method thereof and display panel |
| CN111584362B (en) * | 2020-05-14 | 2023-08-22 | Tcl华星光电技术有限公司 | Semiconductor device manufacturing method, semiconductor device and display panel |
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| JPH0595116A (en) * | 1991-10-01 | 1993-04-16 | Nec Corp | Semiconductor device and its manufacture |
| JPH08148693A (en) * | 1994-09-22 | 1996-06-07 | Sanyo Electric Co Ltd | Thin-film transistor and manufacture thereof |
| CN1133495A (en) * | 1994-12-26 | 1996-10-16 | 现代电子产业株式会社 | Double-channel thin-film transistor and making method thereof |
| CN1401135A (en) * | 2000-06-26 | 2003-03-05 | 皇家菲利浦电子有限公司 | Bottom gate type thin film transistor, its manufacturing method and liquid crystal display device using the same |
| CN1476079A (en) * | 2002-08-13 | 2004-02-18 | 上海宏力半导体制造有限公司 | Method of regulating quick flash storage unit starting voltage |
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Patent Citations (5)
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| JPH0595116A (en) * | 1991-10-01 | 1993-04-16 | Nec Corp | Semiconductor device and its manufacture |
| JPH08148693A (en) * | 1994-09-22 | 1996-06-07 | Sanyo Electric Co Ltd | Thin-film transistor and manufacture thereof |
| CN1133495A (en) * | 1994-12-26 | 1996-10-16 | 现代电子产业株式会社 | Double-channel thin-film transistor and making method thereof |
| CN1401135A (en) * | 2000-06-26 | 2003-03-05 | 皇家菲利浦电子有限公司 | Bottom gate type thin film transistor, its manufacturing method and liquid crystal display device using the same |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US11121261B2 (en) | 2019-07-03 | 2021-09-14 | Au Optronics Corporation | Semiconductor substrate |
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| CN1828852A (en) | 2006-09-06 |
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