JPH08148693A - Thin-film transistor and manufacture thereof - Google Patents

Abstract

PURPOSE: To lessen leakage current and obtain sufficient On-state current in a thin-film transistor. CONSTITUTION: A channel region 2a of a first semiconductor layer 2 and a channel region 6a of a second semiconductor layer 6 are controlled by means of a common gate electrode layer 4. Between the first semiconductor layer 2 and the second semiconductor layer 6, at least on electrical connection is made and the first semiconductor layer 2 and the second semiconductor layer 6 are connected in parallel or in series.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor (hereinafter referred to as "TFT") and its manufacturing method.

[0002]

PRIOR ART AND PROBLEM TO BE SOLVED BY THE INVENTION TFT
Are used, for example, as drive elements for liquid crystal displays. In such a TFT, it is necessary to reduce the leak current in order to increase the on / off ratio. One method of reducing the leakage current is to reduce the thickness of the semiconductor layer forming the channel region.

FIG. 15 is a sectional view showing a TFT in which a semiconductor layer forming such a channel region is thinned.
Referring to FIG. 15, a semiconductor layer 62 is formed on a substrate 61, and a drain region 62b and a source region 62c are formed by doping the semiconductor layer 62 with impurities. As a result, the channel region 62a is formed between the drain region 62b and the source region 62c. A gate insulating film 63 is provided on the semiconductor layer 62, and a gate electrode 64 is provided on the gate insulating film 63 above the channel region 62a. The semiconductor layer 62 is formed to have a film thickness of 100 to 200Å, for example.

By reducing the thickness of the semiconductor layer 62 in this way, it is possible to reduce the leakage current, but the thickness of the channel region 62a is reduced, so that the on-current is reduced. Cause

As another method of reducing the leak current in the TFT, there is a method of arranging two gate electrodes and a channel region in parallel to form a double gate type TFT. FIG. 16 is a sectional view showing such a double gate type TFT. Referring to FIG. 16, semiconductor layer 72 is formed on substrate 71. A drain region 72c, a source region 72e, and an intermediate region 72d are formed in the semiconductor layer 72 by doping impurities. A first channel region 72a is formed between the drain region 72c and the intermediate region 72d, and a second channel region 72b is formed between the intermediate region 72d and the source region 72e. A gate insulating film 73 is formed on the semiconductor layer 72, and a first gate electrode 74a and a second gate electrode 74b are formed above the first channel region 72a and the second channel region 72b, respectively. Has been done. Interlayer insulation 75 is formed on these gate electrodes 74a and 74b.

By adopting the double gate structure as described above, it is possible to reduce the leak current, but since it becomes necessary to provide the gate electrode and the channel region in parallel, the device size becomes large and the degree of integration is increased. There is a problem that it is difficult to increase the density and increase the density.

FIG. 17 is a sectional view showing an example in which the double gate type TFT as shown in FIG. 16 is used as a driving element of a liquid crystal display, and FIG. 18 is a plan view. With reference to FIG. 17, the source region 72e is electrically connected to the pixel electrode 51 made of ITO or the like formed on the substrate 71. A contact hole 75a is formed above the drain region 72c, and the drain electrode 78 is formed by depositing Al or the like.
It is formed so as to fill the inside. The tip of the drain electrode 78 is electrically connected to the drain region 72c.

As shown in FIG. 18, two gate electrodes 74a and 74b extend from the gate line 74. The two gate electrodes 74a and 74b exist between the pixel electrode 51 and the data line 52. Therefore, there is a problem that the area occupied by the driving element becomes large and the element size cannot be reduced.

As described above, when the channel region is thinned in order to reduce the leak current, there arises a problem that the on-current is reduced. In addition, when the double gate structure is adopted to reduce the leakage current, the device size becomes large, the integration degree cannot be increased, and there is a problem that the density cannot be increased.

An object of the present invention is to provide a TFT capable of solving the above problems of the prior art and reducing the leak current, and at the same time, a TFT capable of reducing the element size and increasing the density. It is to provide a manufacturing method.

[0011]

A thin film transistor according to a first aspect of the present invention is formed with a gate electrode layer, a source region and a drain region sandwiching a channel region, and the channel region is formed at a position facing the gate electrode layer. A first semiconductor layer, a first insulating layer provided between the gate electrode layer and the channel region of the first semiconductor layer, and a source region and a drain region sandwiching the channel region. A second semiconductor layer that is provided on the opposite side of the first semiconductor layer with the channel sandwiched between and the channel region is formed at a position facing the gate electrode layer; and the channel region of the gate electrode layer and the second semiconductor layer. And a second insulating layer provided therebetween, and at least one electrical connection is formed between the first semiconductor layer and the second semiconductor layer.

In a thin film transistor according to a second aspect of the present invention, a gate electrode layer, a source region and a drain region sandwiching a channel region are formed, and the channel region is formed at a position facing the gate electrode layer. A semiconductor layer,
A first insulating layer provided between the gate electrode layer and the channel region of the first semiconductor layer, a source region and a drain region sandwiching the channel region are formed, and the first insulating layer is formed with respect to the gate electrode layer.
Second semiconductor layer provided outside the semiconductor layer and having channel regions formed at positions corresponding to the gate electrode layer and the channel region of the first semiconductor layer, the first semiconductor layer, and the second semiconductor layer. A second insulating layer formed between the first semiconductor layer and the second semiconductor layer, and at least one electrical connection is formed between the first semiconductor layer and the second semiconductor layer.

According to a third aspect of the present invention, in the first or second aspect of the present invention, the source region or drain region of the first semiconductor layer and the drain region of the second semiconductor layer or By electrically connecting with the source region, the first semiconductor layer and the second semiconductor layer are connected in series.

According to a fourth aspect of the present invention, in the first aspect or the second aspect of the present invention, an electrical connection is made between the source regions and the drain regions of the first semiconductor layer and the second semiconductor layer, respectively. By connecting to, the first semiconductor layer and the second semiconductor layer are connected in parallel.

In the thin film transistor of the present invention, the first
The electrical connection between the semiconductor layer and the second semiconductor layer can be realized by various methods. For example, when an insulating layer or the like is interposed between the portions where the first semiconductor layer and the second semiconductor layer are to be electrically connected, a contact hole is formed and a metal or the like is placed in the contact hole. Electrical connection can be made by vapor deposition.

Further, by directly forming the portion for electrically connecting the second semiconductor layer on the portion for electrically connecting the first semiconductor layer, the portion is directly contacted and electrically connected. You can also make connections.

The manufacturing method of the present invention is one of the methods by which the thin film transistor of the present invention can be manufactured.
After forming an insulating layer on the gate electrode layer and forming a semiconductor layer on the insulating layer, the semiconductor layers on both sides of the channel region are formed so that the region of the semiconductor layer above the gate electrode layer becomes the channel region. This is a method of doping a region with impurities to form a source region and a drain region.

Specifically, a step of applying a resist film on the semiconductor layer, a step of patterning the resist film by back exposure using the gate electrode layer as a mask, and a step of ionizing the resist film left by the patterning as a mask Forming a source region and a drain region in the semiconductor layer by implanting.

According to a more preferred embodiment of the manufacturing method of the present invention, a step of forming a first semiconductor layer on a substrate,
A step of forming a first insulating film on the first semiconductor layer,
A step of forming a gate electrode layer on the first insulating film, a step of forming a second insulating film on the gate electrode layer, and a second step
Forming a second semiconductor layer on the insulating film of
A step of applying a resist film on the semiconductor layer, a step of patterning the resist film by back exposure using the gate electrode layer as a mask, and a step of ion-implanting the resist film left by patterning with a mask. And forming a source region and a drain region in the semiconductor layer.

[0020]

According to the first aspect of the present invention, the channel region of the first semiconductor layer is opposed to the gate electrode layer with the first insulating layer interposed therebetween, and the channel region of the second semiconductor layer is Similarly, it faces the gate electrode layer with the second insulating layer in between.
Therefore, the gate electrode layer becomes a common gate electrode layer for the channel region of the first semiconductor layer and the channel region of the second semiconductor layer. In such a first semiconductor layer and a second semiconductor layer, a series-connected TFT is formed by connecting the first semiconductor layer and the second semiconductor layer in series according to the third aspect. The same function as that of the conventional double gate type TFT can be provided.

Further, according to the fourth aspect, by connecting the first semiconductor layer and the second semiconductor layer in parallel, the two channel regions can be operated by the potential of one gate electrode layer. With such a configuration, since there are two channel regions, the on-current can be secured, and therefore the film thickness of one channel region can be reduced. Therefore, the leak current can be reduced,
Moreover, the on-current can be secured and the on / off ratio can be increased.

According to the second aspect of the present invention, the channel region of the first semiconductor layer is provided on one side of the gate electrode layer via the first insulating layer, and the channel region of the second semiconductor layer is provided. The channel region is further provided outside the channel region of the first semiconductor layer with the second insulating layer interposed therebetween. Therefore, the gate electrode layer can be commonly used for the channel region of the first semiconductor layer and the channel region of the second semiconductor layer, and one gate electrode layer and the channel region of the first semiconductor layer can be used. And the channel region of the semiconductor layer can be controlled.

In a second aspect according to the present invention, a TF having a double gate structure is obtained by connecting the first semiconductor layer and the second semiconductor layer in series according to the third aspect of the present invention.
A function similar to T can be added.

Further, in the second aspect of the present invention, by connecting the first semiconductor layer and the second semiconductor layer in parallel according to the fourth aspect of the present invention, the film thickness of the channel region of the semiconductor layer is reduced. Even if it is made thin, the on-current can be secured, the leak current can be reduced, and the on / off ratio can be increased.

In the manufacturing method of the present invention, a resist film is applied on the semiconductor layer formed on the gate electrode layer through the insulating layer, and the resist film is back-exposed by using the gate electrode layer as a mask. Patterning. A source region and a drain region are formed in the semiconductor layer by ion implantation using the patterned resist film as a mask layer. Therefore, the source region and the drain region can be formed in the semiconductor layer formed on the gate electrode layer by self-alignment, and thus the channel region can be formed above the gate electrode layer.

[0026]

FIG. 1 is a sectional view showing an embodiment according to the first aspect of the present invention. Referring to FIG. 1, a first substrate is formed on an insulating substrate 1 made of glass or quartz.
The semiconductor layer 2 is formed. A drain region 2b and a source region 2c are formed in the first semiconductor layer 2 with the channel region 2a sandwiched therebetween. The first semiconductor layer 2 can be formed to have a thickness of, for example, about 200 Å or less in order to reduce the leakage current, and is 100 in this embodiment.
It is formed with a thickness of Å.

A first insulating layer 3 made of SiO ₂ or the like is formed on the first semiconductor layer 2. A gate electrode layer 4 is formed above the channel region 2a on the first insulating layer 3.
Are formed. The gate electrode layer 4 can be formed of, for example, polysilicon heavily doped with impurities or a metal such as aluminum (Al).

A second insulating layer 5 made of, for example, SiO ₂ is formed on the first insulating layer 3 and the gate electrode layer 4. A second semiconductor layer 6 made of, for example, polysilicon is formed on the second insulating layer 5.
The film thickness of the second semiconductor layer 6 can be the same as that of the first semiconductor layer 2, for example. A channel region 6a is formed in a region of the second semiconductor layer 6 above the gate electrode layer 4. A drain region 6b and a source region 6c are formed sandwiching the channel region 6a.

On the second semiconductor layer 6, for example, SiN
_An interlayer insulating layer 7 made of _X or the like is formed. A contact hole 7a is formed above the drain region 2b of the first semiconductor layer 2, and a drain electrode 8 is formed by evaporating Al, for example, so as to fill the contact hole 7a. The contact hole 7a is
Since it is formed so as to pass through the drain region 6b of the second semiconductor layer 6, the drain region 8 is formed by the drain electrode 8.
b and the drain region 6b are electrically connected. The upper end of the drain electrode 8 is exposed above the interlayer insulating film 7.

Similarly, a contact hole 7b is formed on the drain region 2c, and a source electrode 9 made of Al or the like is formed so as to fill the contact hole 7b. Since the contact hole 7b is formed to pass through the source region 6c of the second semiconductor layer 6, the source electrode 9 electrically connects the source region 6c and the source region 2c. The upper end of the source electrode 9 is exposed above the interlayer insulating film 7.

The drain region 6b of the second semiconductor layer 6 and the drain region 2b of the first semiconductor layer 2 are electrically connected by the drain electrode 8, and the source electrode 9 forms the second semiconductor layer 6 of the second semiconductor layer 6. The source region 6c and the source region 2c of the first semiconductor layer 2 are electrically connected. Therefore, according to the fourth aspect of the present invention, the first semiconductor layer 2 and the second semiconductor layer 2
And the semiconductor layer 6 are connected in parallel.

The channel region 6a of the second semiconductor layer 6 is
It is located above the gate electrode layer 4 with the second insulating layer 5 interposed therebetween. In addition, the channel region 2a of the first semiconductor layer 2 is
It is located below the gate electrode layer 4 with the first insulating layer 3 interposed therebetween. Since the first semiconductor layer 2 and the second semiconductor layer 6 are connected in parallel as described above, the channel region 2a and the channel region 6a are both controlled by the common gate electrode layer 4. Therefore, even if the film thicknesses of the first semiconductor layer 2 and the second semiconductor layer 6 are thin, a sufficient on-current can be secured. Therefore, the leak current can be reduced and a sufficient on-current can be secured.

FIG. 2 is a sectional view showing an example of steps for manufacturing the embodiment shown in FIG. Referring to FIG. 2 (a),
A first semiconductor layer 2 made of polysilicon is formed on a substrate 1 by a plasma CVD method or a low pressure CVD method. This polysilicon may be formed by crystallizing by heat treatment after forming amorphous silicon. The film thickness is, for example, 100 Å. On the first semiconductor layer 2, for example, by a plasma CVD method or a low pressure CVD method, for example, SiO ₂ having a film thickness of 1000 Å is formed to form the first insulating layer 3. Next, an Al film having a film thickness of 3000 Å is deposited on the first insulating layer 3 by vapor deposition or the like, and is patterned to form the gate electrode layer 4.

Using the formed gate electrode layer 4 as a mask,
P (phosphorus) with acceleration energy of 100 keV, 5 × 10
By implanting ions under the condition of ¹⁵ dose / cm ² ,
A conductive drain region 2b and a source region 2c are formed in the first semiconductor layer 2, and a channel region 2a is formed between them.
To form.

With reference to FIG. 2B, next, for example, a film thickness of 1000Å is formed on the first insulating layer 3 and the gate electrode layer 4.
Of SiO ₂ is formed by a low pressure CVD method or the like to form the second insulating layer 5. On the second insulating layer 5, for example, a film thickness 1
A 00Å polysilicon layer is formed by a low pressure CVD method or the like to form the second semiconductor layer 6.

With reference to FIG. 2C, next, a resist film 10 is applied to the entire upper surface of the second semiconductor layer 6 so as to have a film thickness of 1 μm, for example, and then light is applied from the substrate 1 side. By performing back exposure, patterning is performed using the gate electrode layer 4 as a mask, so that the resist film is left only above the gate electrode layer 4.

Next, using the resist film 10 left by patterning as a mask, P is added at an acceleration energy of 40 ke.
The drain region 6b and the source region 6c are formed in the second semiconductor layer 6 by ion implantation under the conditions of V and 5 × 10 ¹⁵ dose / cm ² . Thereby, the drain region 6b and the source region 6c can be formed by self-alignment, and the channel region 6a is formed in the portion between them.

Next, referring to FIG. 2D, after removing the resist film 10, for example, Si is formed on the second semiconductor layer 6.
The interlayer insulating film 7 made of N _x or the like is formed by a low pressure CVD method or the like. The film thickness of the interlayer insulating film 7 is, eg, 4000 Å.

After forming such an interlayer insulating film 7, hydrogen plasma treatment is performed. Conditions for the hydrogen plasma treatment are, for example, RF power of 350 W, total pressure of 0.9 Torr,
The substrate temperature is 300 ° C. and the processing time is 2 hours.

Next, referring to FIG. 2E, a contact hole 7a penetrating the drain region 6b is formed above the drain region 2b. Further, a contact hole 7b penetrating the source region 6c is also formed above the source region 2c. A drain electrode 8 and a source electrode 9 made of Al or the like are formed by, for example, vapor deposition so as to fill the contact holes 7a and 7b thus formed. The drain electrode 8 is in electrical contact with the drain region 2b of the first semiconductor layer 2 and the drain region 6b of the second semiconductor layer 6, and these drain regions 2b
b and the drain region 6b are electrically connected. The upper end of the drain electrode 8 is exposed above the interlayer insulating film 7.

The source electrode 9 is electrically connected to the source region 2c of the first semiconductor layer 2 and the source region 6c of the second semiconductor layer 6, and as a result, the source region 2c and the source region 6c are electrically connected. Connected to each other. The upper end of the source electrode 9 is exposed above the interlayer insulating film 7.

As described above, the TFT structure of the embodiment shown in FIG. 1 can be formed. FIG. 3 is a cross-sectional view showing another embodiment according to the first aspect of the present invention. This embodiment is also an embodiment according to the fourth aspect of the present invention in which the first semiconductor layer and the second semiconductor layer are connected in parallel.

Referring to FIG. 3, a first semiconductor layer 12 is formed on a substrate 11 made of glass or quartz. A drain region 12b and a source region 12c are formed in the first semiconductor layer 12 with the channel region 12a interposed therebetween. A first insulating layer 13 is formed on the channel region 12a, and a gate electrode layer 14 is formed on the first insulating layer 13. A second insulating layer 15 is formed above the gate electrode layer 14. A second semiconductor layer 16 is formed above the second insulating layer 15 and above the drain region 12b and the source region 12c. A channel region 16a is formed above the gate electrode layer 14 of the second semiconductor layer 16, and a drain region 16b and a source region 16c are formed on both sides of the channel region 16a. Drain region 16
b is hung downward at its end, and the drain region 1
It is in contact with 2b. Similarly, the source region 16c hangs downward at its end and is in contact with the source region 12c.

An interlayer insulating film 17 is formed on the second semiconductor layer 16 along the second semiconductor layer 16. A contact hole 17a is formed in the interlayer insulating film 17 above the drain region 16b.
A drain electrode 18 is formed so as to fill 7a. The lower end of the drain electrode 18 has a drain region 16b.
, And its upper end is exposed above the interlayer insulating film 17.

Similarly, a contact hole 17b is formed in the interlayer insulating film 17 above the source region 16c, and the source electrode 19 is formed so as to fill the contact hole 17b.
Are formed. The lower end of the source electrode 19 is in contact with the source region 16c, and the upper end of the source electrode 19 is exposed above the interlayer insulating film 17.

In this embodiment, the drain region 16b and the source region 16c of the second semiconductor layer 16 are in direct contact with the drain region 12b and the source region 12c of the first semiconductor layer 12, respectively, so that they are electrically connected to each other. Connected to each other. With such a connection, the first semiconductor layer 12 and the second semiconductor layer 16 are connected in parallel. Therefore, as in the embodiment shown in FIG. 1, the channel region 12a of the first semiconductor layer 12 and the second semiconductor layer 16 are formed.
Of the common gate electrode layer 14
Controlled by. Therefore, a sufficient on-current can be secured, and the first semiconductor layer 12 and the second semiconductor layer 1
By reducing the film thickness of 6, the leak current can be reduced and a sufficient on-current can be secured.

FIG. 4 is a sectional view showing an example of a process for manufacturing the embodiment shown in FIG. Referring to FIG. 4 (a),
On the substrate 11, for example, polysilicon having a film thickness of 500 Å is formed by a plasma CVD method or a low pressure CVD method, and the first semiconductor layer 12 is formed. On this first semiconductor layer 12, for example, a SiO ₂ film having a film thickness of 1000 Å is formed by a low pressure CVD method or the like to form a first insulating layer 13.
A gate electrode layer 14 is formed by forming an Al film with a film thickness of 2000 Å on the first insulating layer 13 by vapor deposition and then patterning the Al film.

Referring to FIG. 4B, next, for example, a film thickness of 100 is formed on the gate electrode layer 14 and the first insulating layer 13.
A 0 Å SiO ₂ film is formed by a low pressure CVD method or the like to form the second insulating layer 15. A resist film 20a is applied to the entire upper surface of the second insulating layer 15 and then patterned by mask alignment, thereby leaving the resist film 20a in the upper region including the periphery of the gate electrode layer 14.

With reference to FIG. 4C, next, using the resist film 20a as a mask, the second insulating layer 15 and the first insulating layer 15 are formed.
The insulating layer 13 is etched to expose the first semiconductor layer 12 around the resist film 20a.

With reference to FIG. 4D, next, after removing the resist film 20a, the first semiconductor on the second insulating layer 15 above and around the gate electrode layer 14 and around it. A second semiconductor layer 16 made of, for example, polysilicon having a film thickness of 500 Å is formed on the layer 12.

Next, after coating a resist film 20b on the entire surface of the second semiconductor layer 16, light is irradiated from the substrate 11 side, and the resist film 2 is used with the gate electrode layer 14 as a mask.
0b is back-exposed to leave only the resist film 20b above the gate electrode layer 14.

Next, using the resist film 20b thus formed as a mask, P is added at an acceleration energy of 40 ke.
Ions are implanted under the conditions of V, 5 × 10 ¹⁵ dose / cm ² , and then annealed at 900 ° C. for 1 hour. As a result, predetermined regions of the second semiconductor layer 16 and the first semiconductor layer 12 are made conductive, and the drain regions 16b and 12b and the source regions 16c and 12c are formed. Thereby, the channel regions 16a and 12a are formed between them.

Referring to FIG. 4E, next, after removing the resist film 20b, for example, SiN _x having a film thickness of 4000 Å.
An interlayer insulating film 17 made of, for example, is formed. Interlayer insulation film 1
After formation of 7, hydrogen plasma treatment is performed. The conditions for the hydrogen plasma treatment are, for example, RF power of 350 W, total pressure of 0.9 Torr, substrate temperature of 300 ° C., and treatment time of 2 hours.

Referring to FIG. 4F, the contact hole 1 is then formed in the interlayer insulating film 17 above the drain region 16b.
7a is formed. Similarly, a contact hole 17b is formed in the interlayer insulating film 17 above the source region 16c. Contact holes 17a and 17 formed in this way
Drain electrode 1 made of Al or the like so as to fill the inside of b
8 and the source electrode 19 are formed by vapor deposition or the like. The lower end of the drain electrode 18 contacts the drain region 16b,
The upper end is exposed on the interlayer insulating film 17. Similarly, the lower end of the source electrode 19 is electrically connected to the source region 16c, and the upper end is exposed on the interlayer insulating film 17.

As described above, the TFT structure of the embodiment shown in FIG. 3 can be manufactured. FIG. 5 is a sectional view showing an embodiment according to the second aspect of the present invention. Also in this TFT structure, the first semiconductor layer and the second semiconductor layer are connected in parallel, and the structure is in accordance with the fourth aspect of the present invention.

Referring to FIG. 5, a second semiconductor layer 26 made of polysilicon or the like is formed on an insulating substrate 21 made of glass or quartz. A channel region 26a is sandwiched in the second semiconductor layer 26, and a drain region 26b and a source region 26c are formed on both sides of the channel region 26a.

Channel region 26a of the second semiconductor layer 26
A second insulating layer 25 is formed on the above. The second insulating layer 25 is formed so as to cover only the upper portion of the channel region 26a. The first semiconductor layer 22 is formed on the second insulating layer 25 and the second semiconductor layer 26.

In the region of the first semiconductor layer 22 on the second insulating layer 25, the channel region 22a is formed. A drain region 22b and a source region 22c are formed on both sides of the channel region 22a.

The channel region 22a of the first semiconductor layer 22
A first insulating layer 23 is formed on the top. The first insulating layer 23 is formed only above the channel region 22a. A gate electrode layer 24 made of metal such as polysilicon or Al is formed on the second insulating layer 23. An interlayer insulating film 27 is formed so as to cover the gate electrode layer 24 and the first semiconductor layer 22. A contact hole 27a is formed above the drain region 22b of the first insulating layer 22. A drain electrode 28 made of Al or the like is formed so as to fill the contact hole 27a. Drain electrode 2
The lower end of 8 is in contact with the drain region 22b, and the upper end is exposed on the interlayer insulating film 27.

Similarly, a contact hole 27b is formed above the source region 22c, and a source electrode 29 made of Al or the like is formed so as to fill the contact hole 27b. The lower end of the source electrode 29 is in contact with the source region 22c, and the upper end is exposed on the interlayer insulating film 27.

In the present embodiment, the first semiconductor layer 22
The channel region 22 a of the second semiconductor layer 26 and the channel region 26 a of the second semiconductor layer 26 are both provided on one side of the gate electrode layer 24. The channel region 22a includes the first insulating layer 23.
Is provided on one side of the gate electrode layer 24 via
The channel region 26a is provided outside the channel region 22a via the second insulating layer 25. The channel region 26a is larger than the channel region 22a in the gate electrode layer 24.
Since the gate electrode layer 24 is located at a position farther from, the influence of the potential of the gate electrode layer 24 is weaker than that of the channel region 22a, but both can be controlled by the gate electrode layer 24. Further, in the present embodiment, the first semiconductor layer 22 and the second semiconductor layer 26 are electrically connected by directly contacting the drain regions 22b and 26b and the source regions 22c and 26c. Therefore, the first semiconductor layer 22 and the second semiconductor layer 22
The semiconductor layer 26 is connected in parallel. Therefore, the channel regions 22a and 26a can be controlled by the gate electrode layer 24, and a sufficient ON current can be secured. Therefore, even if the film thickness of the channel regions 22a and 26a is reduced to reduce the leak current, a sufficient ON current can be secured.

FIG. 6 is a sectional view showing an example of a process for manufacturing the embodiment shown in FIG. Referring to FIG. 6 (a),
A second semiconductor layer 26 made of, for example, polysilicon having a film thickness of 100 Å is formed on the substrate 21. On the second semiconductor layer 26, for example, SiO _{2 having a} film thickness of 1000 Å is formed.
A second insulating layer 25 made of a film or the like is formed. After applying a resist film on the entire surface of the second insulating layer 25, the resist film 3 is formed by patterning by mask alignment.
0a is formed.

Referring to FIG. 6B, the resist film 30a
After the second insulating layer 25 is patterned by etching using the mask as a mask, the first insulating layer 25 and the second semiconductor layer 26 are formed on the first insulating layer 25 and the first insulating layer 25 made of, for example, polysilicon having a film thickness of 100 Å. The semiconductor layer 22 is formed. A first insulating layer 23 made of, for example, a SiO ₂ film having a film thickness of 1000 Å is formed on the first semiconductor layer 22.

Referring to FIG. 6C, next, on the first insulating layer 22, a gate electrode layer 24 made of metal such as polysilicon or Al having a film thickness of 2000 Å is formed on the first insulating layer 22. It is formed on the entire surface of 23. Further, a resist film 30b is formed on the entire surface of the gate electrode layer 24. By masking the resist film 30b with an aligner or the like, patterning is performed so that only the upper portion of the second insulating layer 25 remains.

Referring to FIG. 6D, the gate electrode layer 24 and the first insulating layer 23 are etched and patterned using the patterned resist film 30b as a mask. Next, after removing the resist film 30b, P is ion-implanted using the gate electrode layer 24 and the first insulating film 23 as a mask. As a result, the drain region 22b and the source region 22c of the first semiconductor layer 22 and the second semiconductor layer 2 are formed.
The drain region 26b and the source region 26c of No. 6 are made conductive. The conditions for ion implantation are, for example, 40 keV,
It can be performed at 5 × 10 ¹⁵ dose / cm ² . After such ion implantation, 900 as an activation annealing treatment
Heat treatment is performed at 1 ° C. for 1 hour. As a result, the drain regions 22b and 26b and the source regions 22c and 26c become n ⁺ type semiconductor layers. When the gate electrode layer 24 is formed of a semiconductor layer such as polysilicon, the gate electrode layer 24 also becomes an n ⁺ type semiconductor layer.

When the gate electrode layer 24 is made of a metal such as Al, it is not necessary to remove the resist film 30b before the ion implantation. With reference to FIG. 6E, next, an interlayer insulating film 27 made of, for example, SiN _x having a film thickness of 4000 Å is formed on the entire surface. After forming such an interlayer insulating film 27, hydrogen plasma treatment is performed. The conditions for the hydrogen plasma treatment are, for example, RF power 350.
W, total pressure 0.9 Torr, substrate temperature 300 ° C.,
The processing time is 2 hours.

Referring to FIG. 6F, next, a contact hole 27a is formed above the drain region 22b. Similarly, a contact hole 27b is formed above the source region 22c. Next, these contact holes 2
A drain electrode 28 and a source electrode 29 are formed by depositing Al or the like so as to fill 7a and 27b. The lower end of the drain electrode 28 has the drain region 22.
It is in contact with b and is electrically connected, and the upper end is exposed above the interlayer insulating film 27. The lower end of the source electrode 29 is in direct contact with and electrically connected to the source region 22c, and the upper end thereof is exposed above the interlayer insulating film 27.

As described above, the TFT structure of the embodiment shown in FIG. 5 can be manufactured. In the embodiment according to the second aspect of the present invention shown in FIGS. 5 and 6, the first semiconductor layer 22 and the second semiconductor layer 2 according to the fourth aspect of the present invention.
Although 6 and 6 are connected in parallel, the first semiconductor layer 22 and the second semiconductor layer 26 may be connected in series according to the third aspect of the present invention.

FIG. 7 is a sectional view showing still another embodiment according to the first aspect of the present invention. In the embodiment shown in FIG. 7, the first semiconductor layer and the second semiconductor layer are connected in series, which is an embodiment according to the third aspect of the present invention.

Referring to FIG. 7, a first semiconductor layer 32 made of polysilicon is formed on an insulating substrate 31 made of glass or quartz. First semiconductor layer 3
A first insulating layer 33 made of SiO ₂ or the like is formed on the second layer ₂ . A channel region 32a, a drain region 32b, and a source region 33c are formed in the first semiconductor layer 32.

Channel region 32a of the first semiconductor layer 32
A gate electrode layer 34 is formed on the upper first insulating layer 33. A second insulating layer 35 made of SiO ₂ or the like is formed on the gate electrode layer 34 and the first insulating layer 33.
Are formed.

A second semiconductor layer 36 is formed on the second insulating layer 35. A channel region 36a is formed above the gate electrode layer 34 of the second semiconductor layer 36, and the source region 36 is formed on both sides of the channel region 36a.
c and the drain region 36b are formed.

An interlayer insulating film 37 made of SiN _x or the like is formed on the second semiconductor layer 36. Above the drain region 32b of the first semiconductor layer 32, the first insulating layer 33, the second insulating layer 35, and the second semiconductor layer 36.
A contact hole 37a is formed so as to penetrate the source region 36c. This contact hole 37a
A contact portion 38 made of Al or the like is formed therein. The contact portion 38 electrically connects the source region 36c of the second semiconductor layer 36 and the drain region 32b of the first semiconductor layer 32. Therefore, in the present embodiment, the first semiconductor layer 32 and the second semiconductor layer 3 are
6 are connected in series.

Channel region 32a of the first semiconductor layer 32
Are located below the gate electrode layer 34 with the first insulating layer 33 interposed therebetween. In addition, the channel region 36 a of the second semiconductor layer 36 has the gate electrode layer 3 via the second insulating layer 35.
It is located above 4. Therefore, the channel region 32a and the channel region 36a can be controlled by the gate electrode layer 34. Therefore, in the present embodiment, the channel regions 32a and 36a of the first semiconductor layer 32 and the second semiconductor layer 36, which are connected in series, can be controlled by the one common gate electrode layer 34.
Therefore, the leakage current can be reduced as in the conventional double-gate structure TFT. In addition, T of the present embodiment
Since the FT structure is a structure in which two semiconductor layers are stacked, the size of the element can be reduced.

FIG. 8 is a sectional view showing an example of a process for manufacturing the embodiment shown in FIG. Referring to FIG. 8 (a),
The first semiconductor layer 3 is formed on the substrate 31 by forming, for example, polysilicon with a film thickness of 500 Å by a low pressure CVD method or the like.
2 is formed. On the first semiconductor layer 32, for example, a SiO ₂ film having a film thickness of 1000 Å is formed by a low pressure CVD method or the like to form the first insulating layer 33. An Al film having a film thickness of 3000 Å, for example, is formed on the first insulating layer 33, and the gate electrode layer 34 is formed by patterning the Al film.

By implanting P ions using the gate electrode layer 34 as a mask, a drain region 32b and a source region 32c are formed in the first semiconductor layer 32. The ion implantation conditions are, for example, 100 keV, 5 × 1.
It is performed at 0 ¹⁵ dose / cm ² .

Referring to FIG. 8B, next, for example, a film thickness of 100 is formed on the gate electrode layer 34 and the first insulating layer 33.
The second insulating layer 35 is formed by forming a 0Å SiO ² film by a low pressure CVD method or the like. The second semiconductor layer 36 is formed on the second insulating layer 35 by, for example, forming polysilicon having a film thickness of 500 Å by a low pressure CVD method or the like.
Is formed.

Referring to FIG. 8C, next, a resist film 40 is applied on the entire surface of the second semiconductor layer 36 so as to have a film thickness of 1 μm, for example. Applied resist film 40
Is patterned by using the gate electrode layer 34 as a mask by irradiating light from the substrate 31 side, and the resist film 40 is left only above the gate electrode layer 34.

Next, P is ion-implanted by using this resist film 40 as a mask, whereby the second semiconductor layer 3 is formed.
6, the drain region 36b and the source region 36c are formed. The conditions for ion implantation are, for example, 40 ke
V, 5 × 10 ¹⁵ dose / cm ² is used.

Referring to FIG. 8D, next, after removing the resist film 40, a contact hole 37a is formed above the drain region 32b of the first semiconductor layer 32.
The contact hole 37a is formed so as to penetrate the first insulating layer 33, the second insulating layer 35, and the source region 36c of the second semiconductor layer 36. Next, Al is vapor-deposited so as to fill the contact hole 37a, thereby forming the contact portion 38. By forming the contact portion 38, the source region 36c of the second semiconductor layer 36 and the drain region 32 of the first semiconductor layer 32 are formed.
and b are electrically connected.

Referring to FIG. 8E, next, SiN _x having a film thickness of 4000 Å is formed on the second semiconductor layer 36 by a low pressure CVD method or the like to form an interlayer insulating film 37. The upper end of the contact portion 38 is formed on the interlayer insulating film 37.
Embedded inside.

After forming the interlayer insulating film 37, hydrogen plasma treatment is performed. The conditions for the hydrogen plasma treatment are: RF power 350 W, total pressure 0.9 Torr, substrate temperature 3
It is carried out at 00 ° C. for a treatment time of 2 hours.

As described above, the TFT structure of the embodiment shown in FIG. 7 can be manufactured. FIG. 9 is a sectional view showing still another embodiment according to the first aspect of the present invention. In the embodiment shown in FIG. 9, the first semiconductor layer and the second semiconductor layer are connected in series, and the TFT structure according to the third aspect of the present invention is obtained.

Referring to FIG. 9, a first semiconductor layer 42 is formed on an insulating substrate 41 made of glass, quartz or the like. The channel region 4 is formed in the second semiconductor layer 42.
A drain region 42b and a source region 42c are formed sandwiching 2a. The channel region 42a, the source region 42c, and the drain region 42b of the first semiconductor layer 42
The first insulating layer 4 made of SiO ₂ or the like is formed on a part of the
3 are formed. A gate electrode layer 44 is formed above the channel region 42a of the first insulating layer 43.

On the gate electrode layer 44 and the first insulating layer 4
A second insulating layer 45 made of SiO ₂ or the like is formed on the surface 3. A second semiconductor layer 46 is formed on the second insulating layer 45 and on the drain region 42b of the first semiconductor layer 42 where the first insulating layer 43 is not formed. A channel region 46a is formed above the gate electrode layer 44 of the second semiconductor layer 46, and the source region 46c and the drain region 4 are formed on both sides of the channel region 46a.
6b are formed. The source region 46c extends downward along the side surface portions of the second insulating layer 45 and the first insulating layer 43, and is electrically connected by directly contacting the drain region 42b of the first semiconductor layer 42. There is.

An inter-layer insulating film 47 made of SiN _x or the like is formed on the second semiconductor layer 46. A contact hole 47a is formed above the drain region 46b of the second semiconductor layer 46, and the contact hole 47a is formed.
A drain electrode 48 is formed so as to fill in a.
The lower end of the drain electrode 48 is electrically connected to the drain region 46b of the second semiconductor layer, and the upper end is exposed on the interlayer insulating film 47.

In this embodiment, the second semiconductor layer 46 is used.
Source region 46c and the drain region 42b of the first semiconductor layer 42 are electrically connected, and the first semiconductor layer 42 and the second semiconductor layer 46 are connected in series. The channel region 42a of the first semiconductor layer 42 is located below the gate electrode layer 44 with the first insulating layer 43 interposed therebetween. A channel region 46 of the second semiconductor layer 46 is provided above the gate electrode layer 44 with the second insulating layer 45 interposed therebetween.
a is located. Therefore, the channel regions 42a and 46 of the semiconductor layers 42 and 46 connected in series, respectively.
a is in a state in which it can be controlled by the gate electrode layer 44. Therefore, the common gate electrode layer 44 can control the first semiconductor layer 42 and the second semiconductor layer 46, and like the conventional double-gate structure TFT,
The leak current can be reduced. Since the first semiconductor layer 42 and the second semiconductor layer 46 have a stacked structure, the element size thereof can be made smaller than that of a conventional double-gate structure TFT.

FIG. 10 is a sectional view showing an example of a process for manufacturing the embodiment shown in FIG. With reference to FIG. 10A, a first semiconductor layer 42 made of, for example, polysilicon having a film thickness of 100 Å is formed on the substrate 41. On the first semiconductor layer 42, for example, SiO with a film thickness of 1000 Å
_A first insulating layer 43 composed of _two films is formed. On the first insulating layer 43, for example, an Al film having a film thickness of 2000 Å is formed by vapor deposition or the like. Al formed in this way
After forming a resist film 50a on the film, patterning the resist film 50a into a predetermined pattern,
By etching using the resist film 50a as a mask, the gate electrode layer 44 made of an Al film is formed in a predetermined region.
To form.

Next, using the resist film 50a as a mask, P
By ion implantation, a drain region 42b and a source region 42c are formed in the first semiconductor layer 42, and a channel region 42a is formed below the resist film 50a and the gate electrode layer 44.

Referring to FIG. 10B, the resist film 50
After removing a, the first insulating layer 43 and the gate electrode layer 4
A SiO ₂ film having a film thickness of 1000 Å, for example, is formed on the surface of the second insulating film 4 to form the second insulating film 45. This second insulating film 4
5 After forming a resist film on the entire surface by masking, patterning is performed by mask alignment so that the upper portion of the first semiconductor layer 42 other than the drain region 42b remains, as shown in FIG. 10B.

Referring to FIG. 10C, the second insulating layer 45 is formed using the patterned resist film 50b as a mask.
And the first insulating layer 43 is removed by etching,
The drain region 42b of the semiconductor layer 42 is exposed.

Referring to FIG. 10D, next, after removing the resist film 50b, the exposed drain region 42b and the second insulating layer 45 are made of, for example, polysilicon having a film thickness of 100 Å. The second semiconductor layer 46 is formed. A resist film is applied on the second semiconductor layer 46 so as to have a film thickness of 1 μm, for example, and then light is irradiated from the substrate 41 side to perform back exposure using the gate electrode layer 44 as a mask to form a gate. Patterning is performed so that only the upper portion of the electrode layer 44 is left. Thereby, the gate electrode layer 44
The resist film 50c is left only above.

Using this resist film 50c as a mask, P
Are ion-implanted to make the drain region 46b and the source region 46c of the second semiconductor layer 46 conductive. The conditions for ion implantation are, for example, 40 keV,
It can be performed at 5 × 10 ¹⁵ dose / cm ² . After ion implantation, heat treatment is performed at 900 ° C. for 1 hour as activation annealing treatment.

Referring to FIG. 10E, next, on the second semiconductor layer 46, for example, SiN _x having a film thickness of 4000 Å is formed.
To form the inter-layer insulating film 47. After forming the interlayer insulating film 47, hydrogen plasma treatment is performed. The conditions for the hydrogen plasma treatment are, for example, RF power 3
50W, total pressure 0.9Torr, substrate temperature 300
It is performed at a temperature of 2 hours for 2 hours.

Referring to FIG. 10F, next, a contact hole 47a is formed in the interlayer insulating film 47 above the drain region 46b. The drain electrode 48 is formed by depositing Al so as to fill the contact hole 47a. The lower end of the drain electrode 48 is electrically connected to the drain region 46b of the second semiconductor layer 46, and the upper end is exposed on the interlayer insulating film 47.

As described above, the TFT structure of the embodiment shown in FIG. 9 can be manufactured. 11 and 12
FIG. 8A is a sectional view and a plan view showing an example in which the TFT of the embodiment according to the present invention shown in FIG. In addition, FIG. 11 shows XX shown in FIG.
It is sectional drawing which follows the line. Referring to FIG. 11, substrate 31
The source region 32 of the first semiconductor layer 32 formed on the
The pixel electrode 51 is connected to c. As shown in FIG. 12, the data line 52 is connected to the drain electrode 39. As shown in FIG. 11, the drain electrode 39
Are electrically connected to the drain region 36 b of the second semiconductor layer 36, and the source region 3 of the second semiconductor layer 36.
6c is electrically connected to the drain region 32b of the first semiconductor layer 32 by the contact portion 38. Therefore,
As described above, the gate electrode layer 34 can control the channel regions 36a and 32a of the two semiconductor layers 36 and 32, and like the conventional double gate structure,
It is possible to reduce the leak current. As shown in FIG. 11, since it has a structure in which two semiconductor layers are stacked, the element size can be reduced as shown in FIG. 12 as compared with the case of using the conventional double gate structure TFT shown in FIG. can do. Therefore, the aperture ratio can be increased.

FIG. 13 is a sectional view showing an example in which the TFT of the embodiment shown in FIG. 1 according to the present invention is used as a driving element of a liquid crystal display. Referring to FIG. 13, a drain electrode 81 made of Al or the like extending from the data line is formed in contact hole 7a. The drain electrode 81 serves as the drain region 6 b of the second semiconductor layer 6.
And the drain region 2b of the first semiconductor layer 2 are electrically connected. A source electrode 82 made of Al or the like is formed in the contact hole 7b. The source electrode 82 is electrically connected to the source region 2c and the source region 6c. The display electrode 8 made of an ITO film or the like is electrically connected to the upper end of the source electrode 82.
3 is formed on the interlayer insulating film 7. The display electrode 83 is formed in a region corresponding to the pixel. An alignment film 84 is provided on the interlayer insulating film 7 and the display electrode 83. A liquid crystal layer 85 is provided on the alignment film 84. The liquid crystal layer 85 is held by being sandwiched between the liquid crystal layer 85 and the counter substrate 88. Inside the counter substrate 88,
A counter electrode 87 made of an ITO film or the like is formed, and an alignment film 86 is formed on the counter electrode 87.

FIG. 14 is a sectional view showing an example in which the TFT of the embodiment shown in FIG. 9 according to the present invention is used as a driving element of a liquid crystal display. In this embodiment, the drain region and the source region of the TFT of the embodiment shown in FIG. 9 are used in reverse. That is, in the first semiconductor layer 42, 42c is used as a drain region and 42b is used as a source region. Further, in the second semiconductor layer 46,
46c is used as a drain region and 46b is used as a source region. A source electrode 92 made of Al or the like is formed in the contact hole 47a. The source electrode 92 is electrically connected to the source region 46b. The display electrode 93 made of an ITO film or the like is formed so as to be electrically connected to the upper end portion of the source electrode 92.
It is provided above 7. The display electrode 93 is provided so as to correspond to the pixel region.

The drain region 42c of the first semiconductor layer 42
Are electrically connected to the data lines 91 formed on the substrate 41. An alignment film 94 is provided on the interlayer insulating film 47 and the display electrode 93. On the alignment film 94,
A liquid crystal layer 95 is provided. The liquid crystal layer 95 is held by being sandwiched between the liquid crystal layer 95 and the counter substrate 98.
A counter electrode 97 made of an ITO film or the like is formed inside the counter substrate 98, and an alignment film 96 is formed on the counter electrode 97.

In the above embodiment, the embodiment according to the first aspect in which two semiconductor layers are stacked and the gate electrode layer is arranged between the semiconductor layers, and the second embodiment in which the gate electrode layer is arranged on one side of the two stacked semiconductor layers. However, the number of stacked semiconductor layers may be three or more. In such a case, a gate electrode layer may be arranged between the respective semiconductor layers according to the first aspect, or a gate electrode layer may be arranged on one side of the stacked semiconductor layers according to the second aspect. Furthermore, according to the first aspect and the second aspect, a gate electrode layer is arranged between semiconductor layers for a combination of specific semiconductor layers, and one side of the semiconductor layers is provided for a combination of specific semiconductor layers. A gate electrode layer may be disposed in the.

[0101]

In the thin film transistor according to the first aspect of the present invention, the gate electrode layer is arranged between the first semiconductor layer and the second semiconductor layer, and the channel region of each semiconductor layer is a common gate electrode. It is controlled by layers. Therefore,
Even if the thickness of each semiconductor layer is reduced, a sufficient on-current can be secured, the leak current can be reduced, and a sufficient on-current can be secured.
The off ratio can be increased.

In the thin film transistor according to the second aspect of the present invention, the gate electrode layer is arranged on one side of the first semiconductor layer and the second semiconductor layer in which at least one electrical connection is formed. The common gate electrode layer controls the channel regions of the first semiconductor layer and the second semiconductor layer. Therefore, even if the thickness of each semiconductor layer is reduced, a sufficient on-current can be secured, the leak current can be reduced, and the on-current can be secured, so that the on / off ratio is increased. be able to.

According to the third aspect of the present invention, the first semiconductor layer and the second semiconductor layer are connected in series, and each such semiconductor layer can be controlled by the common gate electrode layer. . Therefore, the TFT can be operated similarly to the conventional double-gate structure TFT, the leakage current can be reduced, and the structure in which the first semiconductor layer and the second semiconductor layer are stacked is The element size can be reduced, the integration degree can be increased, and the density can be increased. Therefore, when such a TFT is used as a driving element of a liquid crystal display panel, the aperture ratio can be increased.

In the thin film transistor according to the fourth aspect of the present invention, the first semiconductor layer and the second semiconductor layer are connected in parallel, and a sufficient on-current can be obtained even if the semiconductor layer is thin. Since this can be ensured, the leak current can be reduced and the on-current can be secured.

In the manufacturing method according to the present invention, a resist film is applied onto the semiconductor layer, and back exposure is performed using the gate electrode layer as a mask to pattern the resist film,
Ion implantation is performed using the patterned resist film as a mask to form a source region and a drain region in the semiconductor layer. Therefore, the channel region, the source region, and the drain region can be formed by self-alignment with respect to the semiconductor layer formed over the gate electrode layer.

[Brief description of drawings]

FIG. 1 is a cross-sectional view showing one embodiment according to the first and fourth aspects of the present invention.

FIG. 2 is a cross-sectional view showing an example of a process for manufacturing the embodiment shown in FIG.

FIG. 3 is a sectional view showing another embodiment according to the first aspect and the fourth aspect of the present invention.

FIG. 4 is a cross-sectional view showing an example of a process for manufacturing the embodiment shown in FIG.

FIG. 5 is a cross-sectional view showing one embodiment according to the second aspect and the fourth aspect of the present invention.

FIG. 6 is a sectional view showing an example of a process for manufacturing the embodiment shown in FIG.

FIG. 7 is a cross-sectional view showing an embodiment according to the first aspect and the third aspect of the present invention.

FIG. 8 is a sectional view showing an example of a process for manufacturing the embodiment shown in FIG.

FIG. 9 is a sectional view showing another embodiment according to the first aspect and the third aspect of the present invention.

FIG. 10 is a sectional view showing an example of a process for manufacturing the embodiment shown in FIG.

11 is a sectional view showing an example in which the TFT of the embodiment shown in FIG. 7 is used as a driving element of a liquid crystal display.

FIG. 12 is a TF of the embodiment shown in FIG. 7, similar to FIG.
The top view which shows the state when T is used as a drive element of a liquid crystal display.

13 is a cross-sectional view showing a state in which the TFT of the embodiment shown in FIG. 1 is used as a driving element of a liquid crystal display.

14 is a sectional view showing a state in which the TFT of the embodiment shown in FIG. 9 is used as a driving element of a liquid crystal display.

FIG. 15 is a sectional view showing a conventional TFT.

FIG. 16 is a cross-sectional view showing a conventional double-gate structure TFT.

FIG. 17 is a conventional double-gate structure TF shown in FIG.
Sectional drawing which shows the state which used T as a drive element of a liquid crystal display.

FIG. 18 is a plan view showing a state in which a conventional double-gate structure TFT is used as a drive element of a liquid crystal display, as in FIG.

[Explanation of symbols]

1, 11, 21, 31, 41, ... Substrate 2, 12, 22, 32, 42 ... First semiconductor layer 2a, 12a, 22a, 32a, 42a ... Channel region 2b, 12b, 22b, 32b, 42b ... Drain region 2c, 12c, 22c, 32c, 42c ... Source region 3, 13, 23, 33, 43 ... First insulating layer 4, 14, 24, 34, 44 ... Gate electrode layer 5, 15, 25, 35, 45 ... Second insulating layer 6, 16, 26, 36, 46, ... Second semiconductor layer 6a, 16a, 26a, 36a, 46a ... Channel region 6b, 16b, 26b, 36b, 46b ... Drain region 6c, 16c, 26c , 36c, 46c ... Source region 7, 17, 27, 37, 47 ... Interlayer insulating film 7a, 7b, 17a, 17b, 27a, 27b, 37
a, 47a ... Contact hole 8, 18, 28, 48 ... Drain electrode 9, 19, 29 ... Source electrode 38 ... Contact part

─────────────────────────────────────────────────── ─── Continuation of the front page (51) Int.Cl. ⁶ Identification code Internal reference number FI technical display location 9056-4M 618 D

Claims (6)

[Claims] 1. A gate electrode layer, a first semiconductor layer in which a source region and a drain region are formed so as to sandwich a channel region, and the channel region is formed at a position facing the gate electrode layer, and the gate electrode layer. A first insulating layer provided between the first semiconductor layer and a channel region of the first semiconductor layer, a source region and a drain region sandwiching the channel region, and the gate electrode layer sandwiched between the first insulating layer and the first semiconductor layer. A second semiconductor layer which is provided on a side and a channel region of which is formed at a position facing the gate electrode layer, and a second semiconductor layer which is provided between the gate electrode layer and the channel region of the second semiconductor layer. A thin film transistor comprising two insulating layers, wherein at least one electrical connection is formed between the first semiconductor layer and the second semiconductor layer. 2. A gate electrode layer, a first semiconductor layer in which a source region and a drain region are formed sandwiching a channel region, and the channel region is formed at a position facing the gate electrode layer, and the gate electrode layer. A first insulating layer provided between the first insulating layer and a channel region of the first semiconductor layer, and a source region and a drain region sandwiching the channel region, the outside of the first semiconductor layer with respect to the gate electrode layer. A second semiconductor layer, which is provided at a position corresponding to the gate electrode layer and the channel region of the first semiconductor layer, and the first semiconductor layer and the second semiconductor layer. A second insulating layer formed between the first semiconductor layer and the second semiconductor layer, wherein at least one electrical connection is formed between the first semiconductor layer and the second semiconductor layer. 3. The first semiconductor layer and the second semiconductor layer are formed by forming an electrical connection between the source region and the drain region of the first semiconductor layer and the second semiconductor layer. The thin film transistor according to claim 1, wherein and are connected in series. 4. The first semiconductor layer and the second semiconductor layer are formed by forming electrical connections between the source regions and the drain regions of the first semiconductor layer and the second semiconductor layer, respectively. 1 or 2 are connected in parallel
The thin film transistor according to. 5. An insulating layer is formed on the gate electrode layer, a semiconductor layer is formed on the insulating layer, and the channel region is formed so that the region of the semiconductor layer above the gate electrode layer becomes a channel region. A method of manufacturing a thin film transistor, in which a semiconductor layer region on both sides is doped with impurities to form a source region and a drain region, a step of applying a resist film on the semiconductor layer, and back exposure using the gate electrode layer as a mask A method of manufacturing a thin film transistor, comprising the steps of patterning the resist film thereby, and forming the source region and the drain region in the semiconductor layer by ion implantation using the resist film left by the patterning as a mask. 6. A step of forming a first semiconductor layer on a substrate, a step of forming a first insulating film on the first semiconductor layer, and a gate electrode on the first insulating film. A step of forming a layer, a step of forming a second insulating film on the gate electrode layer, a step of forming a second semiconductor layer on the second insulating film, the second semiconductor Applying a resist film on the layer, patterning the resist film by back exposure using the gate electrode layer as a mask, and ion implanting the resist film left by the patterning as a mask Forming a source region and a drain region in the second semiconductor layer.