CN110690257A - TFT array substrate and manufacturing method thereof - Google Patents
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- 238000002161 passivation Methods 0.000 claims abstract description 31
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- 239000011521 glass Substances 0.000 claims description 53
- 230000004888 barrier function Effects 0.000 claims description 27
- 229910052760 oxygen Inorganic materials 0.000 claims description 24
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- 239000003990 capacitor Substances 0.000 claims description 17
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Abstract
The invention relates to the technical field of array substrates, in particular to a TFT array substrate and a manufacturing method thereof.A first active layer is arranged between a first drain electrode metal layer and a first passivation layer, so that the active layer can be prevented from being damaged by the film formation of the first drain electrode metal layer and the etching process to form a coplanar TFT structure; the first through hole is formed in the first source electrode insulating layer, the second through hole is formed in the gate insulating layer, the second through hole and the first through hole are arranged oppositely and communicated, the active layers are filled in the first through hole and the second through hole, the critical dimension of the thin film transistor channel manufacturing process can be shortened, the occupied area of the whole device is reduced, the bending resistance of the array substrate can be effectively improved, the pixel area and the frame size of the display panel can be reduced, and the display panel is more suitable for being applied to a high-resolution flexible panel.
Description
Technical Field
The invention relates to the technical field of array substrates, in particular to a TFT array substrate and a manufacturing method thereof.
Background
An Organic Light Emitting Diode (OLED) has the advantages of self-luminescence, wide viewing angle, high contrast, low power consumption, high response rate, full color, simple process, etc., and an Active-matrix Organic Light Emitting Diode (AMOLED) using a flexible backplane material can make a display product lighter or thinner, and can be bent and not easily damaged, which is a trend of future display development of OLEDs.
At present, the luminous efficiency and stability of the OLED can meet the requirements of middle and small-size display, and the OLED is widely applied to the fields of instruments and smart phones; large-sized OLED televisions have also begun to enter the market. Since the OLED is an all-solid-state thin-film device and is made of organic materials and amorphous materials, the OLED has natural advantages in flexible devices, and is also an important technology in the field of wearable smart devices. The OLED is an all-solid-state device, and can also work normally in the process of bending and folding, so that a flexible device is easy to prepare.
From the technology development stage, the flexible display can be divided into three stages, namely a bendable screen, a foldable screen and a free flexible screen. Currently, the mainstream of OLED display technology is active driving OLED (amoled) technology. Most flexible OLED products are still in the primary flexible screen stage, and the development in this stage is mainly performed around several key technical points, namely, a flexible substrate, a flexible TFT backplane, a flexible OLED light emitting layer and a thin film package. How to manufacture a high reliability package structure similar to a glass package on a flexible display and provide a flexing characteristic is the most important issue for improving the service life of the flexible AMOLED.
Disclosure of Invention
The technical problem to be solved by the invention is as follows: a TFT array substrate capable of effectively improving the bending resistance of the array substrate and a manufacturing method thereof are provided.
In order to solve the above technical problems, a first technical solution adopted by the present invention is:
a TFT array substrate comprises a TFT area structure, wherein the TFT area structure comprises a first glass substrate, and a first flexible substrate, a first water-oxygen blocking layer, a first buffer layer, a first source electrode metal layer, a first source electrode insulating layer, a grid electrode metal layer, a grid electrode insulating layer, a first drain electrode metal layer, an active layer and a first passivation layer are sequentially stacked on the surface of the first glass substrate;
the first source electrode insulating layer is provided with a first via hole, the grid electrode insulating layer is provided with a second via hole, the second via hole is opposite to the first via hole and communicated with the first via hole, the active layer is filled in the first via hole and the second via hole, and the active layer filled in the first via hole is in contact with the first source electrode metal layer.
The second technical scheme adopted by the invention is as follows:
a manufacturing method of a TFT array substrate comprises the following steps:
s1, providing a first glass substrate of a TFT area structure, and covering the surface of the first glass substrate with a first flexible substrate;
s2, forming a first water and oxygen barrier layer and covering the surface of the first flexible substrate;
s3, forming a first buffer layer, and covering the surface of the first water-oxygen barrier layer;
s4, forming a first source electrode metal layer and covering the surface of the first buffer layer;
s5, forming a first source electrode insulating layer, and covering the surface of the first source electrode metal layer;
s6, forming a gate metal layer and covering the surface of the first source electrode insulating layer;
s7, forming a gate insulating layer and covering the surface of the gate metal layer;
s8, forming a first via hole in the first source insulating layer, and forming a second via hole in the gate insulating layer, wherein the second via hole is opposite to and communicated with the first via hole;
s9, forming a first drain metal layer covering the surface of the gate insulation layer;
s10, forming an active layer which covers the surface of the first drain electrode metal layer and is in contact with one side face, far away from the first glass substrate, of the gate insulating layer; the first via hole and the second via hole are both filled with active layers, and the active layers filled in the first via hole are in contact with one side face, far away from the first glass substrate, of the first source electrode metal layer;
and S11, forming a first passivation layer which covers the surface of the active layer and is in contact with the first drain electrode metal layer.
The invention has the beneficial effects that:
the first through hole is formed in the first source electrode insulating layer, the second through hole is formed in the gate electrode insulating layer, the second through hole and the first through hole are arranged oppositely and communicated, the active layer is filled in the first through hole and the second through hole, the active layer is connected with the source electrode, the critical dimension (CD for short) of a thin film transistor channel manufacturing process can be shortened through the TFT device with a vertical structure, the occupied area of the whole device is reduced, the bending resistance of the array substrate can be effectively improved, the pixel area and the frame size of the display panel can be reduced, and the array substrate is more suitable for being applied to a high-resolution flexible panel.
Drawings
Fig. 1 is a schematic structural view of a TFT array substrate according to the present invention;
FIG. 2 is a schematic structural diagram of a second embodiment of a TFT array substrate according to the present invention;
FIG. 3 is a schematic structural diagram of a third embodiment of a TFT array substrate according to the present invention;
FIG. 4 is a schematic structural diagram of a TFT array substrate according to the present invention;
FIG. 5 is a structural diagram of a portion of a structural layer of a capacitor region structure of a TFT array substrate according to the present invention;
FIG. 6 is a schematic structural diagram of a TFT array substrate according to the present invention;
fig. 7 is a flowchart illustrating a method of fabricating a TFT array substrate according to the present invention.
Description of reference numerals:
1. a TFT region structure; 101. a first glass substrate; 102. a first flexible substrate; 103. a first water oxygen barrier layer; 104. a first buffer layer; 105. a first source metal layer; 106. a first source insulating layer; 107. a gate metal layer; 108. a gate insulating layer; 109. a first drain metal layer; 110. an active layer; 111. a first passivation layer; 112. etching the barrier layer; 113. a top gate metal layer;
2. a capacitive area structure; 201. a second glass substrate; 202. a second flexible substrate; 203. a second aqueous oxygen barrier layer; 204. a second buffer layer; 205. a second source metal layer; 206. a second source insulating layer; 207. a second drain metal layer; 208. a second passivation layer.
Detailed Description
In order to explain technical contents, achieved objects, and effects of the present invention in detail, the following description is made with reference to the accompanying drawings in combination with the embodiments.
The most key concept of the invention is as follows: the active layer is arranged between the first drain electrode metal layer and the first passivation layer, so that the active layer can be prevented from being damaged by the first drain electrode metal layer to form a coplanar TFT structure by film formation and etching processes; the first through hole is formed in the first source electrode insulating layer, the second through hole is formed in the gate insulating layer, the second through hole and the first through hole are arranged oppositely and communicated, and the active layers are filled in the first through hole and the second through hole, so that the bending resistance of the array substrate can be effectively improved.
Referring to fig. 1, a technical solution provided by the present invention:
a TFT array substrate comprises a TFT area structure, wherein the TFT area structure comprises a first glass substrate, and a first flexible substrate, a first water-oxygen blocking layer, a first buffer layer, a first source electrode metal layer, a first source electrode insulating layer, a grid electrode metal layer, a grid electrode insulating layer, a first drain electrode metal layer, an active layer and a first passivation layer are sequentially stacked on the surface of the first glass substrate;
the first source electrode insulating layer is provided with a first via hole, the grid electrode insulating layer is provided with a second via hole, the second via hole is opposite to the first via hole and communicated with the first via hole, the active layer is filled in the first via hole and the second via hole, and the active layer filled in the first via hole is in contact with the first source electrode metal layer.
From the above description, the beneficial effects of the present invention are:
the first through hole is formed in the first source electrode insulating layer, the second through hole is formed in the gate electrode insulating layer, the second through hole and the first through hole are arranged oppositely and communicated, the active layer is filled in the first through hole and the second through hole, the active layer is connected with the source electrode, the critical dimension (CD for short) of a thin film transistor channel manufacturing process can be shortened through the TFT device with a vertical structure, the occupied area of the whole device is reduced, the bending resistance of the array substrate can be effectively improved, the pixel area and the frame size of the display panel can be reduced, and the array substrate is more suitable for being applied to a high-resolution flexible panel.
Furthermore, the TFT area structure further includes an etching blocking layer disposed between the active layer and the first passivation layer, and the etching blocking layer is in contact with a side of the active layer away from the first glass substrate and a side of the first passivation layer close to the first glass substrate, respectively.
As can be seen from the above description, by providing the etching stopper layer, the active layer channel can be protected from being damaged during the film formation and etching of the first drain metal layer, thereby improving the stability of the TFT device.
Further, the TFT area structure further includes a top gate metal layer, the top gate metal layer is disposed between the etching stop layer and the first passivation layer, and the top gate metal layer is in contact with the etching stop layer and the first passivation layer, respectively.
As can be seen from the above description, the gate metal layer is a bottom gate of a Thin Film Transistor (TFT) device, the top gate metal layer is a top gate of the TFT device, and the gate metal layer and the top gate metal layer form a TFT device with a dual-gate structure, where the TFT device with the dual-gate structure has higher electron mobility and device stability than the TFT device with a single-gate structure; the top gate metal layer and the first drain electrode metal layer are structural layers formed at the same time, the top gate metal layer is formed while the first drain electrode metal layer is formed, and the top gate metal layer can be formed only by one photomask, so that the occupied area of the TFT device is further reduced by optimizing the TFT device, and the cost can be saved.
Further, still include the regional structure of electric capacity, the regional structure of electric capacity includes the second glass substrate stacks gradually on the surface and is equipped with flexible substrate of second, second water oxygen barrier layer, second buffer layer and second source metal layer, be equipped with the third via hole more than two on the second buffer layer, and more than two all pack in the third via hole and have the second source metal layer, the second source metal layer of packing in the third via hole with the second water oxygen barrier layer is kept away from a side contact of second glass substrate, the second source metal layer is kept away from stack gradually on a side of first glass substrate and is equipped with second source insulating layer, second drain metal layer and second passivation layer.
As can be seen from the above description, the capacitor with the three-dimensional structure has a better effect of dispersing mechanical stress than a conventional flat-plate capacitor by arranging the two or more third via holes in the second buffer layer of the capacitor region structure, and the film layer is not easily broken and falls off when the array substrate is bent, so that the array substrate has stronger bending resistance; under the condition of keeping the effective area equal, the capacitance of the three-dimensional structure can be improved by 50 percent compared with the capacitance of a flat plate capacitor.
Further, the vertical cross section of the third via hole is in the shape of an isosceles trapezoid.
As can be seen from the above description, the vertical cross-section of the third via is formed in an isosceles trapezoid shape, which can effectively reduce the area of the capacitor.
Referring to fig. 6, another technical solution provided by the present invention:
a manufacturing method of a TFT array substrate comprises the following steps:
s1, providing a first glass substrate of a TFT area structure, and covering the surface of the first glass substrate with a first flexible substrate;
s2, forming a first water and oxygen barrier layer and covering the surface of the first flexible substrate;
s3, forming a first buffer layer, and covering the surface of the first water-oxygen barrier layer;
s4, forming a first source electrode metal layer and covering the surface of the first buffer layer;
s5, forming a first source electrode insulating layer, and covering the surface of the first source electrode metal layer;
s6, forming a gate metal layer and covering the surface of the first source electrode insulating layer;
s7, forming a gate insulating layer and covering the surface of the gate metal layer;
s8, forming a first via hole in the first source insulating layer, and forming a second via hole in the gate insulating layer, wherein the second via hole is opposite to and communicated with the first via hole;
s9, forming a first drain metal layer covering the surface of the gate insulation layer;
s10, forming an active layer which covers the surface of the first drain electrode metal layer and is in contact with one side face, far away from the first glass substrate, of the gate insulating layer; the first via hole and the second via hole are both filled with active layers, and the active layers filled in the first via hole are in contact with one side face, far away from the first glass substrate, of the first source electrode metal layer;
and S11, forming a first passivation layer which covers the surface of the active layer and is in contact with the first drain electrode metal layer.
From the above description, the beneficial effects of the present invention are:
the active layer is arranged between the first drain electrode metal layer and the first passivation layer, so that the active layer can be prevented from being damaged by the first drain electrode metal layer to form a coplanar TFT structure by film formation and etching processes; through set up first via hole on first source insulating layer, set up the second via hole on the gate insulating layer, the second via hole sets up and communicates with each other with first via hole relatively, all pack in first via hole and the second via hole and have the active layer, can shorten the critical dimension (CD for short) of thin film transistor channel processing procedure to reach the area occupied of reducing whole device, can effectively improve array substrate bending resistance ability, and can also reduce pixel area and display panel frame size, more be fit for using in high resolution flexible panel.
Further, the following steps are included between step S9 and step S10:
and forming an etching barrier layer and covering the surface of the active layer.
Further, the following steps are included between step S10 and step S11:
as can be seen from the above description, a top gate metal layer is formed and covers the surface of the etching barrier layer.
The grid metal layer is a bottom grid electrode of a Thin Film Transistor (TFT) device, the top grid metal layer is a top grid electrode of the TFT device, the grid metal layer and the top grid metal layer form the TFT device with a double-grid structure, and the TFT device with the double-grid structure has higher electron mobility and device stability compared with the TFT device with a single-grid structure; the top gate metal layer and the first drain electrode metal layer are structural layers formed at the same time, the top gate metal layer is formed while the first drain electrode metal layer is formed, and the top gate metal layer can be formed only by one photomask, so that the occupied area of the TFT device is further reduced by optimizing the TFT device, and the cost can be saved.
Referring to fig. 1, fig. 4 and fig. 5, a first embodiment of the present invention is:
a TFT array substrate comprises a TFT area structure 1, wherein the TFT area structure 1 comprises a first glass substrate 101, and a first flexible substrate 102, a first water oxygen barrier layer 103, a first buffer layer 104, a first source metal layer 105, a first source insulating layer 106, a gate metal layer 107, a gate insulating layer 108, a first drain metal layer 109, an active layer 110 and a first passivation layer 111 are sequentially stacked on the surface of the first glass substrate 101;
the first source electrode insulating layer 106 is provided with a first via hole, the gate insulating layer 108 is provided with a second via hole, the second via hole is opposite to and communicated with the first via hole, the first via hole and the second via hole are both filled with the active layer 110, and the active layer 110 filled in the first via hole is in contact with the first source electrode metal layer 105.
Still include electric capacity regional structure 2, electric capacity regional structure 2 includes second glass substrate 201 stacks gradually on the surface and is equipped with second flexible substrate 202, second water oxygen barrier layer, second buffer layer 204 and second source metal layer 205, be equipped with the third via hole more than two on the second buffer layer 204, and more than two all fill in the third via hole and have second source metal layer 205, the second source metal layer 205 of filling in the third via hole with second water oxygen barrier layer 203 keeps away from a side contact of second glass substrate 201, second source metal layer 205 is kept away from it is equipped with second source insulating layer 206, second drain metal layer 207 and second passivation layer 208 to stack gradually on a side of first glass substrate 101.
The vertical section of the third via hole is in an isosceles trapezoid shape.
The second source metal layer 205 and the second drain metal layer 207 constitute upper and lower electrode plates of a capacitor, and the thickness of the second source insulating layer 206 is the capacitance distance of the capacitor.
The capacitor designed by the invention is of a three-dimensional structure, and the structural arrangement of the capacitor of the three-dimensional structure can be grid-shaped arrangement: such as rectangular and long curved shapes, etc.;
a distributed arrangement is possible: any polygon (triangle, rectangle, pentagon, hexagon, etc.), curve (circle, ellipse, etc.).
The shape of the capacitor array of the three-dimensional structure refers to a planar direction of the array substrate.
In the actual process, the first glass substrate 101 and the second glass substrate 201 are the same layer of glass substrate distributed in different areas, and are formed during the evaporation process;
the first flexible substrate 102 and the second flexible substrate 202 are the same layer of flexible substrates distributed in different areas, and are formed by being simultaneously manufactured during a photoresist coating process, and the flexible substrates are made of polyimide (polyimide, abbreviated as PI);
the first water-oxygen barrier layer 103 and the second water-oxygen barrier layer 203 are the same water-oxygen barrier layer distributed in different areas, and are formed by simultaneously performing a Chemical Vapor Deposition (CVD) process, wherein the water-oxygen barrier layer is made of silicon nitride, hexagonal boron nitride and the like;
the first buffer layer 104 and the second buffer layer 204 are the same buffer layer distributed in different regions, and are formed by simultaneously performing photoresist coating or Chemical Vapor Deposition (CVD) or Physical Vapor Deposition (PVD) processes, wherein the buffer layers are made of organic photosensitive materials, SiOx, SiNx, titanium oxide, aluminum oxide, and the like;
the first source metal layer 105 and the second source metal layer 205 are the same source metal layer distributed in different regions, and are formed by performing a Chemical Vapor Deposition (CVD) process or a Physical Vapor Deposition (PVD) process at the same time, in order to improve the bending resistance of the flexible array substrate, the source metal layer is preferably made of graphene, carbon nanotubes, silver nanowires, and other materials, and in view of the current technology of highly conductive bending-resistant materials, the source metal layer may also be made of one or more metals with excellent conductivity, such as aluminum, molybdenum, titanium, nickel, copper, silver, chromium, and alloys;
the first source insulating layer 106 and the second source insulating layer 206 are the same source insulating layer distributed in different regions, and are formed simultaneously by performing photoresist coating or Chemical Vapor Deposition (CVD) or Physical Vapor Deposition (PVD) processes, and the source insulating layers are made of SiOx, SiNx, titanium oxide, aluminum oxide, or the like;
the first drain metal layer 109 and the second drain metal layer 207 are the same drain metal layer distributed in different regions, and are formed simultaneously by performing a Chemical Vapor Deposition (CVD) process or a Physical Vapor Deposition (PVD) process, and the drain metal layer is made of the same material as the source metal layer;
the first passivation layer 111 and the second passivation layer 208 are the same passivation layer distributed in different regions, and are formed simultaneously during the evaporation process, and the material of the passivation layer is the same as that of the source electrode insulating layer;
the material of the gate metal layer 107 is the same as that of the source metal layer;
the material of the gate insulating layer 108 is the same as that of the source insulating layer;
the active layer 110 is made of IGZO;
the material of the etch stop layer 112 is the same as that of the source insulating layer.
Referring to fig. 4, since the active layer 110 is mainly attached to the sidewall of the gate metal layer 107, the included angle α of the gate metal layer 107 is controlled between 30-90 ° according to the trigonometric function relationship in consideration of the practical effect of shortening the channel length and the adhesion of the active layer 110:
l ═ Sin α × H, where L is the channel length of the active layer 110109 and H is the actual occupied channel length of the active layer 110;
if α is 60 °, H is 1/2L, that is, 1/2 of the length actually occupied by the channel of the active layer 110 is equal to the channel length of the active layer 110.
The structure diagram of fig. 4 can reduce the critical dimension of the TFT channel process by using the TFT with a three-dimensional structure, so as to reduce the occupied area of the whole device, increase the number of Pixels Per Inch of the panel (the pixel number Per Inch is called Pixels Per Inch, abbreviated as PPI), reduce the contact area between the TFT device and the glass substrate, reduce the damage of the mechanical shear stress when the flexible substrate is bent, and improve the bending resistance of the TFT device.
Referring to fig. 5, assuming that the vertical cross-sectional shape of the third via is an isosceles trapezoid, and S represents the area of the capacitor structure, S is (S1+ S2+ S3+ S4) × n;
s 'represents the actual occupied area of the capacitor structure, and S' (S1'+ S2+ S3+ S4') × n;
according to a trigonometric function, S1 ═ Sin β S1, where S1 ═ S2 ═ S3, β ═ 60 °, S4 ═ S1 ═ S2 ═ S3, S4 ═ S1 ═ 2 ═ S1 ═ 2 ═ S2;
from the above available S ' ((S1 ' + S2+ S3+ S4 ')/n ═ S2+ S2+ S2+ S2): 4 ═ S2 ═ n;
S＝(S1+S2+S3+S4)*n＝(2*S2+S2+S2+2*S2)*n＝6*S2*n；
S-S'＝2*S2*n；
therefore, the actual occupied area of the capacitor structure can be reduced compared with the area of the flat plate capacitor before improvement: (2 × S2 × n)/(6 × S2 × n) ═ 33.3%.
Referring to fig. 2, the second embodiment of the present invention is:
the difference between the second embodiment and the first embodiment is that: the TFT area structure 1 further includes an etching blocking layer 112, the etching blocking layer 112 is disposed between the active layer 110 and the first passivation layer 111, and the etching blocking layer 112 is in contact with a side of the active layer 110 away from the first glass substrate 101 and a side of the first passivation layer 111 close to the first glass substrate 101, respectively.
Referring to fig. 6, a curved array substrate is shown, wherein the structure layer corresponds to the structure layer of fig. 2; since the first glass substrate 101 and the second glass substrate 201 are separated from the flexible array substrate by laser light at the final process of the TFT array substrate, the first glass substrate 101 and the second glass substrate 201 are removed from the cross-sectional structure of the curved array substrate in fig. 6, that is, the first glass substrate 101 and the second glass substrate 201 are not bendable.
Referring to fig. 3, a third embodiment of the present invention is:
the difference between the third embodiment and the first embodiment is that: the TFT region structure 1 further includes a top gate metal layer 113, wherein the top gate metal layer 113 is disposed between the etch stop layer 112 and the first passivation layer 111, and the top gate metal layer 113 is in contact with the etch stop layer 112 and the first passivation layer 111, respectively.
Referring to fig. 7, a fourth embodiment of the present invention is:
a manufacturing method of a TFT array substrate comprises the following steps:
s1, providing a first glass substrate 101 of the TFT area structure 1, and covering the surface of the first glass substrate 101 with a first flexible substrate 102;
s2, forming a first water and oxygen barrier layer 103, and covering the surface of the first flexible substrate 102;
s3, forming a first buffer layer 104 covering the surface of the first water oxygen barrier layer 103;
s4, forming a first source metal layer 105 covering the surface of the first buffer layer 104;
s5, forming a first source insulating layer 106 covering the surface of the first source metal layer 105;
s6, forming a gate metal layer 107 covering the surface of the first source insulating layer 106;
s7, forming a gate insulation layer 108 covering the surface of the gate metal layer 107;
s8, forming a first via hole in the first source insulating layer 106, and forming a second via hole in the gate insulating layer 108, the second via hole being opposite to and communicating with the first via hole;
s9, forming a first drain metal layer 109 covering the surface of the gate insulation layer 108;
s10, forming an active layer 110 covering the surface of the first drain metal layer 109, wherein the active layer 110 contacts with a side of the gate insulating layer 108 away from the first glass substrate 101; the first via hole and the second via hole are both filled with active layers 110, and the active layers 110 filled in the first via hole are in contact with one side surface, away from the first glass substrate 101, of the first source metal layer 105;
s11, forming a first passivation layer 111 covering the surface of the active layer 110 and contacting the first drain metal layer 109.
The following steps are also included between step S9 and step S10:
an etch stop layer 112 is formed and covers the surface of the active layer 110. The patterns of the active layer 110 and the etching stop layer 112 can be defined by two etching processes using a gray tone mask, which saves one mask;
the following steps are also included between step S10 and step S11:
a top gate metal layer 113 is formed and covers the surface of the etch stop layer 112.
In summary, according to the TFT array substrate and the manufacturing method thereof provided by the present invention, the first via hole is formed on the first source insulating layer, the second via hole is formed on the gate insulating layer, the second via hole is opposite to and communicated with the first via hole, and the active layer is filled in both the first via hole and the second via hole, so that the active layer is connected to the source electrode, and the Critical Dimension (CD for short) of the TFT channel process can be shortened by forming the TFT device with the vertical structure, thereby reducing the occupied area of the whole device, effectively improving the bending resistance of the array substrate, and reducing the pixel area and the frame size of the display panel, and being more suitable for being applied to the high-resolution flexible panel.
The above description is only an embodiment of the present invention, and not intended to limit the scope of the present invention, and all equivalent changes made by using the contents of the present specification and the drawings, or applied directly or indirectly to the related technical fields, are included in the scope of the present invention.
Claims (8)
1. The TFT array substrate is characterized by comprising a TFT area structure, wherein the TFT area structure comprises a first glass substrate, and a first flexible substrate, a first water oxygen barrier layer, a first buffer layer, a first source metal layer, a first source insulating layer, a gate metal layer, a gate insulating layer, a first drain metal layer, an active layer and a first passivation layer are sequentially stacked on the surface of the first glass substrate;
the first source electrode insulating layer is provided with a first via hole, the grid electrode insulating layer is provided with a second via hole, the second via hole is opposite to the first via hole and communicated with the first via hole, the active layer is filled in the first via hole and the second via hole, and the active layer filled in the first via hole is in contact with the first source electrode metal layer.
2. The TFT array substrate of claim 1, wherein the TFT area structure further comprises an etch stop layer disposed between the active layer and the first passivation layer, the etch stop layer being in contact with a side of the active layer away from the first glass substrate and a side of the first passivation layer adjacent to the first glass substrate, respectively.
3. The TFT array substrate of claim 2, wherein the TFT area structure further comprises a top gate metal layer disposed between and in contact with the etch stop layer and the first passivation layer, respectively.
4. The TFT array substrate of claim 1, further comprising a capacitor area structure, wherein the capacitor area structure comprises a second glass substrate, a second flexible substrate, a second water-oxygen barrier layer, a second buffer layer and a second source metal layer are sequentially stacked on the surface of the second glass substrate, more than two third via holes are formed in the second buffer layer, the more than two third via holes are filled with the second source metal layer, the second source metal layer filled in the third via holes is in contact with one side face, away from the second glass substrate, of the second water-oxygen barrier layer, and a second source insulating layer, a second drain metal layer and a second passivation layer are sequentially stacked on one side face, away from the first glass substrate, of the second source metal layer.
5. The TFT array substrate of claim 1, wherein the third via has a vertical cross-section that is shaped as an isosceles trapezoid.
6. A manufacturing method of a TFT array substrate is characterized by comprising the following steps:
s1, providing a first glass substrate of a TFT area structure, and covering the surface of the first glass substrate with a first flexible substrate;
s2, forming a first water and oxygen barrier layer and covering the surface of the first flexible substrate;
s3, forming a first buffer layer, and covering the surface of the first water-oxygen barrier layer;
s4, forming a first source electrode metal layer and covering the surface of the first buffer layer;
s5, forming a first source electrode insulating layer, and covering the surface of the first source electrode metal layer;
s6, forming a gate metal layer and covering the surface of the first source electrode insulating layer;
s7, forming a gate insulating layer and covering the surface of the gate metal layer;
s8, forming a first via hole in the first source insulating layer, and forming a second via hole in the gate insulating layer, wherein the second via hole is opposite to and communicated with the first via hole;
s9, forming a first drain metal layer covering the surface of the gate insulation layer;
s10, forming an active layer which covers the surface of the first drain electrode metal layer and is in contact with one side face, far away from the first glass substrate, of the gate insulating layer; the first via hole and the second via hole are both filled with active layers, and the active layers filled in the first via hole are in contact with one side face, far away from the first glass substrate, of the first source electrode metal layer;
and S11, forming a first passivation layer which covers the surface of the active layer and is in contact with the first drain electrode metal layer.
7. The method of claim 6, further comprising the steps of, between the step S9 and the step S10:
and forming an etching barrier layer and covering the surface of the active layer.
8. The method of claim 7, further comprising the steps of, between step S10 and step S11:
and forming a top grid metal layer and covering the surface of the etching barrier layer.
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