KR100349913B1 - Method for manufacturing Poly silicon thin film transistor - Google Patents
Method for manufacturing Poly silicon thin film transistor Download PDFInfo
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- KR100349913B1 KR100349913B1 KR1020000022429A KR20000022429A KR100349913B1 KR 100349913 B1 KR100349913 B1 KR 100349913B1 KR 1020000022429 A KR1020000022429 A KR 1020000022429A KR 20000022429 A KR20000022429 A KR 20000022429A KR 100349913 B1 KR100349913 B1 KR 100349913B1
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- 238000000034 method Methods 0.000 title claims abstract description 32
- 229910021420 polycrystalline silicon Inorganic materials 0.000 title claims abstract description 25
- 239000010409 thin film Substances 0.000 title claims abstract description 22
- 229920005591 polysilicon Polymers 0.000 title claims abstract description 20
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 18
- 239000010410 layer Substances 0.000 claims abstract description 65
- 229910021417 amorphous silicon Inorganic materials 0.000 claims abstract description 38
- 238000000059 patterning Methods 0.000 claims abstract description 9
- 239000002184 metal Substances 0.000 claims abstract description 7
- 238000010030 laminating Methods 0.000 claims abstract description 5
- 238000000151 deposition Methods 0.000 claims abstract description 4
- 239000011241 protective layer Substances 0.000 claims abstract description 4
- 230000003213 activating effect Effects 0.000 claims abstract description 3
- 150000002500 ions Chemical class 0.000 claims description 10
- 239000000758 substrate Substances 0.000 claims description 7
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims description 2
- 229910052710 silicon Inorganic materials 0.000 claims description 2
- 239000010703 silicon Substances 0.000 claims description 2
- 238000005530 etching Methods 0.000 abstract description 7
- 239000004065 semiconductor Substances 0.000 abstract description 7
- 230000000694 effects Effects 0.000 abstract 1
- 239000010408 film Substances 0.000 description 6
- 238000005468 ion implantation Methods 0.000 description 4
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- 230000007547 defect Effects 0.000 description 2
- 239000002019 doping agent Substances 0.000 description 2
- 239000011229 interlayer Substances 0.000 description 2
- 239000004973 liquid crystal related substance Substances 0.000 description 2
- 239000011159 matrix material Substances 0.000 description 2
- 238000000206 photolithography Methods 0.000 description 2
- 238000000623 plasma-assisted chemical vapour deposition Methods 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000011109 contamination Methods 0.000 description 1
- 238000011161 development Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000012986 modification Methods 0.000 description 1
- 230000004048 modification Effects 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000027756 respiratory electron transport chain Effects 0.000 description 1
- 238000003079 width control Methods 0.000 description 1
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- H—ELECTRICITY
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- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/02104—Forming layers
- H01L21/02365—Forming inorganic semiconducting materials on a substrate
- H01L21/02656—Special treatments
- H01L21/02664—Aftertreatments
- H01L21/02667—Crystallisation or recrystallisation of non-monocrystalline semiconductor materials, e.g. regrowth
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- H01L29/66007—Multistep manufacturing processes
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- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
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- H—ELECTRICITY
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- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
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- H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78651—Silicon transistors
- H01L29/7866—Non-monocrystalline silicon transistors
- H01L29/78672—Polycrystalline or microcrystalline silicon transistor
- H01L29/78675—Polycrystalline or microcrystalline silicon transistor with normal-type structure, e.g. with top gate
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- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/136231—Active matrix addressed cells for reducing the number of lithographic steps
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- G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
- G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour
- G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour based on liquid crystals, e.g. single liquid crystal display cells
- G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
- G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
- G02F1/1362—Active matrix addressed cells
- G02F1/1368—Active matrix addressed cells in which the switching element is a three-electrode device
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- Thin Film Transistor (AREA)
Abstract
목적 : 콘택홀(contact hole) 식각에 따른 공정윈도우 확보를 위해 다층으로 비정질실리콘층을 형성하며, 반도체소자 제조공정에 따르는 마스크수를 줄이기 위해 게이트전극, 소스전극, 및 드레인전극을 한 번의 마스크공정으로 형성시킬 수 있는 다결정실리콘 박막트랜지스터 제조방법에 대해 개시한다.Purpose: Amorphous silicon layer is formed in multiple layers to secure the process window by contact hole etching, and the gate electrode, source electrode, and drain electrode are masked once to reduce the number of masks according to the semiconductor device manufacturing process. A method of manufacturing a polysilicon thin film transistor that can be formed by the present invention is disclosed.
구성 : 본 발명의 다결정실리콘 박막트랜지스터 제조방법은, 이온 도핑된 비정질실리콘층을 적층 형성한 후 패터닝하여 소정영역에 콘택영역을 정의하는 제1 단계와; 제1 단계의 결과물 상에 비정질실리콘층을 적층 형성하고, 콘택영역을 포함하여 콘택영역 사이에 활성영역을 정의할 수 있도록 패터닝하는 제2 단계와; 제2 단계의 결과물 상에 레이저를 조사하여 상부에 전도층을 형성시킬 수 있도록 다결정실리콘으로 활성화시키는 제3 단계와; 제3 단계의 결과물 상에 절연층을 적층 형성하고 콘택영역에 콘택홀을 형성하는 제4 단계와; 제4 단계의 결과물 상에 금속층을 적층 형성하고 패터닝하여 소스전극, 드레인전극, 및 게이트전극을 형성시키는 제5 단계와; 제5 단계의 결과물 상에 보호층을 증착 형성하고 드레인전극과 연결되는 콘택홀을 형성하여 화소전극 및 부수적인 배선영역을 형성하는 제6 단계;를 포함하여 이루어진 것을 특징으로 한다.Configuration: A method for manufacturing a polysilicon thin film transistor according to the present invention includes a first step of defining a contact region in a predetermined region by laminating and patterning an ion-doped amorphous silicon layer; A second step of laminating an amorphous silicon layer on the resultant of the first step and patterning an active region between the contact regions including the contact region; A third step of activating polycrystalline silicon to irradiate a laser on the resultant of the second step to form a conductive layer thereon; Stacking an insulating layer on the resultant product of the third step and forming a contact hole in the contact area; Stacking and patterning a metal layer on the resultant of the fourth step to form a source electrode, a drain electrode, and a gate electrode; And a sixth step of forming a pixel electrode and an additional wiring region by depositing a protective layer on the resultant product of the fifth step and forming a contact hole connected to the drain electrode.
효과 : 콘택영역을 다층의 비정질실리콘층으로 형성함으로써 콘택홀 식각에 따른 공정윈도우가 확보됨과 동시에 게이트전극, 소스전극 및 드레인전극을 한 번의 마스크공정으로 형성시킴으로써 마스크수 절감, LDD폭 조절의 용이성, 표면기복의 감소 및 콘택홀에서 접촉저항을 낮출 수 있다. 결국, 반도체소자의 수율을 향상시킬 수 있다.Effect: By forming the contact region as a multilayer amorphous silicon layer, the process window according to the contact hole etching is secured, and the gate electrode, the source electrode, and the drain electrode are formed in one mask process to reduce the number of masks and to easily control the LDD width. It can reduce the surface relief and lower the contact resistance in the contact hole. As a result, the yield of the semiconductor device can be improved.
Description
본 발명은 박막트랜지스터 제조방법에 관한 것으로, 특히 콘택홀 식각에 따른 공정윈도우 확보를 위해 다층으로 비정질실리콘층을 형성하며, 반도체소자 제조공정에 따르는 마스크수를 줄이기 위해 게이트전극, 소스전극, 및 드레인전극을 한 번의 마스크공정으로 형성시킬 수 있는 다결정실리콘 박막트랜지스터 제조방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film transistor, and in particular, to form an amorphous silicon layer in multiple layers to secure a process window due to contact hole etching, and to reduce the number of masks according to a semiconductor device manufacturing process, a gate electrode, a source electrode, and a drain. The present invention relates to a polysilicon thin film transistor manufacturing method capable of forming an electrode in one mask process.
박막트랜지스터는 액티브 매트릭스 액정표시장치와 같은 평판 표시소자 등에서 픽셀의 온/오프 스위칭소자로 널리 활용되고 있다. 이 때, 여기에 적용되는 박막트랜지스터는 내전압성과 온 오프 전류비가 높아야 하는 조건을 충족해야 한다.Thin film transistors are widely used as on / off switching elements of pixels in flat panel display devices such as active matrix liquid crystal displays. At this time, the thin film transistor to be applied here must satisfy the condition that the voltage resistance and the on-off current ratio must be high.
박막트랜지스터의 종류는 비정질실리콘 트랜지스터와 다결정실리콘 트랜지스터가 알려져 있으며, 비정질실리콘에 비해 다결정실리콘이 전자이동율 등의 성능과 신뢰도 면에서 더 좋은 평가를 내리고 있지만 고온 분위기에서 막 형성되는 문제가 있어서 일반적으로는 비정질실리콘 박막트랜지스터가 실용화되고 있었다.Thin film transistors are known as amorphous silicon transistors and polysilicon transistors, and polysilicon has a better evaluation in terms of performance and reliability such as electron transfer rate than amorphous silicon. Amorphous silicon thin film transistors have been put into practical use.
그러나, 최근에 엑시머레이저 장비 등을 활용하여 막 형성을 위한 고온 분위기를 간단하고 저렴한 비용으로 조성할 수 있는 기술적 진보가 이루어짐에 따라 다결정실리콘 박막트랜지스터에 대한 관심이 고조되고 있는 실정이다.However, recently, as technological advances are being made by using an excimer laser device and the like to create a high temperature atmosphere for forming a film at a simple and low cost, interest in polysilicon thin film transistors is increasing.
상기 액티브 매트릭스 액정표시장치에서는 반도체의 한쪽으로 게이트, 소스및 드레인전극을 위치시키는 코플래너 구조(평면형 구조)를 선호하는 경향이 있다. 상기 코플래너 구조는 소자의 크기를 최소화할 수 있고, PMOS와 NMOS를 함께 갖추어 상호간의 장단점을 보완하는 특성을 가진다.In the active matrix liquid crystal display device, there is a tendency to prefer a coplanar structure (planar structure) in which a gate, a source, and a drain electrode are positioned to one side of a semiconductor. The coplanar structure can minimize the size of the device and have a PMOS and an NMOS to complement each other.
그러면, 종래의 박막트랜지스터 제조방법에 대해 도면을 참조하여 설명하기로 한다.Then, a conventional thin film transistor manufacturing method will be described with reference to the drawings.
도 2는 종래의 코플래너 다결정실리콘 박막트랜지스터의 구조를 나타낸 도면이다. 도 2를 참조하면, 먼저 기판(1) 상에 SiO2층인 버퍼층(2)을 선택적으로 적층하고, 상기 버퍼층(2) 상에 비정질실리콘층을 도포하고 패터닝하여 활성층(3)을 정의한다. 이 때, 상기 활성층(3)은 레이저 조사에 의해 다결정실리콘으로 변형된다. 여기서, 상기 버퍼층(2)은, 후속되는 공정에서 PECVD(Plasma Enhanced Chemical Vapor Deposition)법으로 비정질실리콘층을 증착하고 이를 재결정화하여 다결정실리콘의 활성층(3)을 형성하는 경우, 기판에 함유된 불순물에 의해 결정화된 실리콘이 오염되는 현상을 방지하는 역할을 한다.2 is a view showing the structure of a conventional coplanar polysilicon thin film transistor. Referring to FIG. 2, first, a buffer layer 2 , which is a SiO 2 layer, is selectively stacked on a substrate 1, and an amorphous silicon layer is coated and patterned on the buffer layer 2 to define an active layer 3. At this time, the active layer 3 is deformed into polycrystalline silicon by laser irradiation. Here, the buffer layer 2 is an impurity contained in the substrate when the amorphous silicon layer is deposited by a plasma enhanced chemical vapor deposition (PECVD) method in a subsequent process and recrystallized to form the active layer 3 of polycrystalline silicon. It is to prevent the phenomenon that the silicon crystallized by contamination.
상기 활성층(3) 상에 절연막(4)을 도포하고, 이 절연막(4) 상부에 게이트 메탈층을 증착시킨다. 상기 증착된 게이트 메탈층을 패터닝하여 게이트전극(5)을 형성한다.An insulating film 4 is coated on the active layer 3, and a gate metal layer is deposited on the insulating film 4. The deposited gate metal layer is patterned to form a gate electrode 5.
이후, 상기 게이트전극(5) 상에 새로운 포토 레지스트층을 도포하고 이를 패터닝하되 상기 게이트전극(5)보다 약간 큰 폭으로 패터닝한다. 그리고, 여기에 이온 주입하여 상기 활성층의 양단부에 n－영역을 형성하여 n 웰을 형성한다. 이후,상기 포토 레지스트층을 제거한 후에 가볍게 이온 도핑시키면 상기 게이트전극의 좌우로 LDD영역(6)이 형성된다.Thereafter, a new photoresist layer is coated on the gate electrode 5 and patterned, but patterned to a slightly larger width than the gate electrode 5. Then, by ion implantation, n-regions are formed at both ends of the active layer to form n wells. Thereafter, when the photoresist layer is removed and lightly ion-doped, the LDD region 6 is formed to the left and right of the gate electrode.
또한, P－영역을 형성하여 P도핑을 수행함으로써 P영역 활성화층을 형성하는 공정이 추가로 진행된다.Further, the process of forming the P region activation layer is further proceeded by forming the P-region to perform P doping.
이어서 게이트전극(5)의 상면에 층간절연막(7)을 적층하고, 상기 층간절연막(7)을 패터닝하여 콘택홀을 형성한 다음, 여기에 금속막을 증착하여 소스전극(8) 및 드레인전극(9)을 형성한다.Subsequently, an interlayer insulating film 7 is stacked on the upper surface of the gate electrode 5, and the interlayer insulating film 7 is patterned to form a contact hole, and then a metal film is deposited thereon to deposit the source electrode 8 and the drain electrode 9. ).
마지막으로 소스전극(8)과 드레인전극(9)의 상면에 패시베이션층(Passivation layer, 10)을 형성하고 필요 개소에 비아홀을 정의한 후 ITO 등의 화소전극(11)을 형성한다.Finally, a passivation layer 10 is formed on the top surfaces of the source electrode 8 and the drain electrode 9, and via holes are defined in the required portions, and then pixel electrodes 11 such as ITO are formed.
상기와 같이, 종래의 박막트랜지스터 제조 공정에서 포토 리소그라피 공정은 적어도 9회 실시되기 때문에 공정 수의 증가에 따른 생산성의 저하 문제와 제품 불량률의 증가 문제를 피할 수 없었다. 주지된 바와 같이 하나의 포토 리소그라피 공정은 포토 레지스트 도포, 마스크 노광, 현상, 및 에칭 등의 여러 단계로 진행되기 때문에 공정 수의 증가는 심각한 생산성의 저하 및 품질 불량률의 증가를 초래한다.As described above, since the photolithography process is performed at least nine times in the conventional thin film transistor manufacturing process, it is inevitable to reduce the productivity and increase the product defect rate according to the increase in the number of processes. As is well known, since one photolithography process proceeds in several steps, such as photoresist application, mask exposure, development, and etching, an increase in the number of processes leads to a serious decrease in productivity and an increase in quality defect rate.
특히 도핑을 위한 포토 마스크 공정은 기판 패턴, 게이트 패턴, n+ 이온주입, n- 이온주입, p+ 이온주입 등의 5회로 실시되어야 하기 때문에 공정 수를 줄이는데 큰 장애로 작용하고 있다.In particular, since the photo mask process for doping has to be performed five times, such as a substrate pattern, a gate pattern, n + ion implantation, n− ion implantation, and p + ion implantation, it is a major obstacle in reducing the number of processes.
또한, 상기 활성층(3)이 1000Å 내외의 두께를 갖기 때문에 콘택홀 식각시에식각을 위한 공정파라미터를 엄격히 관리하지 않을 경우, 리세스 심화가 발생할 수 있어 공정윈도우가 좋지 않다는 문제점이 있었다.In addition, since the active layer 3 has a thickness of about 1000 mW, if the process parameters for etching are not strictly managed during the contact hole etching, recesses may occur and the process window is not good.
따라서, 본 발명의 목적은 콘택홀 식각에 따른 공정윈도우 확보를 위해 다층으로 비정질실리콘층을 형성하며, 반도체소자 제조공정에 따르는 마스크수를 줄이기 위해 게이트전극, 소스전극, 및 드레인전극을 한 번의 마스크공정으로 형성시킬 수 있는 다결정실리콘 박막트랜지스터 제조방법을 제공하는데 있다.Accordingly, an object of the present invention is to form an amorphous silicon layer in multiple layers to secure a process window according to contact hole etching, and to mask the gate electrode, the source electrode, and the drain electrode in one mask to reduce the number of masks according to the semiconductor device manufacturing process. The present invention provides a method for manufacturing a polysilicon thin film transistor that can be formed by a process.
상기한 목적을 달성하기 위해 본 발명의 다결정실리콘 박막트랜지스터 제조방법은, 기판 상에 선택적으로 버퍼층을 증착 형성하고, 상기 버퍼층 상에 이온 도핑된 비정질실리콘층을 적층 형성한 후 패터닝하여 소정영역에 콘택영역을 정의하는 제1 단계와; 상기 제1 단계의 결과물 상에 비정질실리콘층을 적층 형성하고, 상기 콘택영역을 포함하여 상기 콘택영역 사이에 활성영역을 정의할 수 있도록 패터닝하는 제2 단계와; 상기 제2 단계의 결과물 상에 레이저를 조사하여 상부에 전도층을 형성시킬 수 있도록 다결정실리콘으로 활성화시키는 제3 단계와; 상기 제3 단계의 결과물 상에 절연층을 적층 형성하고 상기 콘택영역에 콘택홀을 형성하는 제4 단계와; 상기 제4 단계의 결과물 상에 금속층을 적층 형성하고 패터닝하여 소스전극, 드레인전극, 및 게이트전극을 형성시키는 제5 단계와; 상기 제5 단계의 결과물 상에 보호층을 증착 형성하고 상기 드레인전극과 연결되는 콘택홀을 형성하여 화소전극 및 부수적인 배선영역을 형성하는 제6 단계;를 포함하여 이루어진 것을 특징으로 한다.In order to achieve the above object, the polysilicon thin film transistor manufacturing method of the present invention comprises depositing a buffer layer selectively on a substrate, and laminating and patterning an ion-doped amorphous silicon layer on the buffer layer to contact a predetermined region. Defining a region; A second step of laminating an amorphous silicon layer on the resultant of the first step and patterning an active region between the contact regions including the contact region; A third step of activating polysilicon so that a laser is irradiated on the resultant of the second step to form a conductive layer thereon; Stacking an insulating layer on the resultant of the third step and forming a contact hole in the contact area; Stacking and patterning a metal layer on the resultant of the fourth step to form a source electrode, a drain electrode, and a gate electrode; And a sixth step of forming a protective layer on the resultant product of the fifth step and forming a contact hole connected to the drain electrode to form a pixel electrode and an additional wiring region.
이 때, 상기 제1 단계에서 비정질실리콘층은 n＋ 및 p＋ 비정질실리콘에서 선택된 어느 하나를 사용한다. 이 경우에, 상기 제5 단계의 결과물 상에 게이트전극을 마스크로 하여 이온을 도핑시키되, 상기 제1 단계에서 n＋ 비정질실리콘을 사용한 경우에는 n－ 이온을 도핑시키고, p＋ 비정질실리콘을 사용한 경우에는 p－ 이온을 도핑시켜 상기 활성영역의 양단 소정부위에 LDD 영역을 형성하는 단계를 더 포함하여 이루어진 것이 바람직하다.At this time, in the first step, the amorphous silicon layer uses any one selected from n + and p + amorphous silicon. In this case, the ions are doped with the gate electrode as a mask on the resultant of the fifth step, but when n + amorphous silicon is used in the first step, n − ions are doped, and p + amorphous silicon is used. Doping ions to form LDD regions at predetermined portions of both ends of the active region.
또한, 상기 제5 단계의 결과물 상에 게이트전극을 마스크로 하여 이온을 도핑시키되, 상기 제1 단계에서 n＋ 비정질실리콘을 사용한 경우에는 n＋ 이온을 도핑시키고, p＋ 비정질실리콘을 사용한 경우에는 p＋ 이온을 도핑시켜 상기 활성영역의 양단 소정부위에 LDD 영역을 형성시키지 않는 단계를 더 포함할 수도 있다.In addition, the dopant is ion-doped using the gate electrode as a mask on the resultant of the fifth step, but n + ions are doped when n + amorphous silicon is used in the first step, and p + ions are used when p + amorphous silicon is used. The method may further include the step of not forming an LDD region at predetermined portions of both ends of the active region.
그리고, 상기 제5 단계에서 게이트전극의 폭은 활성영역의 폭보다 작게 패터닝되는 것이 더욱 바람직하다.In the fifth step, the width of the gate electrode is more preferably patterned to be smaller than the width of the active region.
도 1a 내지 도 1f는 본 발명의 일 실시예로서, 다결정실리콘 박막트랜지스터 제조방법을 공정순서에 따라 도시한 단면도,1A to 1F are cross-sectional views illustrating a method of manufacturing a polysilicon thin film transistor according to an exemplary embodiment of the present invention.
도 2는 종래의 코플래너 다결정실리콘 박막트랜지스터의 구조를 나타낸 도면이다.2 is a view showing the structure of a conventional coplanar polysilicon thin film transistor.
**도면의 주요부분에 대한 부호의 설명**** Description of the symbols for the main parts of the drawings **
20 : 기판 22 : 버퍼층20: substrate 22: buffer layer
24 : n＋ 비정질실리콘층 26 : 채널영역24: n + amorphous silicon layer 26: channel region
28 : 다결정실리콘층 30 : 절연층28 polycrystalline silicon layer 30 insulating layer
32 : 콘택홀 34 : 소스전극32: contact hole 34: source electrode
36 : 드레인전극 38 : 게이트전극36 drain electrode 38 gate electrode
40 : LDD영역40: LDD area
이하, 첨부된 도면을 참조하여 본 발명의 바람직한 실시예에 대해 설명한다.Hereinafter, with reference to the accompanying drawings will be described a preferred embodiment of the present invention.
도 1a 내지 도 1f는 본 발명의 일 실시예로서, 다결정실리콘 박막트랜지스터의 제조방법을 공정순서에 따라 도시한 단면도이다.1A to 1F are cross-sectional views illustrating a method of manufacturing a polysilicon thin film transistor according to an exemplary embodiment of the present invention, according to a process sequence.
도 1a를 참조하면, 기판(20) 상에 선택적으로 버퍼층(22)을 증착 형성하고, 상기 버퍼층(22) 상에 n＋ 비정질실리콘층(24)을 적층 형성한 후 패터닝하여 소정영역에 콘택영역을 정의한다. 이 때, n＋ 비정질실리콘층(24)은 1000Å 정도의 두께로 증착하는 것이 바람직하다.Referring to FIG. 1A, a buffer layer 22 may be selectively deposited on a substrate 20, and an n + amorphous silicon layer 24 may be stacked on the buffer layer 22 and then patterned to form a contact region in a predetermined region. define. At this time, it is preferable to deposit the n + amorphous silicon layer 24 to a thickness of about 1000 mW.
도 1b를 참조하면, 상기 콘택영역을 포함한 전면 상에 비정질실리콘층을 적층 형성하고, 상기 콘택영역 사이에 채널영역(26)을 정의할 수 있도록 상기 콘택영역을 포함하는 소정영역을 패터닝한다. 이 때, 비정질실리콘층은 대략 500Å 정도 증착시키는 것이 바람직하다.Referring to FIG. 1B, an amorphous silicon layer is stacked on the entire surface including the contact region, and a predetermined region including the contact region is patterned to define a channel region 26 between the contact regions. At this time, the amorphous silicon layer is preferably deposited at approximately 500 kPa.
이 때, 도 1c에 도시한 바와 같이, 상기 n＋ 비정질실리콘층과 비정질실리콘층 상으로 레이저를 조사하여 다결정실리콘층(28)으로 결정화시킨다. 이 과정에서 콘택영역은 활성화되고 도펀트(dopant)가 다결정실리콘층(28)의 상부로 이동하여 전도층이 형성된다.At this time, as shown in Fig. 1C, a laser is irradiated onto the n + amorphous silicon layer and the amorphous silicon layer to crystallize the polysilicon layer 28. In this process, the contact region is activated and the dopant is moved to the top of the polysilicon layer 28 to form a conductive layer.
이후, 상기 다결정실리콘층(28) 상에 절연층(30)을 적층 형성하고 상기 콘택영역 상에 콘택홀(32)을 도 1d와 같이 형성한다. 이 때, n＋ 비정질실리콘층(24)과 비정질실리콘층(26)이 대략 1500Å 정도의 두께를 가짐으로써 상기 콘택홀(32) 형성에 따른 리세스(recess)가 심화되더라도 반도체소자의 신뢰성을 확보할 수 있음을 알 수 있다.Thereafter, an insulating layer 30 is laminated on the polysilicon layer 28 and a contact hole 32 is formed on the contact region as shown in FIG. 1D. At this time, since the n + amorphous silicon layer 24 and the amorphous silicon layer 26 have a thickness of about 1500 GPa, the reliability of the semiconductor device may be secured even if the recesses due to the formation of the contact hole 32 are intensified. It can be seen that.
한편, 도 1e에 도시된 바와 같이, 상기 결과물 상에 금속층을 적층 형성하고 패터닝하여 소스전극(34), 드레인전극(36), 및 게이트전극(38)을 동시에 형성시킨다. 이 때, 상기 게이트전극(38)의 폭은 활성영역의 폭보다 작게 패터닝되는 것은 바람직하다. 이는 이후에 선택적으로 진행되는 LDD영역(40)을 형성시키기 위해서이다.Meanwhile, as shown in FIG. 1E, a metal layer is stacked and patterned on the resultant to simultaneously form the source electrode 34, the drain electrode 36, and the gate electrode 38. At this time, the width of the gate electrode 38 is preferably patterned smaller than the width of the active region. This is to form the LDD region 40 which is selectively performed later.
이후, 도 1f에 도시된 바와 같이, 상기 결과물에서 게이트전극(38)을 마스크로 하여 n－ 이온을 도핑시켜 LDD영역(40)을 정의한다. 이 때, 상기 LDD영역(40)을 형성시키지 않는 박막트랜지스터를 제조하기 위해서는 n＋ 이온을 도핑시킨다.1F, the LDD region 40 is defined by doping n-ion with the gate electrode 38 as a mask in the resultant product. At this time, in order to manufacture a thin film transistor which does not form the LDD region 40, n + ions are doped.
한편, 상기 소스전극(34), 드레인전극(36), 및 게이트전극(38) 상으로 보호층(미도시)을 증착 형성하고 상기 드레인전극(36)과 연결되는 콘택홀(미도시)을 형성하여 화소전극(미도시) 및 부수적인 배선영역을 형성한다.Meanwhile, a protective layer (not shown) is deposited on the source electrode 34, the drain electrode 36, and the gate electrode 38, and a contact hole (not shown) connected to the drain electrode 36 is formed. As a result, a pixel electrode (not shown) and an additional wiring area are formed.
본 실시예에서는 n＋ 이온 도핑된 비정질실리콘을 이용한 경우에 대해서만 서술하였으나, p＋ 비정질실리콘을 사용할 수도 있다. 이 경우에, LDD영역 형성을 위해 상기 게이트전극을 마스크로 하여 이온을 도핑시킬 때 p－ 이온을 도핑시키면 된다. 또한, 상기 활성영역의 양단 소정부위에 LDD 영역을 형성시키지 않을 경우에는 p＋ 이온을 도핑시키면 된다.In this embodiment, only the case where n + ion-doped amorphous silicon is used is described, but p + amorphous silicon may also be used. In this case, p-ions may be doped when doping ions with the gate electrode as a mask to form the LDD region. In addition, when the LDD region is not formed at predetermined portions of both ends of the active region, p + ions may be doped.
상술한 바와 같이, 본 발명에 따른 다결정실리콘 박막트랜지스터 제조방법은, 콘택영역을 다층의 비정질실리콘층으로 형성함으로서 공정윈도우가 확보됨과 동시에 게이트전극, 소스전극 및 드레인전극을 한 번의 마스크공정으로 형성시킴으로써 마스크수 절감, LDD폭 조절의 용이성, 표면기복의 감소 및 콘택홀에서 접촉저항을 낮출 수 있다. 결국, 반도체소자의 수율을 향상시킬 수 있다.As described above, in the method of manufacturing a polysilicon thin film transistor according to the present invention, the contact window is formed of a multi-layered amorphous silicon layer, thereby ensuring a process window and simultaneously forming the gate electrode, the source electrode, and the drain electrode in one mask process. It can reduce the number of masks, ease the LDD width control, reduce surface relief and lower the contact resistance in the contact hole. As a result, the yield of the semiconductor device can be improved.
본 발명은 상술한 실시예에 한정되지 않으며, 본 발명의 기술적 사상 내에서 당분야에서 통상의 지식을 가진 자에 의하여 많은 변형이 가능함은 명백하다.The present invention is not limited to the above-described embodiment, and it is apparent that many modifications are possible by those skilled in the art within the technical spirit of the present invention.
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| JPH06260498A (en) * | 1991-03-25 | 1994-09-16 | Fuji Xerox Co Ltd | Thin-film transistor and manufacture thereof |
| JPH06267989A (en) * | 1993-03-12 | 1994-09-22 | Semiconductor Energy Lab Co Ltd | Method of manufacturing thin film transistor |
| JPH06275650A (en) * | 1993-03-19 | 1994-09-30 | Sony Corp | Manufacture of field effect transistor |
| JPH08148425A (en) * | 1994-11-22 | 1996-06-07 | Sharp Corp | Semiconductor device and manufacture thereof |
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| JPH06260498A (en) * | 1991-03-25 | 1994-09-16 | Fuji Xerox Co Ltd | Thin-film transistor and manufacture thereof |
| JPH06267989A (en) * | 1993-03-12 | 1994-09-22 | Semiconductor Energy Lab Co Ltd | Method of manufacturing thin film transistor |
| JPH06275650A (en) * | 1993-03-19 | 1994-09-30 | Sony Corp | Manufacture of field effect transistor |
| JPH08148425A (en) * | 1994-11-22 | 1996-06-07 | Sharp Corp | Semiconductor device and manufacture thereof |
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