JP3141636B2 - Thin film transistor and method of manufacturing the same - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor used as a switching element in, for example, an active matrix liquid crystal display and the like, and more particularly to a thin film transistor for reducing off current.

[0002]

2. Description of the Related Art A thin film transistor is, for example, a switching element for controlling the operation of a liquid crystal element constituting an active matrix type liquid crystal display. It is used as one of the constituent elements. Such thin film transistors include:
Since a current driving capability is required, a so-called polysilicon thin film transistor using poly-Si (polysilicon) having high carrier mobility for a channel layer is often used.

However, the polysilicon thin film transistor does not have a very low off-state current. In particular, in the case of a liquid crystal display or the like, the off-state current is maintained because the driving voltage of the liquid crystal is maintained when the thin film transistor is turned off. If it is large, it is difficult to secure a driving voltage required for driving the liquid crystal, which causes deterioration in image quality. For this reason, as a technique for reducing the off current of a polysilicon thin film transistor, a channel layer and a drain source of the thin film transistor are used.
LD that forms a region with a low impurity concentration between itself and the source region
A structure called a D (lightly doped drain) structure has been proposed (for example, see Japanese Patent Application Laid-Open No. 3-64971).

Incidentally, in a thin film transistor having an LDD structure, a photolithography method is generally used to form a low-concentration impurity region. When this photolithography method is used, misalignment is apt to occur during so-called mask alignment.
Therefore, there is a problem that the off-current varies every time the device is manufactured, and the yield is reduced. As a technique for solving such a problem, for example, Japanese Unexamined Patent Publication No.
As described in JP-A-204570, a thin film transistor having an LDD structure is manufactured without performing mask alignment by performing ion implantation using a resist film formed by overetching on the upper surface of a gate electrode as a mask. Something like that has been proposed.

[0005]

However, in this technique, the impurity is implanted by an ion implantation method used in an LSI manufacturing process. However, this method has a slow throughput, and therefore has a large glass area compared to the LSI. It is actually difficult to apply the method to manufacture of a thin film transistor in an active matrix liquid crystal display manufactured on a substrate. For this reason, as a technique for solving such a problem, shower-
A technique using the ping method has been proposed (see “S. Inoue, P.
roc. of IEDM 91, pp. 555-558 ”), but in this technique, since the mass separation of impurities is not performed, the implantation efficiency is low and the substrate temperature rises during the impurity implantation. However, the prior art which presupposes that the substrate temperature is relatively low (the technique disclosed in Japanese Patent Application Laid-Open No. 58-204570) cannot be used. Therefore, there has been a problem that it is difficult to manufacture a thin film transistor having an LDD structure with a small variation in off-current without causing any new inconvenience in any of the conventional techniques.

The present invention has been made in view of the above circumstances, and provides a thin film transistor having no variation in off current and a method of manufacturing the same.

[0007]

According to a first aspect of the present invention, there is provided a thin film transistor, which is located on the polycrystalline silicon film via a gate insulating film and a polycrystalline silicon film formed on an insulating substrate. While a gate electrode is provided, a channel region is formed on the polycrystalline silicon film at a position immediately below the gate electrode so as to sandwich the channel region.
In a thin film transistor in which a low-concentration impurity region having a lower impurity concentration than the source / drain region is formed and a source / drain region is formed so as to sandwich the low-concentration impurity region, An interlayer insulating film having a portion protruding from the periphery of the gate electrode in a direction substantially perpendicular to the lamination direction of the gate electrode is formed. According to a second aspect of the present invention, there is provided a method of manufacturing a thin film transistor, comprising: a polycrystalline silicon film formed on an insulating substrate; and a gate electrode located on the polycrystalline silicon film via a gate insulating film. On the other hand, in the polycrystalline silicon film, a channel region is provided at a portion located immediately below the gate electrode, and a low-concentration impurity region having a lower impurity concentration than the source / drain region is provided so as to sandwich the channel region. A method of manufacturing a thin film transistor, wherein a source / drain region is formed so as to sandwich the low-concentration impurity region, wherein the gate electrode is formed on the gate insulating film, Forming a source / drain region in a self-aligned manner by injecting impurities into the polycrystalline silicon using the gate electrode as a mask; and forming the source / drain region after forming the source / drain region. A step of coating the gate insulating film plane insulating member facing the stacking direction of, - and the gate
Removing the side wall of the gate electrode by a predetermined width in a direction substantially perpendicular to the lamination direction of the gate electrode after coating with the insulating member; and removing the source using the gate electrode as a mask.
Forming a low-concentration impurity region by implanting an impurity into the polycrystalline silicon using the gate electrode as a mask at a concentration lower than the concentration of the implanted impurity at the time of forming the drain / drain region. It becomes.

[0008]

In the thin film transistor according to the first aspect of the present invention, the portion where the interlayer insulating film formed on the gate electrode protrudes from the peripheral portion of the gate electrode is formed as a source / drain region. Later, the low-concentration impurity region is formed by shaving the side wall of the gate electrode, and the low-concentration impurity region is formed by implanting impurities after shaving the side wall of the gate electrode. Since the impurity region has a structure formed without performing mask alignment, a thin film transistor having less variation in off-state current is obtained. In the method of manufacturing a thin film transistor according to the second aspect of the present invention, after forming the source / drain region in a self-aligned manner using the gate electrode as a mask, the gate electrode is moved in the stacking direction of the gate electrode. Then, a portion corresponding to the width of the gate electrode is newly implanted into the polycrystalline silicon film, and the impurity is implanted again. Since the region becomes an impurity region, the length of the low-concentration impurity region is set without requiring mask alignment.

[0009]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS A thin-film transistor according to the present invention will be described below with reference to FIGS. Here, FIG. 1 is a longitudinal sectional view showing one embodiment of the thin film transistor according to the present invention, and FIGS. 2 to 4 are longitudinal sectional views in main steps for explaining a manufacturing process of the thin film transistor according to the present invention.

In this thin film transistor, an impurity diffusion preventing layer 2 is laminated on a glass substrate 1, and a low concentration impurity region is formed on the impurity diffusion preventing layer 2 so as to sandwich the channel layer 3 with the channel layer 3 at the center. 4a and 4b, and furthermore, the source is sandwiched between these low-concentration impurity regions 4a and 4b.
S / drain regions 5a and 5b are formed respectively. Then, a gate insulating film 6 is laminated so as to cover them, and a gate electrode 7 is formed on the gate insulating film 6. On the gate insulating film 6 around the gate electrode 7, a first interlayer insulating film 8 is laminated, and on the gate electrode 7, a peripheral portion of the gate electrode 7 is formed. The first interlayer insulating film 8 is stacked in a state in which the first interlayer insulating film 8 is approaching. further,
On the first interlayer insulating film 8, a second interlayer insulating film 9 is laminated. Then, contact holes 10a and 10b are formed so as to penetrate the second interlayer insulating film 9, the first interlayer insulating film 8 and the gate insulating film 6, and the source holes are formed in the contact holes 10a and 10b. Wiring electrodes 11a and 11b joined to the drain regions 5a and 5b are provided.

Next, a manufacturing process of the thin film transistor having the above configuration will be described with reference to FIGS. First, an impurity diffusion preventing layer 2 is formed by depositing a silicon nitride film or a silicon oxide film on a glass substrate 1 for about 500 angstroms (see FIG. 2A). Subsequently, after depositing a-Si of about 1000 Å by low pressure CVD, a KrF excimer laser is
By irradiating the entire surface with an intensity of 50 mJ / cm ² ,
A poly-Si film 3a is obtained. After this, poly-Si
The film 3a is patterned into an island shape by photolithography.
Then, a silicon oxide film is deposited on the order of 1000 angstroms to obtain a gate insulating film 6 (FIG. 2).
(A)).

Next, 50 tantalum layers are formed by sputtering.
After film formation of about 00 Å, CDE (Chemical D
The gate electrode 7 is obtained by forming it in an island shape using a ry etching (see FIG. 2B). Subsequently, the gate electrode 7 is used as a mask in a self-aligned manner by a shadowing method.
N-type source / drain regions 5a and 5b are formed by implanting 5 × 10 ¹⁵ ions / cm ² of phosphorus impurity at an energy of 0 KeV (see FIG. 2C). Next, a silicon oxide film is formed by ECR-PCVD to a thickness of 100%.
A first interlayer insulating film 8 is obtained by depositing about 0 Å (see FIG. 3A). In this case, the deposition conditions are Si
H ₄ : O ₂ = 5: 15 sccm, microwave power is 2
00W, gas pressure 1mTorr, film formation temperature 25 ° C
Therefore, no substrate bias is applied. When deposition is performed under such conditions, the deposition directivity is enhanced. That is, specifically, the silicon oxide film is deposited only on the surface orthogonal to the deposition direction, and the side surface portion of the gate electrode 7 (FIG.
In the case of (a), the gate electrode 7 which is orthogonal to the horizontal direction of the paper surface
Surface) is not covered with the silicon oxide film and the gate electrode 7
Is left exposed.

After the deposition of the silicon oxide film is completed, the side surface of the gate electrode 7 is additionally etched to be set back by about 1 μm in the horizontal direction (the horizontal direction in FIG. 3) (see FIG. 3B). As a result of this processing, the first interlayer insulating film 8 made of a silicon oxide film on the gate electrode 7 protrudes from the peripheral portion of the gate electrode 7 (see FIG. 3B). Next, a concentration lower than the concentration of phosphorus implanted into the source / drain regions 5a and 5b, specifically, 5 × 10 ¹² ions, at an energy of 100 KeV by the showering method.
By implanting phosphorus at a concentration of s / cm ² and performing a heat treatment at 500 ° C. after the implantation, the low-concentration impurity regions 4 a and 4 b
Is formed (see FIG. 4A). As a result, the width of the low-concentration impurity regions 4a and 4b to be formed (the width in the left-right direction in FIG. 4) is determined by the additional etching performed on the side surface of the gate electrode 7 so that the gate electrode 7 is in the lateral direction ( In FIG. 4, the length corresponds to the retreated length in the horizontal direction of the drawing. Thereafter, a silicon oxide film is formed to a thickness of about 9000 angstroms using SOG (Spin On Glass) and heat-treated at 450 ° C. for about 1 hour to obtain a second interlayer insulating film 9 (FIG. 4B). reference).

Finally, the contact holes 10a and 10b are formed, and the wiring electrodes 11a and 11b are formed by depositing and patterning the contact holes 10a and 10b by using aluminum for wiring by sputtering, thereby completing the thin film transistor. (See FIG. 1). In this embodiment, as a member for forming the first interlayer insulating film 8,
Although a silicon oxide film is used, the invention is not limited to this. For example, a silicon nitride film or a silicon oxynitride film may be used.

In this embodiment, after the source / drain regions 5a and 5b are formed by implanting impurities in a self-aligned manner using the gate electrode 7 as a mask, the gate electrode 7 is additionally etched. By retreating in the direction of forming the low-concentration impurity regions 4a and 4b, and then implanting impurities again at a concentration lower than the concentration at the time of the previous impurity implantation,
Since the portion corresponding to the length of the recessed gate electrode 7 becomes the low-concentration impurity regions 4a and 4b,
The lengths of a and 4b are determined by the amount of retreat of the gate electrode 7 due to additional etching of the gate electrode 7.
Therefore, unlike the conventional case, the length of the low-concentration impurity region is set without performing the mask alignment, so that the length of the low-concentration impurity region due to the misalignment of the mask may vary at every manufacturing. As a result, a thin film transistor with less variation in off-current due to variation in the length of the low-concentration impurity region can be obtained. Further, since the low-concentration impurity regions are formed without using a resist mask, the present invention can be applied to an active matrix liquid crystal display manufactured using a large-sized glass substrate.

[0016]

As described above, according to the present invention,
The mask alignment is required by forming the low-concentration impurity region corresponding to the width of the shaved gate electrode by implanting the impurity again after shaving the gate electrode. Since the width of the low-concentration impurity region can be set without any variation, the size of the low-concentration impurity region becomes uniform without variation, and as a result, so-called variation in off-current due to the variation in size of the low-concentration impurity region is eliminated. This has the effect of providing a thin film transistor having a uniform value.

[Brief description of the drawings]

FIG. 1 is a longitudinal sectional view showing one embodiment of a thin film transistor according to the present invention.

FIG. 2 is a longitudinal sectional view of main steps for describing a manufacturing process of a thin film transistor according to the present invention.

FIG. 3 is a longitudinal sectional view of main steps for describing a manufacturing process of a thin film transistor according to the present invention.

FIG. 4 is a longitudinal sectional view showing main steps for describing a manufacturing process of the thin film transistor according to the present invention.

[Explanation of symbols]

2 ... impurity diffusion preventing layer 3 ... channel layer 4a,
4b: low concentration impurity region; 5a, 5b: source / drain region; 8: first interlayer insulating film; 9: second interlayer insulating film

Claims (2)

(57) [Claims] 1. A polycrystalline silicon film formed on an insulating substrate and a gate electrode located on the polycrystalline silicon film via a gate insulating film are provided. A channel region at a position immediately below the gate electrode, a low concentration impurity region having a lower impurity concentration than the source / drain region so as to sandwich the channel region, and a low concentration impurity region so as to sandwich the low concentration impurity region. In a thin film transistor in which a source / drain region is formed, a portion protruding from the periphery of the gate electrode in a direction substantially perpendicular to the lamination direction of the gate electrode on the gate electrode. A thin film transistor comprising an interlayer insulating film having 2. A polycrystalline silicon film formed on an insulating substrate and a gate electrode located on the polycrystalline silicon film via a gate insulating film are provided. A channel region at a position immediately below the gate electrode, a low concentration impurity region having a lower impurity concentration than the source / drain region so as to sandwich the channel region, and a low concentration impurity region so as to sandwich the low concentration impurity region. A method of manufacturing a thin film transistor in which a source / drain region is formed, wherein the gate electrode is formed on the gate insulating film, and then the polycrystalline silicon is formed using the gate electrode as a mask. Forming a source / drain region in a self-aligned manner by implanting impurities into the substrate; and, after forming the source / drain region, a plane facing the stacking direction of the gate electrode and the gate insulating film. Covering with an insulating member,
Removing the side wall of the gate electrode by a predetermined width in a direction substantially perpendicular to the lamination direction of the gate electrode after coating with the insulating member; and removing the source using the gate electrode as a mask.
Forming a low-concentration impurity region by implanting an impurity into the polycrystalline silicon using the gate electrode as a mask at a concentration lower than the concentration of the implanted impurity at the time of forming the drain / drain region. A method for manufacturing a thin film transistor.