JPH1197696A - Thin-film semiconductor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin-film semiconductor device which avoids poor activation of an Si layer after implanting ions, without deteriorating characteristics or reducing the throughput. SOLUTION: Si semiconductor layers 14 (14a, 14b, 14c) are formed in trenches 12 formed in the surface of an insulation substrate 10. Each trench 12 has a first part 12a having a channel region 13a and second part 12b having a source and drain regions 14a, 14b, the latter part being deeper than the former. The top surfaces of all the semiconductor layers 14 are located being flush with the surface of the insulation substrate.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a thin-film semiconductor device used for a liquid crystal display device or the like.

[0002]

2. Description of the Related Art Generally, a thin film semiconductor device used for a liquid crystal display device or the like is formed on a transparent insulating substrate such as a glass substrate, and the semiconductor layer is made of amorphous silicon or polysilicon obtained by crystallizing the same. Is used. In particular, when polysilicon is used, it has a feature that a driving circuit can be formed at the same time because of its high mobility.

However, when a drive circuit is created,
It is necessary to create a complementary MOS in consideration of power consumption. In this case, an n-type MOS and a p-type MOS must be separately formed on the same substrate. An ion implantation method is used.

When ion implantation is performed, the crystal becomes amorphous in a region where the ion is implanted,
The required characteristics cannot be obtained as it is. Therefore, ions are activated by an annealing step called an activation step, and the resistance of the source / drain regions is reduced.

Generally, in a semiconductor device process,
Activation is performed at a high temperature of 800 ° C. or more. However, in the case of a liquid crystal display device, since a glass plate is used as a substrate, it can be heated only up to a temperature of about 600 ° C.
It is necessary to activate a silicon layer at a lower temperature than a semiconductor device. When the activation is performed at a low temperature, a region serving as a nucleus of recrystallization is required in order to cause activation within a realistic time as a process. For this reason, it is important to control the implantation profile of ion implantation so that nuclei remain at the bottom of the source / drain regions into which ions are implanted.

[0006]

However, in this case, it is important to control the thickness of the semiconductor layer in the source / drain region and the thickness of the gate oxide film formed on the semiconductor layer. The resistance value is greatly affected by the variation in the film thickness.

Further, when the thickness of the semiconductor layer is reduced beyond a certain limit, activation failure occurs, and it becomes difficult to obtain desired TFT characteristics. In order to increase the margin for such activation failure, it is possible to cope with the problem by increasing the thickness of the silicon layer serving as the source region and the drain region. Problems such as an increase in off-leakage and an increase in disconnection probability due to an increase in the level difference of the silicon layer occur.

When the channel region is made of polysilicon, problems such as a decrease in throughput due to an increase in power required for crystallization by laser irradiation and an increase in unevenness of the polysilicon surface occur. In order to avoid such a problem, it is conceivable to reduce the thickness of the channel region and increase the thickness of the source / drain region in the silicon layer. The unevenness of the silicon layer becomes large, and the probability of disconnection increases.

The present invention has been made in view of the above points, and an object of the present invention is to provide a thin film semiconductor device capable of preventing a failure in activation of a silicon layer after ion implantation without deteriorating characteristics and decreasing throughput. To provide.

[0010]

In order to achieve the above object, a thin film semiconductor device according to the present invention is provided on an insulating substrate and has a channel region, a source region and a source region located on both sides of the channel region. A semiconductor layer having a drain region, a gate insulating film formed on the semiconductor layer, and a gate electrode formed on the gate insulating film so as to face the channel region; , The upper surface of each of the drain regions is located on the same plane, and the source region and the drain region have a larger thickness than the channel region.

According to the thin film semiconductor device of the present invention, at least the source region and the drain region of the semiconductor layer are partially provided in the grooves formed on the surface of the insulating substrate, respectively. The region is formed to be thicker than the channel region, and the upper surfaces of the channel region, the source region, and the drain region are located on the same plane.

Further, according to the thin-film semiconductor device of the present invention, the semiconductor layer is provided in the groove formed on the surface of the insulating substrate, and the groove has the first portion provided with the channel region, the source region, and the source region. A second portion provided with a drain region, wherein the second portion is formed deeper than the first portion. The upper surfaces of the channel region, the source region, and the drain region are located on the same plane as the surface of the insulating substrate.

According to the so-called coplanar thin film semiconductor device configured as described above, the thickness of the source region and the drain region is made larger than that of the channel region to increase off-leakage. The probability of activation failure after the ion implantation step is drastically reduced without problems such as a decrease in throughput due to an increase in power and an increase in unevenness of the polysilicon surface.

Further, since the upper surface of the entire channel, source, and drain regions and the surface of the insulating substrate on which they are formed are located on the same plane and are flat, disconnection of the wiring formed thereabove, The probability of a short circuit at the intersection is reduced.

Further, by forming a groove on the surface of the insulating substrate and providing at least a part of the source region and the drain region in the groove, the thin film of the source region and the drain region is thicker than the channel region. A semiconductor device can be obtained relatively easily.

[0016]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS Hereinafter, a coplanar thin film semiconductor device according to an embodiment of the present invention will be described in detail with reference to the drawings. As shown in FIG. 1, the thin-film semiconductor device includes an insulating substrate 10 made of, for example, transparent glass, and a groove 12 is formed on the surface of the insulating substrate 10. The groove 12 has a first portion 12a and a pair of second portions 12b located continuously on both sides of the first portion, and the second portion is formed deeper than the first portion. For example, the first portion 12a is formed at a depth of 50 nm, and the second portion is formed at a depth of 80 nm.

In the trench 10, a semiconductor layer 14 made of polysilicon is formed. The semiconductor layer 14 has a channel region 14a, and a source region 14b and a drain region 14c located on both sides of the channel region. The channel region 14a is formed in the first portion 12a of the groove 12, and the source region 14a and the drain region 14b are formed in the second portion 12b of the groove 12, respectively.

The channel region 14a and the source region 1
4b and the drain region 14c are formed such that their upper surfaces are located on the same plane as the surface of the insulating substrate 10. Therefore, the channel region 14a has a thickness of 50 nm, and the source region 14b and the drain region 14c have a thickness of 80n.
m and the source region 1 is larger than the channel region 14a.
4b and the drain region 14c are formed thicker.

A gate insulating film 16 is formed on the surfaces of the semiconductor layer 14 and the insulating substrate 10, and a gate electrode 18 is formed on the gate insulating film 16 so as to face the channel region 14a. Further, an interlayer insulating film 20 is formed on the gate electrode 18.

On the interlayer insulating film 20, a source region 14b
A source electrode 22 and a drain electrode 24 are formed to face the drain region 14c, respectively. The source electrode 22 and the drain electrode 24 are connected to the source region 14b and the drain region 14c via contact holes 26 and 27, respectively. Also,
The drain electrode 24 is formed on the I
While being connected to the pixel electrode 28 made of TO,
A passivation 30 is formed to cover the source electrode 22 and the drain electrode 24.

The thin film semiconductor device having the above structure is manufactured by the following steps. First, as shown in FIG. 2A, a groove 12 is formed in a portion of the surface of an insulating substrate 10 made of transparent glass where a semiconductor layer 14 is formed. In this case, grooves are formed by photolithography in portions of the surface of the insulating substrate 10 that will be the source and drain regions.
The channel 12, the source, and the drain region are etched again by the photo-etching method to form the groove 12. At this time, the trench 12 is formed so that the depth of the first portion 12a serving as a channel region is 50 nm and the depth of the second portion 12b serving as a source region and a drain region is 80 nm.

The groove 12 may be formed by etch back using a photoresist. That is, a photoresist is formed on the surface of the insulating substrate in which a portion corresponding to the channel region is opened and a film thickness of a portion corresponding to the source and drain regions is smaller than that of a peripheral portion where the semiconductor layer is not present. By etching back the entire surface of the insulating substrate, a groove may be formed that includes the entire channel, source, and drain regions, and that has a source and drain region portion deeper than the channel region portion. A photoresist having such a structure is prepared by exposing the channel region under normal conditions, and then exposing and developing the source and drain regions with reduced exposure.

Subsequently, as shown in FIG. 2B, an amorphous silicon thin film 50 is formed on the surface of the insulating substrate 10 to a thickness of 100 nm by using the plasma CVD method. Then, the amorphous silicon thin film 50 is crystallized by an excimer laser or the like to obtain a polysilicon film 50.

Next, as shown in FIG. 2C, a photoresist is applied on the polysilicon film 50, and is etched back, so that the channel region 14a and the source region 1 are formed.
4b and an island-shaped polysilicon layer 52 to be the drain region 14c.

As shown in FIG. 2D, a silicon oxide film to be the gate insulating film 16 is formed on the surface of the polysilicon layer 52 and the insulating substrate 10 by a plasma CVD method for 100 nm.
m. Subsequently, after a metal thin film is formed on the gate insulating film 16 to a thickness of 200 nm by a sputtering method, portions other than necessary portions such as a gate wiring portion are removed by a photolithography method to form a gate electrode 18.

Subsequently, as shown in FIG. 3A, ions such as phosphorus are implanted into the polysilicon layer 52 in a self-aligned manner using the gate electrode 18 as a mask to form a source region 14b and a drain region 14c. I do. Thereafter, the polysilicon layer 52 is activated by performing a heat treatment at 600 ° C. for 3 hours.

Next, as shown in FIG. 3B, a silicon oxide film to be an interlayer insulating film 20 is formed on the gate electrode 18 and the gate insulating layer 16 by a plasma CVD method.
Further, an ITO film having a thickness of 100 nm is formed on the interlayer insulating film 20, and the ITO film other than the necessary portions is formed by photolithography.
Is removed to form the pixel electrode 28.

Subsequently, as shown in FIG. 3C, the gate insulating film 16 and the interlayer insulating film 20 are formed by photolithography.
Then, contact holes 26 and 27 which are opened in the source region 14b and the drain region 14c of the polysilicon layer 52 are formed.

After that, aluminum or an alloy thereof is deposited on the interlayer insulating film 20 by sputtering.
Formed to a thickness of 00 nm, source by photo engraving,
By removing portions other than the drain portion, the source electrode 22 is removed.
And a wiring including the drain electrode 24 is completed. Subsequently, a silicon nitride film serving as a passivation 30 is formed to a thickness of 100 nm by a plasma CVD method, and portions other than necessary portions are removed by a photolithography method, thereby completing a thin film semiconductor device.

According to the thin film semiconductor device configured as described above, the semiconductor layer 14 made of polysilicon is provided in the groove 12 formed on the surface of the insulating substrate 10 and forms the source region 14b and the drain region 14c. The depth of the groove in the portion is formed deeper than the depth of the groove in the channel region 14a. This makes it possible to relatively easily obtain a thin-film semiconductor device in which the source region 14b and the drain region 14c are thicker than the channel region 14a.

Therefore, it is possible to prevent an increase in off-leakage and to drastically reduce the probability of activation failure after the ion implantation step. At the same time, the power required for crystallization of the amorphous silicon layer by laser irradiation can be reduced, and a decrease in throughput can be prevented.

Further, according to the thin film semiconductor device, the upper surfaces of the entire channel, source, and drain regions of the semiconductor layer 14 are located on the same plane as the surface of the insulating substrate 10 on which these are formed, and are flat. For this reason, the surface of the semiconductor layer does not become uneven, and the probability of disconnection of a wiring formed above the semiconductor layer 14 and a short circuit at an intersection can be reduced.

The present invention is not limited to the above-described embodiment, but can be variously modified within the scope of the present invention. For example, in the above embodiment, the entire semiconductor layer 14 is formed in the groove 12 formed in the insulating substrate. However, at least a part of the source region and the drain region is formed so as to be located in the groove. May be.

In other words, according to another embodiment shown in FIG. 4, grooves 12 are formed only in the portions of the surface of insulating substrate 10 where the source region and the drain region are to be formed. A semiconductor layer 14 is provided. Then, the source region 14b and the drain region 14
Only the lower end portion of c is accommodated in the groove 12. However, the upper surfaces of the channel region 14a, the source region 14b, and the drain region 14c are located on the same plane and are flat.

Even in such a configuration, the thickness of the source region 14b and the drain region 14c can be easily made larger than the thickness of the channel region 14a, and the same operation and effect as in the above-described embodiment can be obtained. Obtainable.
Other configurations are the same as those of the above-described embodiment, and the same portions are denoted by the same reference numerals and detailed description thereof will be omitted.

In the above embodiment, the semiconductor layer is provided directly on the insulating substrate. However, an undercoat may be provided between the insulating substrate and the semiconductor layer. The groove may be provided in the groove.

In the above-described embodiment, the polycrystalline silicon thin film forming the semiconductor layer is formed by the laser annealing method. However, the semiconductor layer may be obtained by solid-phase growing amorphous silicon. In the step of forming the channel region, the source region, and the drain region, an etch-back method using a photoresist is used, but a method of mechanically polishing the surface may be used.

The gate electrode is not limited to a metal thin film formed by a sputtering method, but may be a silicon thin film to which impurities are added. Further, the n-type thin film semiconductor device using phosphorus as an impurity to be implanted into the polysilicon layer has been described.
A complementary MOS semiconductor device in which the p-type is formed on the same substrate may be used.

The interlayer insulating film is not limited to a silicon oxide film formed by a plasma CVD method, but may be a silicon oxide film formed by a thermal CVD method or a sputtering method. In this case, another film can be used instead of the silicon oxide film as long as the film has an insulating property. Further, the source electrode and the drain electrode are made of aluminum,
Not only the alloy thin film but also other conductive materials may be used.

[0040]

As described above in detail, according to the present invention, the semiconductor layer is provided in a state where at least a part of the source region and the drain region is accommodated in the groove formed on the surface of the insulating substrate. A thin film semiconductor in which the thickness of the region and the drain region can be easily made larger than the thickness of the channel region, and the activation failure of the silicon layer after ion implantation can be prevented without causing characteristic deterioration and throughput reduction. An apparatus can be provided.

[Brief description of the drawings]

FIG. 1 is a sectional view of a thin film semiconductor device according to an embodiment of the present invention.

FIG. 2 is a cross-sectional view showing a step of manufacturing the thin-film semiconductor device.

FIG. 3 is a cross-sectional view showing a step of manufacturing the thin film semiconductor device.

FIG. 4 is a sectional view of a thin film semiconductor device according to another embodiment of the present invention.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 ... Insulating substrate 12 ... Groove 12a ... 1st part 12b ... 2nd part 14 ... Semiconductor layer 14a ... Channel region 14b ... Source region 14c ... Drain region 16 ... Gate insulating film 18 ... Gate electrode 20 ... Interlayer insulating film 22 ... Source Electrode 24 ... Drain electrode

Claims (4)

[Claims] A semiconductor layer provided on an insulating substrate and having a channel region and source and drain regions located on both sides of the channel region; and a gate insulating film formed on the semiconductor layer. And a gate electrode formed on a gate insulating film so as to face the channel region. The upper surfaces of the channel region, the source region, and the drain region are located on the same plane, and the source region and the drain The thin film semiconductor device, wherein the region has a larger thickness than the channel region. 2. A semiconductor layer provided on an insulating substrate and having a channel region and source and drain regions located on both sides of the channel region, and a gate insulating film formed on the semiconductor layer. A gate electrode formed on a gate insulating film facing the channel region; an interlayer insulating layer formed on the gate insulating film and the gate electrode; and a gate electrode formed on the interlayer insulating layer. A source electrode and a drain electrode connected to the source region and the drain region, respectively, at least a part of the source region and the drain region of the semiconductor layer are provided in grooves formed on the surface of the insulating substrate, The source region and the drain region are formed to be thicker than the channel region, and Le area, thin film semiconductor device each of the upper surface of the source region, the drain region, characterized in that the are located on the same plane. 3. An insulating substrate having a groove formed on a surface thereof, a channel region, and a source region and a drain region located on both sides of the channel region, the semiconductor being provided in the groove of the insulating substrate. A layer, a gate insulating film formed on the semiconductor layer, a gate electrode formed on the gate insulating film facing the channel region, and an interlayer insulating layer formed on the gate insulating film and the gate electrode And a source electrode and a drain electrode formed on the interlayer insulating layer and connected to the source region and the drain region, respectively, wherein the groove of the insulating substrate has a first surface provided with the channel region. A second portion provided with the source region and the drain region, wherein the second portion is formed deeper than the first portion; A thin film semiconductor device, wherein upper surfaces of the region and the drain region are located on the same plane as the surface of the insulating substrate. 4. The first portion of the groove has a depth of 30 nm to 1 nm.
4. The thin film semiconductor device according to claim 3, wherein the second portion is formed to a thickness of 80 nm to 150 nm.