KR20010019665A - Method of forming top gate type Thin Film Transistor - Google Patents

Abstract

PURPOSE: A method for forming a top-gate polysilicon thin film transistor is provided so that the whole formation process can be simplified by introducing two-step tone exposure. CONSTITUTION: A polysilicon film, a gate insulating film and a gate film are sequentially stacked on a substrate. A two-layer photoresist pattern is formed thereon according to a photolithography process using two-step tone exposure. In order to divide regions of a transistor, the gate film, gate insulating film and polysilicon film are sequentially etched and removed by using the photoresist pattern as an etching mask. The photoresist pattern is wholly etched, so that a thick portion of the photoresist pattern can remain. A gate film pattern having an undercut is formed according to isotropic etching, and a gate insulating film pattern is formed according to succeeding etching. A highly-doped low energy N type material is ion-implanted by using the gate etching pattern as an ion implantation mask. A gate etching pattern is formed in a P type transistor region. Thereafter, a gate film pattern and a gate insulating film pattern are formed in the P type transistor region according to anisotropic etching. A highly-doped low energy P type ions are implanted.

Description

Method of manufacturing top gate polysilicon thin film transistor {Method of forming top gate type Thin Film Transistor}

The present invention relates to a method of manufacturing a top gate polysilicon thin film transistor, and more particularly, to alleviate or solve the existing process problems when using a photoresist as an ion implantation mask and to reduce the process The present invention relates to a method of manufacturing a top gate polysilicon thin film transistor.

In recent years, the most actively developing field in relation to the display device is the LCD field, and the development of the active matrix type TFT LCD field is remarkable. The LCD roughly injects liquid crystal between two substrates and applies voltage to two electrodes formed inside the substrate to adjust the arrangement of liquid crystals therebetween, thereby transmitting or blocking light in relation to the polarizing plate attached to the substrate. The principle is to use.

The TFT LCD controls the electrodes of the individual pixels forming the screen of the display device by using a transistor, which is a nonlinear element, in which the transistor is formed on a glass substrate using a semiconductor thin film. TFT LCDs can be roughly divided into amorphous silicon type and polysilicon type according to the characteristics of the semiconductor thin film used.

Either way, efforts are being made to reduce the number of exposure steps in the process in order to reduce process costs and increase yields.Amorphous silicon can be formed using CVD at low temperatures, which is advantageous due to the characteristics of LCDs using glass substrates. There is a point. However, amorphous silicon is not suitable for forming a transistor element of a driving circuit requiring low operating characteristics due to low carrier mobility. This fact means that the IC for driving the LCD must be manufactured separately and attached to the LCD panel periphery, and the LCD manufacturing cost increases due to the increased process for the driving module.

On the other hand, polysilicon has a much higher mobility of carriers than amorphous silicon, and thus can be used to manufacture ICs for driving circuits. Therefore, when polysilicon is used as a semiconductor thin film for forming TFTs of LCDs, a TFT device for pixel electrodes and a TFT for driving circuits can be formed together on a same glass substrate through a series of processes. This has the effect of reducing the cost of the module process in LCD manufacturing, and at the same time lowers the power consumption of the LCD.

However, in the case of using polysilicon, in order to form a polysilicon thin film on a glass substrate, an amorphous silicon thin film is first formed through a low temperature CVD process and an additional process for crystallization such as irradiating a laser beam is required. When the gate voltage is turned OFF in the transistor formed by the high degree, the leakage current (OFF Current) is excessively flowed, thereby preventing a sufficient electric field from being maintained in the pixel portion. As a method of suppressing the occurrence of the leakage current, the LDD region having low impurity concentration or an offset region without impurity ion implantation is provided at the junction between the source and drain regions of the thin film transistor and the channel. It is generally used to act as a barrier to the. In addition, since the N-channel and P-channel thin film transistors must be formed on one substrate, the P-channel is sealed with a protective layer to prevent ion implantation and the N-channel region is formed during the formation of the P-channel thin film transistor. It must also be sealed with a protective layer.

Further considerations in this process for forming polysilicon thin film transistors increase the number of photolithography processes, thus increasing the manufacturing cost of polysilicon thin film transistors. In addition, the LDD formation and the formation of the N and P channels require an ion implantation process. When the ion implantation is made with a large amount of energy, the ion implantation energy is eventually converted into heat, thereby increasing the temperature of the substrate. In some cases, the process may be impossible by increasing the substrate temperature to an unacceptable temperature for the glass substrate. However, the photoresist is used to denature the photoresist applied to the substrate as an etching mask or an ion implantation mask even if the temperature is not reached. It may cause resist burning.

Photoresist burning is caused by the conversion of ion implantation energy into heat when ion implanted onto the photoresist, but it appears that the energy of individual ions at the time of ion implantation triggers a direct reaction to change the properties of the photoresist. This can be seen by comparing the change in photoresist when the same heat is applied to the photoresist. Unlike the general photoresist, the modified photoresist does not remove well through the strip process and may cause various defects due to particles in the process. Therefore, ion implantation that causes photoresist burning may not be adopted in the process.

Recently, a technique developed in order to solve the problem of manufacturing a polysilicon thin film transistor is an LDD formation method using a gate auxiliary layer of a metal material as an ion implantation mask. In this method, first, a polysilicon pattern, a gate insulating film and a gate film are formed on a substrate. The gate pattern of the P-type transistor, which does not require the LDD structure, is formed first. In this case, general photolithography and etching are used. Then, the remaining photoresist is removed and P-type high concentration high energy ion implantation is performed. At this time, the region of the N-type transistor is protected from ion implantation because the gate film is covered as it is. Next, a metal gate auxiliary film is stacked on the entire substrate, and then the P-type transistor region is covered with the gate auxiliary film, and in the N-type transistor region requiring the LDD structure, a gate pattern consisting of the gate film and the gate auxiliary film is formed. In this case, photolithography and etching are used, and the etching uses an isotropic etching method such as wet etching. In addition, the gate auxiliary layer pattern is formed to protrude outward from the gate layer pattern by using a material difference between the gate layer and the gate auxiliary layer and an undercut phenomenon of isotropic etching. Then, a high concentration high energy N-type ion implantation is performed on the gate pattern composed of these two films. The remaining photoresist film is previously removed. Subsequently, the gate auxiliary film is removed and low concentration high energy ion implantation is performed. In this case, since the gate auxiliary layer is also removed in the P-type transistor region, the basic gate source drain structures of the N-type and P-type transistors are formed as a whole.

According to the LDD formation method using the undercut in the gate auxiliary layer, since the photoresist does not remain on the substrate when the ion implantation is performed, the gate layer or the gate auxiliary layer acts as an ion implantation mask and eliminates the problems caused by photoresist burning. . However, this technology uses chromium, which can increase the etching selectivity of aluminum, aluminum alloy, and gate as an etching solution for aluminum as a gate film. When annealing is performed to activate the polysilicon layer, the gate layer has a problem in that a pin hole is formed in a portion of the gate pattern due to the action of chromium and nemium in the case of aluminum nemium (AlNd).

In addition, the gate pattern made of the gate layer has a large angle of about 80 ° with the sidewall perpendicular to the etching process from the side during etching while using chromium as the gate auxiliary layer. When the step pattern is clearly formed in the gate pattern and the thickness of the interlayer insulating film stacked thereon is so thin that the step is revealed, the data wiring that passes over the gate pattern is uneven and stressed in the place where the step is exposed due to the gate pattern. Notch phenomenon where part is separated and width is reduced, or disconnection of wires are likely to occur.

The present invention solves problems that may occur in the process of using a photoresist as an ion implantation mask and a gate auxiliary layer as an ion implantation mask, which have been developed to date in manufacturing a conventional top gate type polysilicon thin film transistor. It is an object of the present invention to provide a method for manufacturing a new top gate type polysilicon thin film transistor. At the same time, an object of the present invention is to provide a method of manufacturing a top gate polysilicon thin film transistor which can reduce the number of processes which are problematic in polysilicon thin film transistor manufacturing.

1 to 12 are cross-sectional views illustrating a method of manufacturing a top gate type polysilicon thin film transistor according to an embodiment of the present invention.

FIG. 13 is a plan view of a unit pixel portion of a thin film transistor liquid crystal display manufactured by using a top gate type polysilicon thin film transistor formed through the process of FIG.

※ Name of code for main part of drawing

11: Substrate 11: Blocking layer

13,33,53: polysilicon layer 15: gate insulating film

17: gate film 21: photoresist pattern

26: drain region 28: source region

31, 51: gate etching pattern 35, 55: gate insulating film pattern

37, 57: gate film pattern 43: Lightly Doped Drain (LDD)

44: gate 46: storage capacitor

61: interlayer insulating film 67: metal layer

71: Shield 75,76,77: Contact

85: gate line 89: capacitor line

86: data line 90: pixel electrode

91,92: Contact 93: connecting plate

In order to achieve the above object, the method of manufacturing a top gate polysilicon thin film transistor of the present invention comprises sequentially stacking a polysilicon film, a gate insulating film, and a gate film on a substrate, and forming a gate film pattern through a photolithography process using two-step tone exposure. Forming a thick two-stage photoresist pattern in the N-type transistor region and forming a thick photoresist pattern in the P-type transistor region, and forming the photoresist pattern with an etch mask for the gate layer, Etching and removing the gate insulating layer and the polysilicon layer in order, forming a gate etching pattern by etching the photoresist pattern as a whole so that only a thick portion of the photoresist pattern remains, and isotropically forming the gate etching pattern as an etching mask. Under etching through Forming a gate layer pattern to be formed, and forming a gate insulating layer pattern through subsequent etching, performing ion implantation of a high concentration low energy N-type material using the gate etching pattern as an ion implantation mask, and removing the gate etching pattern Forming a gate etching pattern in the P-type transistor region with a photoresist layer and forming a protective pattern in the other region through a photolithography process; forming a gate layer pattern and a gate insulating layer in the P-type transistor region through anisotropic etching Forming a pattern, and performing a high concentration low energy P-type ion implantation.

In the present invention, the order of forming P-type and N-type transistors is determined and described. However, the order of forming P-type and N-type transistors can be interchanged. In this case, in the present invention, N and P may be replaced with each other. However, the use of isotropic etching when etching the gate pattern in the state where the gate etching pattern is formed may be limited to the N type.

The key part of the present invention is a gate insulating film in advance to enable the high-resistance high-energy ion implantation step, which is a step that causes photoresist burning in the past, to a high-concentration low-energy ion implantation step, to suppress photoresist burning and to enable low-energy ion implantation A removal step has been added. At the same time, in order to reduce the exposure process in one step, the process of dividing the transistor region and forming the gate pattern in the N-type transistor region is performed by using the exposure using two-step tone.

The two-stage tone exposure may be performed by using a reticle in which an image is formed in two-stage tones or by using a reticle that forms a plurality of slits in the midtone portion and implements midtones using diffraction. In this case, the photoresist exposed to the translucent intermediate tone is photoresist-induced by light of the intermediate value, and the upper layer is photodegraded and removed through development to form a photoresist pattern of medium thickness. When the reticle is formed in transparent tones, the corresponding part of the photoresist is completely exposed to cause photolysis in all layers and is removed through development, and the part of the photoresist corresponding to the completely opaque part on the reticle remains thick so that A pattern is formed.

Hereinafter, a method of forming a top gate type polysilicon thin film transistor of the present invention will be described with reference to the accompanying drawings.

FIG. 1 shows that a silicon oxide film is deposited on a glass substrate 10 as a blocking layer 11 by 2000 microseconds, and a polysilicon layer 13 500 microseconds to 800 microseconds without a separate buffer pattern is stacked thereon, followed by a gate insulating film 15 and a gate film ( 17) shows a state of being laminated in order. The blocking layer 11 may be omitted, and the polysilicon layer 13 is formed by depositing amorphous silicon and then laser recrystallization. Amorphous silicon deposited on the backside of the substrate prior to recrystallization is removed. The gate insulating film 15 is formed by stacking about 1000 실리콘 of silicon oxide film, and the gate film 17 is mainly formed by stacking 2000 Å to 3000 알 of aluminum-neodymium (AlNd) alloy. In general, the gate layer 17 may have a two-layer structure of an aluminum-containing metal and a molybdenum-containing metal, and a two-layer structure of an aluminum-containing metal and, in some cases, chromium. However, the gate layer 17 forms an undercut in etching to form a gate layer pattern. Or metals without problems in the annealing step after ion doping should be used.

FIG. 2 is a photolithography process using two-step tone exposure in the state of FIG. 1 to form a two-stage photoresist pattern having a thick gate portion and a thin other portion in the N-type transistor region and a thick photoresist in the P-type transistor region. After the pattern is formed, the gate layer 17, the gate insulating layer 15, and the polysilicon layer 13 in the exposed portions are sequentially etched using the photoresist pattern 21 as an etch mask to form an active region of the transistor. It shows the state removed.

3 illustrates a state in which the thick portion is left by etching the photoresist pattern 21 in the state of FIG. 2. At this time, the photoresist pattern becomes the gate etching pattern 31 and is uniformly anisotropically etched, so that only a thick portion, that is, a portion where the gate layer pattern is to be formed and a portion where the P-type transistor is to be formed, is often etched back. back etching). The etching of the photoresist is commonly performed through a process called ashing, in which a plasma is formed while oxygen is supplied to oxidize and remove an upper layer of the photoresist, which is an organic film.

FIG. 4 shows a state in which the lower gate layer 17 and the gate insulating layer 15 are etched and patterned using the gate etching pattern 31 in FIG. 3 as an etching mask. The gate etching pattern 31 obtained through the ashing of FIG. 3 has a form in which the sidewall is slightly inclined vertically. In addition, since the gate layer pattern 37 including the gate layer is formed by an isotropic etching such as wet etching, the gate layer pattern 37 must be formed while the undercut is reduced in the pattern formed of the photoresist. The size of the undercut for forming the LDD is about 0.5 to 1.5 μm, and in this embodiment, the size of the under cut is about 1 μm. The size is further reduced. Subsequently, the gate insulating layer 35 is also etched. The gate insulating layer 35 is formed to have the same width as that of the photoresist pattern through anisotropic etching, and thus, the width of the gate insulating layer 35 is 0.5 to 1.5 um larger than that of the gate layer pattern. In this case, it is particularly important to use an etchant having an etching ratio of 10: 1 or more so as not to damage the polysilicon layer 13 below when etching the gate insulating film. An example of such an etchant is a gas in which CHF ₃ is mixed with argon.

FIG. 5 is a cross-sectional view illustrating a state in which an N-type high concentration low energy ion implantation is performed without removing the photoresist in the state of FIG. 4. PH ₃ is commonly used as the N-type ion implantation material, and low energy ion implantation of 20 KeV is performed in this embodiment at 30 KeV or less based on high concentration ion implantation of 1.0E15 to 5.0E15 particles per unit Cm ² . In the conventional case, high energy ion implantation of about 90 KeV was performed at the same concentration, but the ion implantation energy was reduced because the gate insulating layer was removed in the gate patterning step. That is, since the implanted ions do not have to pass through the gate insulating film layer, the energy projected to the polysilicon layer is reduced accordingly, thereby reducing heat generation on the substrate and reducing the action of the photoresist, thereby preventing the curing phenomenon such as photoresist burning. Can be. In addition, if the ion implantation energy is small, the impact amount on the polysilicon during the ion implantation is reduced and damage is reduced, thereby reducing the energy for laser annealing in the subsequent activation step. If the energy for annealing is reduced, the temperature rise and an adverse effect of the annealing can be reduced. For example, in the conventional case, if chromium is left on the aluminum neodymium, the nedium reacts with the chromium in the annealing step. It can also be suppressed.

FIG. 6 shows a state in which the LDD 43 structure is formed by removing the gate etching pattern 31 made of photoresist and performing low concentration and high energy ion implantation in the state of FIG. 5. At this time, the ion implantation concentration is 1.0E12 to 8.0E12 per unit square centimeter, and the level of 1/1000 of the previous stage, and the incident energy is about 90KeV. The reason why ion implantation can be performed with such high energy without any problem is because ion implantation is performed at low concentration. In other words, the overall incident energy level to the substrate is low, approximately 1/100 level when high concentration low energy ion implantation is made. If the patterning of the gate insulating film is performed by etching the gate film pattern 37 with a mask in a state where the gate etching pattern 31 formed of the upper photoresist is removed in the previous step, low concentration and low energy ion implantation may be possible. In this step, the ion implantation may be performed without proceeding to the next step. In this case, an OFF SET structure rather than an LDD structure is formed in the N-type transistor. Also in this case, the P-type transistor region is protected by the gate film 17, thereby protecting it from high energy ion implantation.

In the present embodiment, the LDD 43 structure is formed for both the driving circuit and the N-type transistor in the pixel portion. However, in some cases, the LDD may be formed only for the N-type transistor in the driving circuit portion. However, in this case, an additional process for distinguishing the driving circuit unit from the pixel unit may be necessary.

FIG. 7 shows a gate etching pattern 51 in a P-type transistor region as a photoresist layer through a photolithography process in the state of FIG. 6 and a gate film pattern 57 and a gate insulating film pattern in the P-type transistor region through etching. (55) is formed and P type high concentration low energy ion implantation is shown. In this case, the gate insulating layer pattern 55 and the gate layer pattern 57 may have the same width as that of the gate etching pattern 51 formed of the photoresist through anisotropic etching. This is because the P-type transistor does not need to form an LDD structure. The N-type transistor region serves as a mask in the ion implantation and etching steps with the photoresist remaining to form a protective pattern. The injection amount and energy per unit area of particles used in ion implantation are the same as in the case of N type high concentration low energy ion implantation, and the material used for ion implantation is B ₂ H ₆ .

In the above embodiment, the N-type transistor is first formed and the P-type transistor is formed, but may be formed in a reversed order. However, the use of the undercut when etching the gate pattern in the state in which the gate etching pattern is formed may be limited to the N type.

FIG. 8 shows a state in which the photoresist is removed by ashing or the like in the state of FIG. 7 and then annealing for activating the polysilicon layers 33 and 53 using a laser is shown. As mentioned above, since the high concentration of ion implantation uses low energy, there is no conventional photoresist burning phenomenon and the photoresist may be removed through a general strip process. Compensation for structural damage of the polysilicon layers 33 and 53 by ion implantation and activation for diffusion of the implanted particles are carried out through laser annealing. You can use less energy.

FIG. 9 shows a state in which the interlayer insulating film 61 is formed in the state of FIG. 8 and patterning for contact is completed. The interlayer insulating film 61 is usually formed by stacking a silicon oxide film or a silicon nitride film by about 6000 kV to 8000 kV. In some cases, the interlayer insulating film 61 may be formed of a photosensitive organic film. In this case, since the etching process for patterning does not need to be performed separately, the process can be simplified.

FIG. 10 shows a state in which the metal layer 67 for contact and wiring is stacked and patterned in the state of FIG. For example, the metal layer is formed as a double layer of a lower aluminum aluminum layer on the upper layer of molybdenum tungsten (MoW) alloy, or a double layer of a chromium, titanium, Ta layer or the like in the aluminum neodymium alloy layer. On the other hand, before stacking the contact metal layer 67 in the state in which the interlayer insulating layer 61 is patterned, the sheet resistance is large at the contact interface between the polysilicon layers 33 and 53 and the metal layer 67, thereby applying the applied voltage. There are many cases of dropping and degrading the function of the transistor. In order to reduce such a problem of interfacial resistance, it is necessary to remove resistive materials that cause an increase in interfacial resistance as much as possible before stacking the metal layer 67. At this time, since the organic material and the surface oxide, which tend to act as resistances, have different properties, it is preferable to clean the two resistance materials according to the process. For example, plasma cleaning may be performed while supplying hydrofluoric acid (HF) or mixed gas of CF ₄ and oxygen to remove the oxide film, and then dry cleaning may be performed by applying plasma using argon or the like. In addition, since the contact surface between the polysilicon layers 33 and 53 and the metal layer 67 is not made of a material such as polysilicon and has poor electrical conductivity, polysilicon is 350 to 450 ° C for electrical contact between interfaces through annealing. It is desirable to increase. Annealing to activate polysilicon after ion implantation may also be done at this stage.

In the conventional case, the contacts are usually in contact with the buffer layer through the polysilicon layer. The buffer layer is formed for the stability of the contact between the polysilicon layer and the metal layer for forming the source drain electrode in case the polysilicon layer is etched during the contact hole formation to reduce the contact surface. In this case, the electrical conductivity is amorphous silicon. Since the polysilicon layer is much higher than the buffer layer made, substantial contact is made between the polysilicon layer and the metal layer. However, in the case of high concentration low energy ion implantation as in the present invention, since impurities may be introduced into the polysilicon layer without passing through the gate insulating film, the same number of impurity particles as the number of projected particles are injected into the polysilicon to improve conductivity. . In this case, since the contact stability can be secured without forming the buffer, the process steps for stacking and patterning the amorphous silicon film for forming the buffer can be reduced.

FIG. 11 shows a state in which the protective film 71 is formed and patterned on it in the state of FIG. As the protective film, both an organic film and an inorganic film can be used, and a photosensitive organic film is often formed to a thickness of about 3 μm.

FIG. 12 illustrates a state in which the pixel electrode 90 is formed by stacking and patterning the transparent electrode layer in the state of FIG. As the transparent electrode, indium tin oxide (ITO), which is most efficient in light transmission, is used a lot, but indium zinc oxide (IZO) may be used instead.

FIG. 13 is a plan view of a thin film transistor manufactured by a top gate polysilicon thin film transistor formed through the process as shown in FIG. In this case, since a leakage current may flow through the semiconductor layer because the semiconductor layer remains under the gate, the gate line must be removed pixel by pixel from the gate patterning step to the lower semiconductor layer. Then, when forming the source and drain electrodes, a gate line connection part which is broken in pixel units is formed. The same can be said for the capacitor line. In more detail below, the upper portion of the gate layer pattern shows a storage capacitor 46 for a storage capacitor and the lower portion shows a gate 44 of an N-type transistor. Since the gate insulating film and the polysilicon layer are formed under the gate film pattern, the gate film pattern, that is, the gate and the capacitor are connected in one line to prevent the formation of a channel in which signals applied to electrodes from other pixels affect neighboring pixels. Does not form. Instead, gates and capacitors are formed in each pixel portion, and contact holes are formed upward to form contacts and drain electrodes, so that the gates and capacitors are connected to each other to form gates and drain electrodes. A gate line 85 and a capacitor line 89 connecting the capacitor and the capacitor are formed.

Although not separately indicated, the LDD region is formed at a portion where the gate insulating film remains and the active region, that is, the region having polysilicon, overlap. Source region 28 is connected to source electrode and data line 86 via contact 76 and drain region 26 is connected to drain electrode via contact, which in turn connects to contact 91 over drain electrode. The connecting plate 93 is connected to the pixel electrode 90 through the contact 92 formed on the connecting plate 93.

According to the present invention, the process can be reduced through two-step tone exposure, and the photoresist can be prevented from burning in relation to ion implantation in the manufacturing process of the top gate polysilicon thin film transistor, and low energy during high ion implantation Since the incident, the polysilicon structure is less damaged, the input energy of the annealing is reduced, and the problems resulting from the annealing are relatively reduced. In addition, since impurity ions are introduced into the polysilicon without passing through the gate insulating film, even when the same number of particles are added, the amount of polysilicon is increased, which increases the conductivity of the polysilicon to form the polysilicon and the source drain metal film. Helps reduce interfacial resistance with closed contacts. If the resistance of the interface is reduced, there is no need to form a buffer, which increases the reliability of the contact between the polysilicon and the metal layer, thereby reducing the number of processes.

Claims (11)

Stacking a polysilicon film, a gate insulating film, and a gate film on the substrate in sequence; Forming a two-stage photoresist pattern in the N-type transistor region and forming a thick photoresist pattern in the P-type transistor region through a photolithography process using two-step tone exposure; Etching and removing the gate layer, the gate insulating layer, and the polysilicon layer in order to form a region of the transistor using the photoresist pattern as an etch mask; Forming a gate etching pattern by etching the photoresist pattern as a whole so that only a thick portion of the photoresist pattern remains; Forming a gate layer pattern in which an undercut is formed through isotropic etching using the gate etching pattern as an etching mask, and forming a gate insulating layer pattern through subsequent etching; Performing ion implantation of high concentration low energy N-type material using the gate etching pattern as an ion implantation mask; Removing the gate etching pattern; Forming a gate etching pattern in the P-type transistor region with a photoresist layer and forming a protective pattern in the other region through a photolithography process; Forming a gate film pattern and a gate insulating film pattern in the P-type transistor region through anisotropic etching; and A method of manufacturing a top gate polysilicon thin film transistor, comprising the step of performing a high concentration low energy P-type ion implantation. The method of claim 1, A method of manufacturing a top gate polysilicon thin film transistor according to claim 1, further comprising ion implanting N-type impurities at low concentration and high energy following the removing of the gate etching pattern. The method according to claim 1 or 2, The etchant used in the step of forming the gate insulating film pattern through etching is characterized in that the selectivity to the polysilicon pattern is characterized in that less than 1/10 of the gate insulating film, polysilicon thin film transistor manufacturing method. . The method of claim 3, wherein The etchant gas is a mixed gas of argon and CHF ₃ Top gate type polysilicon thin film transistor manufacturing method. The method of claim 1, And an annealing step for activation to recover structural damage of the polysilicon pattern after the ion implantation is completed. The method of claim 5, After the ion implantation is completed, forming an interlayer insulating layer over the gate pattern and performing patterning for forming a contact hole exposing a source drain region of the polysilicon pattern; Cleaning the exposed contact holes; Stacking and patterning metal layers for contacts and wiring, Stacking a protective film and patterning a contact hole to expose a drain electrode formed of the metal layer; A method of manufacturing a top gate polysilicon thin film transistor, the method comprising: forming a pixel electrode by stacking and patterning a pixel electrode layer. The method of claim 6, The protective film is a photosensitive organic film manufacturing method of a top gate type polysilicon thin film transistor. The method of claim 6, The cleaning of the contact hole may be performed by performing a plasma cleaning while supplying hydrofluoric acid (HF) gas to remove an oxide film, and then performing dry cleaning by applying plasma using argon. And annealing at 350 ° C. to 450 ° C. with respect to the contact interface between the polysilicon pattern and the metal layer. The method of claim 8, The annealing step for the activation is performed in the annealing treatment step for the contact interface as in the top gate type polysilicon thin film transistor manufacturing method. The method of claim 6, The pixel electrode is a IZO top gate polysilicon thin film transistor manufacturing method characterized in that. The method of claim 1, The gate etching pattern and the gate insulating layer pattern in the N-type transistor region is a width of 0.5 to 1.5 μm larger than the gate layer pattern is formed, characterized in that the top gate type polysilicon thin film transistor manufacturing method.