JP2000332254A - Thin-film transistor device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enable manufacture of a liquid-crystal display device, having satisfactory display quality with a high manufacturing yield by preventing poor display characteristics due to degradation of voltage-retaining characteristics of a pixel electrode or circuit leakage in using a TFT in the liquid-crystal display device, wherein the current along side surface of a semiconductor layer brings adverse effects to the characteristics of the TFT. SOLUTION: In a thin-film transistor device, the side surfaces of semiconductor layers 21, 22 are made amorphous and then oxidized to form underlying regions 23, 24 underneath the gate insulating film 27, and further a silicon oxide(SiO2) film 26, which is the surface region of the gate insulating film 27, is formed on the semiconductor layers 21, 22. Thereby, the film thickness on the side surfaces of the semiconductor layers 21, 22 is larger than the film thickness of the gate insulating film 27. As a consequence, the characteristics of an n-type p-SiTFT 16 and of a p-type p-SiTFT are stabilized, and lowering of the yield due to poor display characteristics of the liquid-crystal display device is prevented.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a top gate type thin film transistor device having a gate electrode on a semiconductor layer via a gate insulating film.

[0002]

2. Description of the Related Art In recent years, a thin film transistor device (hereinafter abbreviated as TFT) using a polycrystalline silicon (hereinafter abbreviated as p-Si) film or an amorphous silicon (hereinafter abbreviated as a-Si) film as a semiconductor layer. The active matrix type liquid crystal display device, which uses p-Si as a semiconductor layer, has a high mobility and good semiconductor characteristics. Accordingly, practical use as a drive circuit element for operating the switching element of the pixel electrode has been attempted.

The structure of such a p-Si TFT is such that a source region and a drain region are formed with high manufacturing accuracy by implanting impurities into a p-Si film in a self-aligned manner using a gate electrode as a mask. The top gate type shown in FIGS. 9 to 11 is often used. That is, p-Si is formed on the glass substrate 1 through the undercoat layer 1a.
After the film 2 is formed in an island shape, the p-Si film 2 is covered with a gate insulating film 3 made of silicon oxide (SiO ₂ ), a gate electrode 4 is formed on the gate insulating film 3, and the gate electrode is masked. Then, an impurity is implanted into the p-Si film 2 in a self-aligned manner to form a source region 6 and a drain region 7.
Then, after further forming the interlayer insulating film 8, the interlayer insulating film 8 is formed.
The signal lines 10 and 11 are wired thereon, connected to the source region 6 or the drain region 7 via the contact holes, and the p-
The SiTFT 12 was formed.

[0004]

In the p-SiTFT12 of however the top gate type [0005] has a gate insulating film is a silicon oxide (SiO _2), p-Si film 2
The film becomes thin on the side surface. Moreover, since the gate electrode 4 is also wired above the side surfaces 2a and 2b of the island-shaped p-Si film 2, the p-Si TFT 12 is affected by the side surfaces 2a and 2b of the p-Si film 2, and its characteristics are as follows. In addition to the current flowing on the upper surface of the p-Si film 2, the side surfaces 2a, 2b of the p-Si film 2
The current flowing through the side is superposed, and this side 2
a, 2b are particularly low current p-SiT
The current characteristics of the FT 12 are affected.

Therefore, when such a p-Si TFT 12 is used as a switching element of a pixel electrode of a liquid crystal display device, its voltage holding characteristic is reduced. On the other hand, when it is used as a driving circuit element, it causes a circuit leak, and the rise of current is slow. There has been a problem that uniform display is not achieved, and spots are formed on an image, resulting in remarkable deterioration of display quality and poor display.

Accordingly, the present invention has been made to solve the above-mentioned problem, and a p-Si TFT in a top gate type p-Si TFT has been proposed.
The effect of the current on the side surface of the film is reduced, the characteristics are stabilized, and when a p-Si TFT is used in a liquid crystal display device, the voltage holding characteristic of the pixel electrode is improved, or the leakage of the driving circuit element is prevented. It is an object of the present invention to provide a thin film transistor device capable of obtaining a liquid crystal display device having good display quality at a high yield.

[0007]

In order to solve the above-mentioned problems, the present invention provides an insulating substrate, a channel region formed on the insulating substrate in an island shape, and a source region and a drain region sandwiching the channel region. A semiconductor layer having a region, a gate insulating film covering the semiconductor layer such that a film thickness applied to a side surface of the semiconductor layer is thicker than a film thickness applied to an upper surface of the semiconductor layer, and And a gate electrode formed in a region corresponding to the channel region.

With the above structure, the insulating property on the side surface of the p-Si film is improved, so that the p-Si film has stable semiconductor characteristics.
-Si TFT can be obtained. Therefore, such a p
-If the SiTFT is used in a liquid crystal display device, the pixel electrode can hold a display image well, and in the case of a drive circuit element, stable drive characteristics can be obtained, so that display quality can be improved and yield due to display failure can be reduced. Prevention of the reduction also makes it possible to reduce the manufacturing cost.

[0009]

FIG. 1 is a block diagram showing an embodiment of the present invention.
This will be described with reference to FIGS. FIG. 1 shows, for example, an n-type p-Si TFT 16 for driving a pixel electrode (not shown) of a liquid crystal display device (not shown) and a p-type TFT 16 used as a drive circuit.
3 shows a type p-Si TFT 17. n-type p-Si TFT16
Further, the p-type p-Si TFT 17 is a top gate type, and a film thickness of 3 is formed on a glass substrate 18 which is an insulating substrate.
N-type p-Si TFT having a thickness of 50 nm through an undercoat layer 20 made of 00 nm silicon nitride (SiN _x )
Sixteen semiconductor layers 21 and a semiconductor layer 22 of the p-type p-Si TFT 17 are patterned in an island shape.

The semiconductor layer 21 includes a channel region 21a and a channel region 21a.
Phosphorus (P) adjacent to the channel region 21a. ⁺) Low concentration of ions
LDD (Lightly Doped)
 Drain) regions 21b and 21c, and LDD region 2
Phosphorus (P) adjacent to 1b, 21c⁺) Doping ions at high concentration
Source region 21d and drain region 21
e. The semiconductor layer 22 includes a channel region 22
a and boron (B⁺) Doping ions at high concentration
Source region 22b and drain region 22c
I have.

On the side surfaces of the semiconductor layers 21 and 22, underlying regions 23 and 2 formed by oxidizing amorphous p-Si are formed.
4 are adjacent to each other, and the semiconductor layers 21 and 22 have a surface region of 100 nm thick silicon oxide (SiO 2) from above.
₂ ) Coated with film 26. This silicon oxide (Si
The O ₂ ) film 26 constitutes a gate insulating film 27 together with the underlying regions 23 and 24. That is, the gate insulating film 27 is formed on the upper surfaces of the semiconductor layers 21 and 22 by silicon oxide (Si).
O ₂₎ film made 26 alone, its thickness is set to 100 nm, In the side surface of the semiconductor layer 21, underlying region 2
3, 24 and a silicon oxide (SiO ₂ ) film 26 having a thickness of 500 nm.

A gate insulating film 27 is formed on the semiconductor layers 21 and 22 at a position corresponding to the channel regions 21a and 22a.
The gate electrodes 28 and 30 having a thickness of 250 nm formed of a metal film which is an alloy of molybdenum (Mo) and tungsten (W) and formed integrally with a gate line (not shown) are formed through the silicon oxide film. It is covered with an interlayer insulating film 46 made of (SiO ₂ ). Contact holes are formed in the interlayer insulating film 46 and the gate insulating film 27, and molybdenum (Mo), aluminum (Al), and molybdenum (Mo) are sequentially deposited through the contact holes.
nm, 400 nm, and 50 nm stacked source region 2
Source electrodes 47 and 48 connected to 1d and 22b;
Drain electrodes 50 and 51 connected to the drain regions 21e and 22c are formed.

Next, referring to FIGS. 2 and 3, n-type p-Si
A method for manufacturing the TFT 16 and the p-type p-Si TFT 17 will be described. First, as shown in FIG. 2A, an undercoat layer 20 made of a silicon nitride (SiN _x ) film and an a-Si layer 32 are formed on a glass substrate 18 by plasma CVD (C).
chemical Vapor Deposition
Films of 300 nm and 50 nm are formed by the method n). Thereafter, annealing is performed at 600 ° C. for 1 hour, dehydrogenation is performed so that the hydrogen concentration in the a-Si layer 32 becomes approximately 0.1 atomic% or less, and boron ions (B ⁺ ) are formed as shown in FIG. Ion doping of about 1E12 / cm ^{2 and} ELA
The a-Si layer 32 is instantaneously melted by irradiating a XeCl excimer laser by an (excimer laser annealing) method, and polycrystallized to form a p-Si layer 33.

Next, as shown in FIG. 2C, the p-Si layer 3
PEP (Photo Engraving Pr)
The photoresists 36 and 37 are pattern-formed by the process, and the semiconductor layers 21 and 22 are patterned by etching the p-Si layer 33 into an island shape using the photoresists 36 and 37 as a mask. Thereafter, as shown in FIG. 2D, photoresists 36 and 37 are formed by ashing.
Is receded, and argon ions (Ar) are implanted into the side surfaces of the semiconductor layers 21 and 22 at 10 keV to make the side surfaces of the semiconductor layers 21 and 22 amorphous. Thus, when the side surface is oxidized by the oxygen (O ₂ ) plasma in the next step, not only the surface but also the entire region can be oxidized.

Next, after removing the photoresists 36 and 37, the entire regions on the side surfaces of the semiconductor layers 21 and 22 which have been made amorphous are oxidized by oxygen (O ₂ ) plasma to form the underlying regions 23 and 22 as shown in FIG. 24 are formed. FIG. 2
As shown in FIG. 1F, TEOS (tetra et al.) Is formed on the semiconductor layers 21 and 22 on which the underlying regions 23 and 24 are formed.
silicon oxide (Si) by a plasma CVD method using hydrogen orthosilicate as a raw material.
An O ₂ ) film 26 is grown to a thickness of about 100 nm to form a gate insulating film 27.

Subsequently, as shown in FIG. 2 (g), a metal film 40 made of an alloy of molybdenum (Mo) and tungsten (W) is formed to a thickness of 250 nm by a sputtering method, and then the photo film formed by the PEP method is formed. Using a resist (not shown) as a mask, the metal film 40 is etched to pattern the gate electrodes 28 and 30, and then, as shown in FIG. 2H, phosphorus ions (P ⁺ ) are added at a dose of 3E13 /
Low concentration ion doping is performed at a pressure of 80 keV and cm ² .

Next, after a resist is applied, p
Photoresist 4 covering the whole of the p-Si TFT 17
After patterning a photoresist 42 covering an area slightly larger than the gate electrode 28 of the 1-type and n-type p-Si TFTs 16, as shown in FIG.
₃ ) Phosphorus ions (P ⁺ ) are added using gas and the dose amount is 2E1.
High-concentration ion doping is performed at 5 / cm ² and a pressurization voltage of 70 keV. As a result, the source region 21d and the drain region 2 having a high ion concentration in the semiconductor layer of the n-type p-Si TFT 16
The low ion concentration LDD regions 21b and 21c are formed between 1e and the channel region 21a. The LDD regions 21b and 21c reduce the leak current and provide n-type p-S
Deterioration of the iTFT 16 is prevented.

Subsequently, after removing the photoresists 41 and 42 by an ashing method, the resist is applied again and then PEP is applied.
A photoresist 43 covering the entire n-type p-Si TFT 16 is formed by a patterning method, and boron ions (B ⁺ ) are implanted at a dose of 2E10 ¹⁵ / cm 2 as shown in FIG.
^2. High-concentration ion doping at a pressurization voltage of 70 keV. Thereafter, the photoresist 43 is removed by an ashing method. Then, as shown in FIG. 3C, the glass substrate 18 is heated at 500 ° C. for 1 hour to activate the doped ions.
Anneal for a time.

Next, as shown in FIG.
An interlayer insulating film 46 made of silicon oxide (SiO ₂ ) is formed to a thickness of 400 nm by Method D. Further, using a mask (not shown) formed by the PEP method, a contact hole 23 is formed in the interlayer insulating film 46 and the gate insulating film 27 by etching, and as shown in FIG. ), Aluminum (Al), and molybdenum (Mo) in order of 50 nm, 400 nm, and 50 n.
The metal film 47 is formed by stacking m. Thereafter, using a mask formed by the PEP method, source electrodes 48 and 50 and drain electrodes 51 and 52 are patterned to form desired n-type p-Si TFTs 16 and p-type p-type TFTs as shown in FIG.
-Si TFT 17 is obtained.

That is, the n-type p-Si thus obtained is
As shown in FIGS. 4 and 5, the TFT 16 and the p-type p-Si TFT 17 are formed in the underlying regions 2 on the side surfaces of the semiconductor layers 21 and 22.
3,24 and silicon oxide (SiO ₂₎ film thickness of the gate insulating film 27 made of film, the gate insulating film 27 made of the semiconductor layer 21, 22 top silicon oxide (SiO ₂₎ film 26
The semiconductor layers 21 and 22 are formed thicker than
TF due to side current can maintain good insulation on the side
The adverse effect on the T characteristic is reduced.

With this structure, n-type p-SiTF
T16 and the p-type p-Si TFT 17 are formed in the semiconductor layer 2
Undesirable current does not flow on the side surfaces 1 and 22 and stable characteristics can be obtained. When these are used for a liquid crystal display device,
Since the voltage holding characteristic of the pixel electrode can be improved, a good display can be obtained, and further, the leakage of the driving circuit element is prevented. As shown by a solid line in FIG. 6, the gate insulating film on the side of the semiconductor layer is thinner than the conventional example. Current (Ig) when a voltage (Vg) is applied.
Since the rise of d) can be obtained, uniform display can be obtained over the entire surface without causing spots, a decrease in yield due to display defects can be prevented, and a low-cost liquid crystal display device having good display quality can be achieved. .

The present invention is not limited to the above embodiment, but can be modified without departing from the spirit of the present invention. For example, the thickness of the gate insulating film covering the semiconductor layer is limited to the upper surface of the semiconductor layer. There is no limitation as long as the sides are thicker.

Further, the method of forming the underlying region on the side surface of the semiconductor layer is not limited. For example, as shown in FIG. 7, a first modified example shown in FIG. After forming the first oxide film on the semiconductor layer,
If the first oxide film is uniformly etched until the upper surface of the semiconductor layer is exposed, an oxide film remains on the side surface of the semiconductor layer after the etching is completed, and this may be used as a base region.

That is, as shown in FIG. 7A, after patterning semiconductor layers 57 and 58 made of p-Si on a glass substrate 55 via an undercoat layer 56, as shown in FIG. , a plasma CVD method by the first layer of silicon oxide (SiO ₂₎ film 60 is grown approximately 500 nm, followed by as shown in FIG. 7 (c) silicon dioxide (SiO ₂₎
The film 60 is uniformly etched to expose the upper surfaces of the semiconductor layers 57 and 58. At this time, silicon oxide (SiO ₂ ) films 60a to 60d remain on the side surfaces of the semiconductor layers 57 and 58.

Therefore, TEOS (tetra
If a second silicon oxide (SiO ₂ ) film 61 is grown to a thickness of about 100 nm by a plasma CVD method using ethyl orthosilicate as a raw material to form a gate insulating film 62 together with silicon oxide (SiO ₂ ) films 60a to 60d, As shown in FIG. 7D, the silicon oxide (SiO ₂ ) films 60a to 60d are further provided on the side surfaces of the semiconductor layers 57 and 58 with a second silicon oxide (Si) layer.
A gate insulating film 62 made of an O ₂ ) film 61 is applied, and the film thickness is larger than that of the gate insulating film 62 made of only a _second silicon oxide (SiO ₂ ) film 61 covering the upper surfaces of the semiconductor layers 57 and 58. Be killed.

Further, as shown in a second modification shown in FIG. 8, after forming the first oxide film on the semiconductor layer, the underlying region on the side surface of the semiconductor layer is kept until the upper surface of the semiconductor layer is exposed. May be formed by etching only the oxide film. With this configuration, the thickness of the oxide film as a base region remaining on the side surface of the semiconductor layer can be controlled by the thickness of the first oxide film.

That is, as shown in FIG. 8A, after semiconductor layers 67 and 68 made of p-Si are formed on a glass substrate 65 via an undercoat layer 66 by patterning, as shown in FIG. Then, a first silicon oxide (SiO ₂ ) film 70 is grown by a plasma CVD method, and then FIG.
As shown in the figure, the first silicon oxide (SiO ₂ ) film 7
Only the upper portions of the semiconductor layers 67 and 68 are etched to expose the upper surfaces of the semiconductor layers 57 and 58. At this time, the glass substrate 6
The silicon oxide (SiO ₂ ) films 70 a to 70 c remain on 5.

Therefore, TEOS (tetra
A second silicon oxide (SiO ₂ ) film 71 is grown by a plasma CVD method using ethyl orthosilicate as a raw material, and silicon oxide (S
When the gate insulating film 72 is formed together with the iO ₂ ) films 70a to 70c, the semiconductor layers 67 and 6 are formed as shown in FIG.
On the eight side surfaces, silicon oxide (SiO ₂ ) films 70 a to 70
Further, a gate insulating film 72 made of a second-layer silicon oxide (SiO ₂ ) film 71 is deposited on c, and semiconductor layers 67 and 68 are formed.
Second silicon oxide (SiO ₂ ) film 7 covering the upper surface
The film thickness is made larger than that of the gate insulating film 72 consisting of only one.

[0029]

As described above, according to the present invention, the gate insulating film on the side surface of the semiconductor layer is thicker than the gate insulating film on the upper surface of the semiconductor layer. Without adversely affecting the characteristics of
FT can obtain uniform and stable good characteristics. Therefore, if such a stable TFT is used in a liquid crystal display device, display defects can be eliminated, the yield can be improved, and the price of a liquid crystal display device having good display quality can be reduced.

[Brief description of the drawings]

FIG. 1 is a schematic sectional view showing an n-type p-SiTFT and a p-type p-SiTFT according to an embodiment of the present invention.

FIG. 2 shows a method for manufacturing an n-type p-SiTFT and a p-type p-SiTFT according to an embodiment of the present invention.
(B) at the time of forming the p-Si layer,
(C) when the semiconductor layer pattern is formed, (d) when the side surface of the semiconductor layer is made amorphous, (e) when the base region is formed, (f) when the gate insulating film is formed, and (g) when the gate insulating film is formed. (H) is a schematic explanatory view showing the time of doping the semiconductor layer with phosphorus ions (P ⁺ ) at a low concentration when the metal film is formed.

FIG. 3 shows a method for manufacturing an n-type p-SiTFT and a p-type p-SiTFT according to an embodiment of the present invention.
During phosphorus ions ^{(P +)} doped at high concentration to the type p-SiTFT, (b) when boron ions (B +) doped at a high concentration to that p-type p-SiTFT, (c) its semiconductor layer activity (D) when the interlayer insulating film is formed, (e) when the metal film is formed, and (f) when the source
FIG. 4 is a schematic explanatory view showing a state when a drain electrode is formed.

FIG. 4 is a schematic perspective view showing a state in which a gate electrode is formed on a semiconductor layer according to the embodiment of the present invention.

FIG. 5 is a schematic sectional view taken along line AA ′ in FIG. 4 of the embodiment of the present invention.

FIG. 6 is a graph showing a comparison of current rise characteristics according to the embodiment of the present invention.

FIGS. 7A and 7B show a method of forming a base region on a semiconductor side surface according to a first modified example of the present invention, wherein FIG. 7A shows a method for forming a semiconductor layer pattern, FIG.
(C) shows the etching of the first silicon oxide film,
(D) is a schematic explanatory view showing the time of forming the second silicon oxide film.

8A and 8B show a method of forming a base region on a semiconductor side surface according to a second modified example of the present invention, wherein FIG. 8A shows a method of forming a semiconductor layer pattern thereof, FIG.
(C) shows the etching of the first silicon oxide film,
(D) is a schematic explanatory view showing the time of forming the second silicon oxide film.

FIG. 9 is a schematic sectional view showing a p-Si TFT of a conventional device.

FIG. 10 is a schematic perspective view showing a state in which a gate electrode is formed on a semiconductor layer of a conventional device.

11 is a schematic cross-sectional view of the conventional device taken along line BB ′ in FIG.

[Explanation of symbols]

 Reference Signs List 16 n-type p-Si TFT 17 p-type p-Si TFT 18 glass substrate 20 undercoat layer 21 semiconductor layer 21 a channel regions 21 b and 21 c LDD region 21 d source region 21 e drain region 22 semiconductor layer 22 a ... channel region 22b ... source region 22c ... drain region 23, 24 ... base region 26 ... silicon oxide film 27 ... gate insulating film 28, 30 ... gate electrode 46 ... interlayer insulating film 47, 48 ... source electrode 50, 51 ... drain electrode

Continued on the front page F-term (reference) 2H092 JA24 JA25 JA34 JA37 KA04 KA05 KB25 MA08 MA17 MA23 MA29 NA29 PA01 5F110 AA06 BB02 BB04 CC02 DD02 DD14 DD24 EE06 EE44 FF02 FF30 GG02 GG13 GG22 GG25 GG32 H03 GG34 JG HL04 HL12 HM02 HM15 NN02 NN04 NN23 NN35 PP03 PP33 PP35 QQ02 QQ09 QQ11

Claims (5)

[Claims] An insulating substrate, a semiconductor layer formed in an island shape on the insulating substrate and having a channel region, a source region and a drain region sandwiching the channel region, and a film thickness to be deposited on a side surface of the semiconductor layer A gate insulating film covering the semiconductor layer so as to be thicker than a film deposited on the upper surface of the semiconductor layer; and a gate electrode formed in a region on the gate insulating film corresponding to the channel region. A thin film transistor device characterized by the above-mentioned. 2. The thin film transistor device according to claim 1, wherein the gate insulating film includes a base region adjacent to a side surface of the semiconductor layer and a surface region covering the semiconductor layer together with the base region. . 3. The thin film transistor device according to claim 2, wherein the base region is formed by exposing and oxidizing a side surface of the semiconductor layer. 4. An underlayer region formed by oxidizing the entire surface of the semiconductor layer to form an oxide film and then uniformly etching and removing the oxide film until the upper surface of the semiconductor layer is exposed. Item 3. A thin film transistor device according to item 2. 5. The semiconductor device according to claim 2, wherein the base region is formed by oxidizing the entire surface of the semiconductor layer to form an oxide film, and then etching away only the oxide film above the upper surface of the semiconductor layer. The thin-film transistor device according to claim 1.