JP2004336073A - Top gate type thin film transistor and its manufacturing method - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a manufacturing method for a top gate type thin film transistor which improves a reliability of a gate electrode, achieves a low resistance, reduces a leakage current, gives a high through-put out in a manufacturing process, and accomplishes a low cost. <P>SOLUTION: After a substrate insulating film 2 is accumulated on an insulating substrate 1, a polysilicon thin film 3 constituting a channel area and a source-drain area is formed. A gate insulating film 4 is formed on the polysilicon thin film 3, and the gate electrode constituted of a two-layer structure of an upper layer metal thin film 6 and a lower layer microcrystal silicon thin film 5 is formed. Resistivity of the lower layer microcrystal silicon thin film 5 is 1 Ωcm and lower, and the width of of the upper layer metal thin film 6 is smaller than the width of the lower layer microcrystal silicon thin film 5. The film thickness of the microcrystal silicon thin film 5 is 70 nm and thicker. The source-drain area 7 includes a LDD area 8. <P>COPYRIGHT: (C)2005,JPO&NCIPI

Description

  The present invention relates to a method of manufacturing a top gate thin film transistor, and more particularly, to a top gate thin film transistor formed on an insulating substrate such as a liquid crystal display and a contact image sensor, and a method of manufacturing the same.

  In a liquid crystal display (LCD), an amorphous silicon thin film transistor (TFT) -LCD has become mainstream. However, since it is difficult to realize an LCD with a large screen and high definition in an amorphous silicon TFT, a TFT using a polysilicon thin film having higher mobility as an active layer has attracted attention.

  On the other hand, with the increasing use of LCDs, there is a strong demand for thinning and miniaturization. In order to respond to such demands, attempts have been made to form a drive circuit on an active matrix substrate using TFTs as well. . However, forming the TFT for the driving circuit using an amorphous silicon thin film is not preferable in terms of operating speed and driving capability, and it is required to form the TFT using a polysilicon thin film. As a method of manufacturing a polysilicon thin film, a laser annealing method capable of forming a polysilicon thin film on an inexpensive low-temperature glass substrate is becoming mainstream from the viewpoints of lowering the process temperature, improving the throughput, and reducing the cost.

  However, a general polysilicon TFT has problems that the reliability of the gate wiring is low, it is difficult to reduce the resistance, and it is difficult to increase the definition of the LCD. In order to avoid this problem, for example, as disclosed in Patent Document 1 (Japanese Patent Laid-Open No. 5-235353), it is conceivable that the gate wiring is a two-layer wiring of a polysilicon thin film and a metal thin film.

  FIG. 6 is a cross-sectional view showing the structure of a polysilicon TFT in which the gate wiring has two layers. A base oxide film 2 is formed on a low-temperature glass substrate 1, a polysilicon thin film 3 is selectively formed on the base oxide film 2, and source / drain regions 7 are formed on both sides thereof. A gate insulating film 4 is formed so as to cover the polysilicon thin film 3 and the source / drain regions 7, and the source is formed through contact holes formed in the gate insulating film 4 and an interlayer insulating film 9 thereabove. The metal wiring 10 is formed so as to be in contact with the drain region 7. Further, a two-layer gate electrode composed of a lower polysilicon thin film 11 and an upper metal thin film 6 is formed on the gate insulating film 4 at a position matching the polysilicon thin film 3. These layers are covered with an interlayer insulating film 9.

  However, in the conventional thin film transistor in which the gate wiring is formed into two layers by using the polysilicon thin film 11, the gate forming process temperature is extremely high, such as 600 ° C. in the film forming step and 850 ° C. in the phosphorus diffusion step. In addition, there is a problem that the time for heating and cooling the substrate is long, and the throughput is reduced. The temperature of 600 ° C. or higher is a temperature higher than the softening point of an inexpensive low-temperature glass substrate. For this reason, an expensive quartz substrate needs to be used for the TFT substrate, which increases the manufacturing cost.

  Further, one of the serious problems of the polysilicon TFT is that the leakage current is large. To avoid this problem, for example, Patent Document 2 (Japanese Patent Application Laid-Open No. 58-204570), Patent Document 3 (Japanese Patent Application Laid-Open No. 1-125866), Patent Document 4 (Japanese Patent Application Laid-Open No. 5-152326), As disclosed in Document 5 (Japanese Patent Application Laid-Open No. 7-106582) and the like, a so-called LDD (Lightly Doped Drain) structure having a low-concentration impurity region at the drain end of a TFT, or, for example, Patent Document 6 (Japanese Patent Application Laid-Open No. As disclosed in Japanese Patent Application Laid-Open No. 6-37314) and Patent Document 7 (Japanese Patent Application Laid-Open No. 7-202210), it is conceivable to employ an overlap LDD structure.

  FIG. 7 shows these LDD-TFT structures. A low-concentration LDD region 8 is formed between the polysilicon thin film 3 and the source / drain region 7, and a gate insulating film 4 is formed on the LDD region 8 and the polysilicon thin film 3. A metal gate electrode 6 is formed in a selected region on the film 4.

  FIG. 8 shows another conventional LDD-TFT structure. In this LDD-TFT, a gate insulating film 4 is formed so as to cover the source / drain region 7, the LDD region 8, and the polysilicon thin film 3, and the LDD region 8 and the polysilicon thin film 3 on the gate insulating film 4 are formed. A gate electrode made of the lower polysilicon thin film 11 is formed in a region immediately above, and a gate electrode made of the upper polysilicon thin film 11 which is narrower than the lower layer is formed thereon.

JP-A-5-235353 JP-A-58-204570 JP-A-1-125866 JP-A-5-152326 JP-A-7-106582 JP-A-6-37314 JP-A-7-202210

  However, in the conventional LDD-TFT including the overlap LDD structure, there is a problem that the number of steps increases and the throughput decreases. For example, JP-A-58-204570 and JP-A-7-106582 require an impurity introduction step twice. For example, JP-A-6-37314 discloses that an impurity is etched through a photoresist step through a photoresist step. The above gate electrode forming process is required twice. For example, in Japanese Patent Application Laid-Open No. 7-202219, an anodic oxidation process for the upper gate electrode and a process for removing the anodized portion are required.

  In these LDD-TFTs, it is difficult to improve the reliability of the gate wiring and reduce the resistance as described above. For example, JP-A-58-204570, JP-A-1-125866 and JP-A-6-37314 disclose that a gate electrode is made of only a polysilicon thin film having a high resistance and formed by a high-temperature process. For example, in JP-A-5-152326 and JP-A-7-202210, only a low-reliability metal thin film is used for a gate electrode (FIG. 7).

  An activation step needs to be performed after the impurity implantation step including the LDD. The process temperature of this activation step is also one of the problems of the polysilicon TFT. For example, in JP-A-1-125866 and JP-A-5-235353, the activation process temperature is 1000 ° C., so that an inexpensive low-temperature glass substrate cannot be used. As a low-temperature activation method, for example, Japanese Patent Application Laid-Open No. 5-152326 uses a laser annealing method, but the laser annealing method is more expensive than a heat treatment method. In addition, the laser annealing method has a problem in that the film is peeled or cracked due to excessive thermal shock, thereby lowering the reliability of the gate electrode.

  The present invention has been made in view of such a problem, and it is possible to improve the reliability of a gate electrode and reduce the resistance, further reduce the leak current, and increase the throughput of a thin film transistor manufacturing process. It is an object of the present invention to provide a top gate type thin film transistor and a method for manufacturing the same, which can simultaneously satisfy the cost reduction.

  A top-gate thin film transistor according to the present invention comprises an insulating substrate, a polysilicon thin film formed on the insulating substrate and constituting a channel region and a source / drain region, and a gate insulating film formed on the polysilicon thin film. And a gate electrode formed on the gate insulating film and having a two-layer structure of an upper metal thin film and a lower microcrystalline silicon thin film, wherein the lower microcrystalline silicon thin film has a resistivity of 1 Ωcm or less, and The width of the thin film is smaller than the width of the lower microcrystalline silicon film.

  In this top gate type thin film transistor, it is preferable that the source / drain regions have an LDD structure including a low concentration region and a high concentration region. Further, a region of the microcrystalline silicon thin film projecting outside the metal thin film can be formed so as to overlap with the low concentration region. Further, the microcrystalline silicon thin film preferably has a thickness of 70 nm or more.

  The method of manufacturing a top-gate thin film transistor according to the present invention includes the steps of: forming a polysilicon thin film on an insulating substrate; forming a gate insulating film on the polysilicon thin film; Forming a thin film, selectively forming a photoresist on the conductive thin film, and forming the gate electrode by etching the conductive thin film using the photoresist as a mask so that the width is smaller than the mask. Performing a step of introducing high-concentration impurities into the polysilicon thin film via the gate insulating film while holding the mask; removing the mask; and removing the polysilicon thin film after removing the mask. And introducing a low-concentration impurity through the gate insulating film.

  In this method of manufacturing a top-gate thin film transistor, the step of forming the conductive thin film includes forming a microcrystalline silicon thin film by a plasma CVD method and forming a metal thin film by sputtering on the microcrystalline silicon thin film. And

  Another method of manufacturing a top-gate thin film transistor according to the present invention includes a step of forming a polysilicon thin film on an insulating substrate; a step of forming a gate insulating film on the polysilicon thin film; Forming a microcrystalline silicon thin film by a plasma CVD method, forming a metal thin film on the microcrystalline silicon thin film by a sputtering method, selectively forming a photoresist on the metal thin film, Using the resist as a mask to continuously etch the metal thin film and the microcrystal thin film under the same mask to form a two-layered gate electrode; and form an impurity in the polysilicon thin film via the gate insulating film. And a step of introducing

  In this method of manufacturing a top gate thin film transistor, in the step of forming the two-layer gate electrode, the metal thin film can be etched so as to have a smaller width than the microcrystalline silicon thin film. In the step of forming the two-layer gate electrode, the microcrystalline silicon thin film may be etched after the metal thin film is etched so as to have a smaller width than the mask. Further, a step of removing the mask, and introducing an impurity into the polysilicon thin film after the mask is removed, wherein a high-concentration impurity region in an impurity introduction region only through the gate insulating film; The thin film and the low-concentration impurity region in the impurity introduction region via the gate insulating film can be formed at the same time.

  In the present invention, by applying the microcrystalline silicon thin film to the lower layer of the two-layered gate electrode, a low-cost gate wiring having high reliability and low cost is formed. Microcrystalline silicon thin film is defined as disclosed in Journal of Non-Crystline Solids, Vol. 59 & 60, p. 767 (J. Non-Cryst. Solids, Vol. 59 & 60, p. Is a silicon thin film formed by a plasma CVD method, in which extremely fine crystal grains having a particle size of 10 nm or less and amorphous are mixed. Since the film forming temperature of the microcrystalline silicon thin film is about 300 ° C., the film forming temperature of the low pressure CVD method and the normal pressure CVD method used for forming the conventional polysilicon thin film is about 600 ° C. As compared with the above, the throughput and the manufacturing cost of the film forming process are extremely excellent. In addition, since microcrystalline silicon thin films have fine crystal grains, the resistance can be reduced as much as the polysilicon thin film. Therefore, by using a microcrystalline silicon thin film as a lower layer and a metal thin film as an upper layer as a gate electrode of a TFT, a low-resistance gate wiring having high reliability and low cost can be formed.

  Further, in the present invention, when forming the two-layer gate electrode, only the upper-layer metal gate electrode is side-etched, so that a single step of introducing impurities through the gate insulating film enables the overlap LDD structure to be activated at a low temperature. Is formed.

  At the portion where the lower gate electrode is exposed, impurities are introduced into the polysilicon thin film via the lower gate electrode and the gate insulating film. On the other hand, in a portion where the gate electrode does not exist, impurities are introduced into the polysilicon thin film only through the gate insulating film. Therefore, the region directly below the portion where the lower gate electrode of the polysilicon thin film is exposed is an LDD region where the amount of introduced impurities is smaller than the region immediately below the portion where the gate electrode does not exist. Note that no impurity is introduced into a region immediately below the portion where the upper gate insulating film of the polysilicon thin film is present due to the shielding effect of the upper gate electrode.

  The activation temperature after impurity introduction depends on the structural change of the polysilicon thin film accompanying the impurity introduction. When the impurity is introduced, the polysilicon thin film changes to an amorphous phase because the atomic structure is disturbed. Activation after impurity introduction refers to recrystallizing an amorphous phase containing the impurity. Here, when the polysilicon thin film becomes amorphous in all regions in the thickness direction from the interface of the insulating film to the interface of the substrate, a heat treatment temperature of 600 ° C. or more, preferably about 1000 ° C. is required for crystallization. In order for the amorphous phase to crystallize, both processes of nucleation and grain growth must be performed, but nucleation requires a latent time depending on the heat treatment temperature. In the case of silicon, a temperature of 1000 ° C. is required to cause nucleation in a time range of about several hours suitable for a manufacturing process. When the heat treatment temperature is lowered to 600 ° C., the time required for nucleation increases to 20 hours, and the throughput increases remarkably.

  However, if only the surface of the polysilicon film becomes amorphous after the impurity is introduced and the polysilicon remains near the substrate interface, the activation can be performed by a heat treatment at a low temperature of about 500 ° C. for about several hours. This is because the crystallization progresses only in the grain growth process because the crystal nucleus already exists. In the present invention, by introducing an impurity through an insulating film, the impurity concentration profile in the thickness direction of the polysilicon film can be controlled, and the polysilicon can be easily controlled so as to remain after the impurity is introduced. Therefore, low-temperature activation can be performed to such an extent that an inexpensive low-temperature glass substrate can be used, and the throughput is also increased.

  As described above, by performing side-etching only on the upper metal gate electrode during the formation of the two-layer gate electrode according to the present invention, low-temperature activation can be achieved in one impurity introduction step through the gate insulating film. An overlapped LDD-TFT having a gate electrode with low resistance and high reliability is formed.

  As described above, according to the method of manufacturing a top gate type thin film transistor according to the present invention, by using a two-layer gate electrode composed of a microcrystalline silicon thin film and a metal thin film as a gate electrode, low resistance and high reliability can be achieved. A TFT having a flexible gate electrode can be manufactured at high throughput and at low cost. Further, by side-etching only the upper gate electrode, an LDD-TFT having a gate electrode with low resistance and high reliability can be manufactured at low cost.

  Next, embodiments of the present invention will be specifically described with reference to the accompanying drawings. FIG. 1 is a sectional view showing a top gate type thin film transistor manufactured by the method according to the first embodiment of the present invention. This transistor can be manufactured as follows. First, a base insulating film 2 is deposited on an insulating substrate 1. Next, a silicon thin film is deposited on the entire surface, a polysilicon thin film 3 is formed by a laser annealing method using CW laser light or pulsed laser light, and after patterning into an island shape, a gate insulating film 4 is deposited thereon. I do. Next, a microcrystalline silicon thin film 5 is deposited as a lower gate electrode by plasma CVD at a temperature of 350 ° C. or less at a thickness of 70 nm or more, and a metal thin film 6 is successively deposited as an upper gate electrode. By patterning, a two-layer gate electrode is formed.

  The source / drain regions 7 are formed by selectively introducing impurities into the polysilicon thin film 3 via the gate insulating film 4 by an ion doping method or the like, and the impurities are activated by heat treatment at, for example, 500 ° C. Subsequently, an interlayer insulating film 9 is deposited, and a contact hole exposing the source / drain region 7 is opened. Finally, a metal thin film of aluminum or the like is formed, and this is patterned to form a metal wiring 10 which is in contact with the source / drain region 7, thereby completing the thin film transistor forming step.

  In this manner, the channel region made of the polysilicon thin film 3, the source / drain regions 7 on both sides thereof, and the two-layered gate electrode laminated between these regions via the gate insulating film 4 are formed. Having a top gate type thin film transistor. The two-layer gate electrode is composed of a lower microcrystalline silicon thin film 5 and an upper metal thin film 6. Since the microcrystalline silicon thin film 5 has a low film forming temperature, the throughput of the film forming process is better and the manufacturing cost is reduced as compared with the conventional polysilicon thin film. In addition, since the microcrystalline silicon thin film 5 has fine crystal grains, it is possible to reduce the resistance as much as the polysilicon thin film. Therefore, a low-resistance gate wiring with high reliability and low cost can be formed.

  Next, a method according to a second embodiment of the present invention will be described with reference to FIG. In this embodiment, the manufacturing process is the same as that of the first embodiment up to the step of depositing the microcrystalline silicon thin film 5 and the metal thin film 6. In the present embodiment, when a two-layer gate electrode is formed by patterning, the gate electrode is side-etched by performing over-etching on both layers. Then, while holding the resist on the gate electrode, the impurity is selectively introduced into the polysilicon thin film 3 through the gate insulating film 4 by an ion doping method or the like to form the source / drain region 7.

  Next, after removing the resist, a low concentration impurity is introduced to form an LDD region (low concentration region) 8. Thereafter, the steps after the activation of the impurities are the same as those in the first embodiment, and the thin film transistor is completed by these steps.

  In the present embodiment, in addition to the same effects as in the first embodiment, the source / drain region has the LDD region (low-concentration region) 8, whereby a thin film transistor having an LDD structure can be obtained.

  FIG. 3 is a cross-sectional view illustrating a top-gate thin film transistor manufactured by a method according to a third embodiment of the present invention. The steps up to the deposition of the microcrystalline silicon thin film 5 and the metal thin film 6 are the same as in the first embodiment. In this embodiment, when the two-layer gate electrode is formed by patterning, only the metal thin film 6 is over-etched, so that the upper metal thin film 6 and the lower microcrystalline silicon thin film 5 have different widths. Is formed.

  After the resist on the gate electrode is removed, the impurity is selectively introduced into the polysilicon thin film 3 by penetrating the gate insulating film 4 by an ion doping method or the like, and passes through the microcrystalline silicon thin film 5 of the lower gate electrode. The low density LDD region 8 is formed by forming a low concentration LDD region 8, and the high concentration source / drain region 7 is formed by passing through a region outside the lower microcrystalline silicon thin film 5. Thus, in the present embodiment, the source / drain region 7 and the LDD region 8 can be formed simultaneously. The steps after the activation of the impurities are the same as in the first embodiment, thereby completing the step of forming the thin film transistor. In the present embodiment, in addition to the same effects as those of the first and second embodiments, low-temperature activation is possible by one impurity introduction step via the gate insulating film 4 and the lower microcrystalline silicon thin film 5. Overlap LDD structures can be formed.

Next, a result of actually manufacturing a top gate type thin film transistor by the method of the present embodiment and evaluating its characteristics will be described. First, the result of manufacturing the thin film transistor having the structure of the first embodiment will be described. As the low-temperature glass substrate, an OA-2 substrate manufactured by NEC Corporation was used. A silicon dioxide thin film as a base insulating film was deposited to a thickness of 100 nm by plasma CVD using SiH ₄ and N ₂ O as source gases.

Next, an amorphous silicon thin film was deposited to a thickness of 75 nm by low pressure CVD using Si ₂ H ₆ as a source gas. The deposition was performed for 70 minutes at a flow rate of Si ₂ H ₆ of 150 sccm, a pressure of 8 Pa, and a substrate temperature of 450 ° C. A polysilicon thin film was formed on the amorphous silicon thin film by using a laser annealing method of irradiating XeCl excimer laser light having a wavelength of 308 nm. The laser irradiation was performed under the conditions of an energy density of 420 mJ / cm ² and a beam overlap ratio of 90%. The polysilicon thin film was formed into islands by a dry etching method after patterning by a normal photoresist process.

Next, on the islanded polysilicon thin film, a silicon dioxide thin film serving as a gate insulating film was deposited to a thickness of 40 nm using SiH ₄ and O ₂ as source gases by a low pressure CVD method. The deposition was performed for 20 minutes under the conditions of a SiH ₄ flow rate of 35 sccm, an O ₂ flow rate of 140 sccm, a pressure of 30 Pa, and a substrate temperature of 400 ° C.

Next, a microcrystalline silicon thin film serving as a lower gate electrode was deposited to a thickness of 70 nm using SiH ₄ , PH ₃ (0.5% H ₂ diluted) and H ₂ as source gases by a plasma CVD method. The deposition conditions were as follows: SiH ₄ flow rate 20 sccm, PH ₃ flow rate 40 sccm, H ₂ flow rate 1000 sccm, pressure 50 Pa, discharge power density 0.13 W / cm ² , and substrate temperature 350 ° C. for 19 minutes.

  As shown in FIG. 4, the resistivity of the microcrystalline silicon thin film greatly depends on the film thickness. This is because the growth of the crystal component in the microcrystalline silicon proceeds as the film thickness increases. That is, the crystal component of the lower microcrystalline silicon thin film grows from the lower part to the upper part. Then, as the growth of the crystal component proceeds, the resistivity decreases. When the application to the lower gate electrode is considered, the resistivity of the film is desirably 1 Ωcm or less. Therefore, the thickness of the microcrystalline silicon thin film needs to be 70 nm or more. In addition, a higher substrate temperature promotes the growth of crystal components. Therefore, it is desired that the substrate temperature be high. However, an excessive temperature causes a decrease in throughput and an increase in apparatus cost and process cost. Therefore, the substrate temperature is suitably up to about 350 ° C. which can be realized by a normal plasma CVD apparatus.

Next, a 100 nm thick tungsten silicide thin film serving as an upper gate electrode was deposited by a sputtering method. Ar was used as the sputtering gas, and the deposition was performed under the conditions of an Ar flow rate of 100 sccm, a pressure of 0.3 Pa, 2 W / cm ² , and a substrate temperature of 150 ° C. for 0.3 minutes. At this time, the resistivity of the film was a value of 5 × 10 ⁻⁵ Ωcm.

  The microcrystalline silicon thin film and the tungsten silicide thin film were continuously deposited in the same vacuum apparatus using different chambers in order to improve throughput and suppress the formation of a natural oxide film on the surface of the microcrystalline silicon thin film. When each thin film was formed by a different vacuum device, a natural oxide film was generated on the surface of the microcrystalline silicon thin film, the resistivity of the entire two-layer gate electrode was increased, and as a result, TFT characteristics were reduced by about 4%.

Next, the gate electrode was patterned by a normal photoresist method. Next, the tungsten silicide thin film was dry-etched from CF ₄ and O ₂ by dry etching. The etching was performed for 1.5 minutes under the conditions of a CF ₄ flow rate of 40 sccm, an O ₂ flow rate of 10 sccm, a pressure of 6 Pa, and a discharge power density of 0.3 W / cm ² . After the etching of the tungsten silicide thin film was completed, the etching chamber was once evacuated to 10 ⁻⁴ Pa, and then Cl ₂ , SF ₆ and H ₂ were introduced to dry-etch the microcrystalline silicon thin film. Etching was performed for 6 minutes at a Cl ₂ flow rate of 40 sccm, SF ₆ flow rate of 10 sccm, H ₂ flow rate of 10 sccm, pressure of 10 Pa, and discharge power density of 0.35 W / cm ² .

As an etching gas for the tungsten silicide thin film, CF ₄ and O ₂ capable of obtaining a high etching rate were used. The dry etching gas for the microcrystalline silicon thin film must have a high selectivity between the microcrystalline silicon thin film and the silicon dioxide thin film. However, by using Cl ₂ , SF ₆ and H ₂ , residual tungsten is removed. The silicon removal ability was excellent, and a high selectivity of 20 or more was obtained between the microcrystalline silicon thin film and the silicon dioxide thin film. Dry etching a tungsten silicide thin film and a microcrystalline silicon thin film in the same vacuum apparatus is advantageous in terms of throughput.

After the resist on the gate electrode was removed, self-aligned impurities were introduced by PH ₃ (5% H ₂ dilution) using the gate electrode as a mask by ion doping. The doping conditions were an acceleration voltage of 50 keV, a dose of 3 × 10 ¹⁵ cm ⁻² , and a pressure of 0.02 Pa.

FIG. 5 shows a P concentration profile in silicon obtained as a result of doping. Experiments have revealed that the P concentration that causes the silicon thin film to become amorphous is 3 × 10 ¹⁹ cm ⁻³ or more. Therefore, when a 75-nm polysilicon thin film is doped via a 40-nm insulating film, the polysilicon remains in about half of the film thickness, and the impurity activation temperature can be kept low. In fact, activation was achieved under the conditions of a heat treatment temperature of 500 ° C. and a heat treatment time of 2 hours. At this time, the resistivity of the impurity introduction portion was 2 × 10 ⁻³ Ωcm. In addition, although 2 ppm of strain was observed on the substrate after the activation step, there was no problem in the subsequent TFT manufacturing steps.

  On the other hand, when the polysilicon thin film is directly doped without using an insulating film, the polysilicon thin film becomes amorphous over almost the entire thickness. At this time, at a heat treatment temperature of 500 ° C., activation was not achieved even with a heat treatment time of 50 hours, and activation was first achieved at a heat treatment temperature of 600 ° C. and a heat treatment time of 20 hours. In addition, the substrate after the activation process was distorted by as much as 40 ppm, which hindered the subsequent TFT manufacturing process, particularly in aligning the reticle in the photoresist process and transporting the substrate in the film forming process. As a result, throughput and yield decreased.

Next, a silicon nitride film was deposited to a thickness of 300 nm from SiH ₄ , NH ₃ and N ₂ by a plasma CVD method. After opening a contact hole by dry etching, an aluminum film was deposited to a thickness of 400 nm by sputtering and patterned to form a metal wiring. Finally, hydrogen annealing was performed to complete the TFT.

  The TFT completed in this manner has a lower processing temperature than conventional TFTs, is manufactured with high throughput and low cost, and has high reliability of the gate electrode.

Next, the result of manufacturing a thin film transistor by the method of the second embodiment of the present invention will be described. As a low-temperature glass substrate, a Corning 1737 substrate was used. Next, a silicon dioxide thin film as a base insulating film was deposited to a thickness of 100 nm using SiH ₄ and N ₂ O by a plasma CVD method.

Next, an amorphous silicon thin film was deposited to a thickness of 75 nm using SiH ₄ and H ₂ by a plasma CVD method. Deposition was performed for 8 minutes under the conditions of SiH ₄ flow rate of 150 sccm, H ₂ flow rate of 400 sccm, pressure of 100 Pa, discharge power of 0.1 W / cm ² , and substrate temperature of 320 ° C. The amorphous silicon thin film was subjected to dehydrogenation annealing at a heat treatment temperature of 400 ° C. for 2 hours, and then a polysilicon thin film was formed by a laser annealing method of irradiating a KrF excimer laser beam having a wavelength of 248 nm. The laser irradiation was performed under the conditions of an energy density of 380 mJ / cm ² and a beam overlap ratio of 90%. The polysilicon thin film was formed into islands by a dry etching method after patterning by a normal photoresist process.

Next, on the islanded polysilicon film, a silicon dioxide thin film serving as a gate insulating film was deposited to a thickness of 40 nm from SiH ₄ and O ₂ by ECR-plasma CVD. The deposition was performed for 4 minutes under the conditions of a SiH ₄ flow rate of 10 sccm, an O ₂ flow rate of 200 sccm, a pressure of 100 Pa, a discharge power density of 0.23 W / cm ² , and a substrate temperature of 270 ° C.

Next, a microcrystalline silicon thin film serving as a lower gate electrode was deposited to a thickness of 70 nm by plasma CVD using SiH ₄ , PH ₃ (0.5% H ₂ diluted) and H ₂ as source gases. The deposition conditions were SiH ₄ flow rate 10 sccm, PH ₃ flow rate 40 sccm, H ₂ flow rate 1000 sccm, pressure 100 Pa, discharge power density 0.5 W / cm ² , and substrate temperature 300 ° C. for 23 minutes. Subsequently, a tungsten silicide thin film serving as an upper gate electrode was deposited to a thickness of 100 nm by sputtering in the same manner as in the first embodiment.

  The gate electrode is formed by patterning and dry etching in the same manner as in the first embodiment. At this time, the etching time is set longer than usual, and a side-etched region of 1 μm is formed. The etching time was 2 minutes and 9 minutes for the upper layer and the lower layer, respectively.

Next, while the resist was held on the gate electrode, impurities were introduced by ion doping as in the first embodiment. Next, the resist on the gate electrode is removed, and low-concentration impurities are introduced into the side-etch region by ion doping using PH ₃ (H ₂ diluted 0.1%) and H ₂ as source gases to form an LDD region. did. The doping conditions were an acceleration voltage of 40 keV, a dose of 7 × 10 ¹² cm ⁻² , and a pressure of 0.02 Pa. By having an LDD region, the leakage current of the resulting TFT was reduced to about 1/50.

  After the activation step, the LDD-TFT was completed in the same steps as in the first embodiment. The LDD-TFT thus completed has a lower processing temperature than the conventional LDD-TFT, is manufactured with high throughput and low cost, and has high reliability of the gate electrode.

  Next, a result of manufacturing a thin film transistor by the method of the third embodiment of the present invention will be described. As in the first embodiment, a polysilicon thin film was formed on a glass substrate to form islands, and a gate insulating film, a microcrystalline silicon thin film, and a tungsten silicide thin film were deposited.

  A gate electrode is formed by patterning and dry etching in the same manner as in the first embodiment, and the etching time at this time is 2 minutes for the upper layer and 6 minutes for the lower layer. As a result, the width of the upper layer became smaller by 1 μm on the left and right sides than the lower layer.

Next, as in the first embodiment, impurities were introduced by an ion doping method. At the portion where the gate electrode does not exist, impurities were introduced into the polysilicon thin film only through the gate insulating film, and the dose was 3 × 10 ¹⁵ cm ⁻² as in the first embodiment. On the other hand, the dose was 2 × 10 ¹² cm ⁻² in the polysilicon region immediately below the portion where the upper gate electrode was side-etched and the lower gate electrode was exposed.

  As shown in FIG. 5, the P concentration decreased by about three digits due to the influence of the lower gate electrode having a thickness of 70 nm. By having an LDD region, the leakage current of the resulting TFT was reduced to about 1/20.

  The steps after the activation step are the same as those in the first embodiment, whereby the LDD-TFT is completed. The LDD-TFT thus completed has a lower process temperature than the conventional LDD-TFT, has a smaller number of times of impurity introduction, is manufactured at a high throughput and at a low cost, and has a high reliability of the gate electrode.

  Note that the present invention is not limited to the above embodiment. For example, in the above embodiment, amorphous silicon is used as an initial material for laser annealing, but the same effect can be obtained by using another silicon film such as polysilicon or microcrystal silicon as an initial material. Was done. The same effect was obtained by using another insulating film such as a silicon nitride film and a silicon oxynitride film instead of the silicon oxide film as the gate insulating film. Similar effects were obtained by using another metal such as aluminum, chromium, molybdenum, molybdenum silicide, or a tungsten-molybdenum alloy instead of tungsten silicide as the upper gate electrode.

FIG. 3 is a cross-sectional view illustrating a structure of a thin film transistor manufactured by the method according to the first embodiment of the present invention. FIG. 3 is a cross-sectional view illustrating a structure of a thin film transistor manufactured by a method according to a second embodiment of the present invention. FIG. 9 is a cross-sectional view illustrating a structure of a thin film transistor manufactured by a method according to a third embodiment of the present invention. FIG. 4 is a graph showing the relationship between the thickness of a microcrystalline silicon thin film and the resistivity. FIG. 4 is a graph showing a P concentration profile in silicon. FIG. 9 is a cross-sectional view illustrating a structure of a conventional thin film transistor. FIG. 4 is a cross-sectional view illustrating a structure of a conventional LDD thin film transistor. It is sectional drawing which shows the other conventional LDD-TFT structure.

Explanation of reference numerals

1: low-temperature glass substrate 2: base oxide film 3: polysilicon thin film 4: gate insulating film 5: microcrystalline silicon gate electrode 6: metal gate electrode 7: source / drain region 8: LDD region 9: interlayer insulating film 10: metal Wiring 11: polysilicon gate electrode

Claims (10)

An insulating substrate, a polysilicon thin film formed on the insulating substrate and constituting a channel region and a source / drain region, a gate insulating film formed on the polysilicon thin film, and formed on the gate insulating film. A gate electrode having a two-layer structure of an upper metal thin film and a lower microcrystal silicon thin film, wherein the lower microcrystal silicon thin film has a resistivity of 1 Ωcm or less, and the upper metal thin film has a width of the lower microcrystal silicon film. A top gate type thin film transistor characterized by having a width smaller than the width of The top gate type thin film transistor according to claim 1, wherein the source / drain region has an LDD structure including a low concentration region and a high concentration region. 3. The top gate type thin film transistor according to claim 2, wherein a region of the microcrystalline silicon thin film projecting outside the metal thin film is formed so as to overlap with the low concentration region. 4. The top gate type thin film transistor according to claim 1, wherein the thickness of the microcrystalline silicon thin film is 70 nm or more. Forming a polysilicon thin film on an insulating substrate; forming a gate insulating film on the polysilicon thin film; forming a conductive thin film on the gate insulating film; Selectively forming a resist, forming the gate electrode by etching the conductive thin film using the photoresist as a mask so as to have a smaller width than the mask, and forming the gate insulating layer while holding the mask. Introducing a high-concentration impurity into the polysilicon thin film through a film; removing the mask; and removing the mask with a low-concentration impurity through the gate insulating film after removing the mask. Introducing a top gate thin film transistor. The step of forming the conductive thin film includes a step of forming a microcrystalline silicon thin film by a plasma CVD method, and a step of forming a metal thin film by a sputtering method on the microcrystalline silicon thin film. Item 6. A method for manufacturing a top gate thin film transistor according to Item 5. Forming a polysilicon thin film on an insulating substrate, forming a gate insulating film on the polysilicon thin film, forming a microcrystalline silicon thin film on the gate insulating film by a plasma CVD method, A step of forming a metal thin film on the microcrystalline silicon thin film by a sputtering method, a step of selectively forming a photoresist on the metal thin film, and using the photoresist as a mask to form the same metal thin film and the microcrystal thin film in the same manner. Top gate, comprising: a step of forming a two-layered gate electrode by continuous etching under a mask; and a step of introducing an impurity into the polysilicon thin film via the gate insulating film. Method of manufacturing a thin film transistor. 8. The method according to claim 7, wherein in the step of forming the two-layer gate electrode, the metal thin film is etched so as to have a smaller width than the microcrystalline silicon thin film. 9. The top gate type according to claim 8, wherein in the step of forming the two-layer gate electrode, the microcrystalline silicon thin film is etched after the metal thin film is etched so as to have a smaller width than the mask. A method for manufacturing a thin film transistor. Removing the mask, and introducing an impurity into the polysilicon thin film after removing the mask; a high-concentration impurity region in an impurity introduction region only through the gate insulating film; and the microcrystalline silicon thin film and 10. The method of manufacturing a top-gate thin film transistor according to claim 8, wherein a low-concentration impurity region in the impurity introduction region via the gate insulating film is formed at the same time.

Images