JP2013138232A - Thin film transistor and manufacturing method thereof and liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a TFT which has a leakage current reducing structure and can be manufactured by a simple process.SOLUTION: A base insulation film 11 is deposited on an insulation substrate. Next, a silicon thin film is deposited, and a polysilicon thin film 12 is formed by a laser annealing process. The polysilicon thin film 12 is turned into an island, and a gate insulation film 13 is deposited. Next, a microcrystal silicon thin film 14 is deposited as a lower layer gate electrode, and then a metal film 15 is deposited in succession as an upper layer gate electrode. When these are put into patterns to form a multilayer gate electrode, the lower layer gate electrode is formed in greater size than the upper layer gate electrode. After that, impurities is selectively introduced into the polysilicon thin film 12 via the gate insulation film 13 by an ion implantation process, etc., to form an LDD region 19 and a source-drain region 18 at the same time. Then, a portion where the lower gate electrode is exposed is etched using the upper gate electrode as a mask to obtain an intended TFT 10.

Description

  The present invention relates to a thin film transistor and a manufacturing method thereof, and more particularly to a thin film transistor formed on an insulating substrate such as a liquid crystal display and a contact image sensor, and a manufacturing method thereof.

  In recent years, in a liquid crystal display device (hereinafter referred to as “LCD”), an amorphous silicon thin film transistor (hereinafter referred to as “TFT”)-LCD has become mainstream. However, due to diversification of applications in LCDs, there are strong demands for thinning and miniaturization, and in order to meet these demands, it has become common to form a drive circuit with TFTs on an active matrix substrate. Forming the TFT for the drive circuit using an amorphous silicon thin film is not preferable in terms of operation speed and drive capability, and forming the TFT for the drive circuit using a polysilicon film having a higher mobility as an active layer. Is required.

  However, one of the serious problems with polysilicon TFTs is a large leakage current. In order to avoid this problem, an LDD (Lightly Doped Drain) structure having a low-concentration impurity region at the drain end of the TFT as disclosed in, for example, Patent Documents 1 to 4, or disclosed in, for example, Patent Document 5 It is conceivable to employ such an overlapping LDD structure.

  FIG. 7 shows a method of manufacturing an LDD-TFT described in Patent Document 1. First, as shown in FIG. 7 [1], a base insulating film 71 is formed on an insulating substrate (not shown), a polysilicon thin film 72 is formed thereon, and this is turned into an island by etching. A gate insulating film 73 is formed thereon, a gate electrode 74 is formed thereon, a photoresist film 75 is formed thereon, and this is patterned.

  Subsequently, as shown in FIG. 7 [2], the gate electrode 74 is etched using the photoresist film 75 as a mask, and the photoresist film 75 is removed. Subsequently, as shown in FIG. 7 [3], a photoresist film 76 is formed so as to cover the gate electrode 74, and is patterned. Subsequently, as shown in FIG. 7 [4], a source / drain region 77 is formed by introducing an impurity into the polysilicon thin film 72 through the gate insulating film 73 using the photoresist film 76 as a mask.

  Finally, as shown in FIG. 7 [5], the photoresist film 76 is removed, and impurities are further introduced into the polysilicon thin film 72 through the gate insulating film 73 using the gate electrode 74 as a mask, thereby forming an LDD region 78. Form. Thereby, the basic structure of the TFT 70 is completed.

  However, the conventional LDD-TFT has a problem in that the number of steps and the number of necessary masks increase and throughput decreases. For example, in Patent Documents 1 and 4, the impurity introduction process is required twice, and in Patent Document 5, for example, an anodizing process for the upper gate electrode and a removing process for the anodized part are required.

  As a conventional technique for solving this problem, there is an overlap structure LDD-TFT. In Patent Document 6, as a process-saving LDD-TFT using an overlap structure TFT, impurities are introduced through an overlapped gate electrode, whereby a source / drain region and an LDD region are formed by a single impurity introduction step. Realization of process.

  FIG. 8 is a cross-sectional view of an overlap LDD structure TFT realizing a process saving in Patent Document 6. In the TFT 80 shown in FIG. 8, the difference in size between the microcrystalline silicon thin film 85 and the metal film 86 is obtained by side-etching the metal film 86 in the etching process for forming the gate electrode.

JP 58-204570 A (2nd page) Japanese Patent Laid-Open No. 1-125866 (Page 1 Prior Art and its Problems) JP-A-5-152326 (page 2, paragraph 0003) JP-A-7-106582 (page 4, paragraph 0020) JP-A-7-202210 (page 3, example 2, page 4, effect of the invention) Japanese Patent Laid-Open No. 11-307777 (FIG. 4 on page 6)

  However, in the overlap structure LDD-TFT, there is a problem that leakage current is generated from the overlap portion, so that reduction of the leakage current, which is the original purpose, cannot be sufficiently achieved. In Patent Document 6, although an LDD-TFT including an overlap structure by a simple manufacturing method is described, an increase in leakage current from an overlap portion due to application of a reverse voltage is so high that it cannot be ignored. When a leak current is generated in the TFT used in the LCD, the operation of the liquid crystal cannot be sufficiently controlled. Therefore, reducing the leakage current of the polysilicon TFT is an unavoidable problem in producing an LCD.

  SUMMARY OF THE INVENTION An object of the present invention is to provide a highly reliable top-gate TFT capable of realizing high throughput and low cost of the TFT manufacturing process and simultaneously satisfying a reduction in leakage current, and a manufacturing method thereof. There is to do.

  The TFT according to the present invention includes an amorphous semiconductor thin film formed on an insulating substrate, a gate insulating film formed on the amorphous semiconductor thin film, a lower gate electrode and an upper layer formed on the gate insulating film. A thin film transistor comprising: a gate electrode comprising a gate electrode; and an LDD structure comprising a high concentration impurity introduction region and a low concentration impurity introduction region formed in the amorphous semiconductor thin film, wherein the low concentration impurity introduction region and the high concentration The difference in impurity concentration from the impurity introduction region corresponds to the concentration of impurities blocked by the lower gate electrode, and the gate electrode does not exist on the surface of the gate insulating film on the low concentration impurity introduction region. And there is a shape reflecting the residue.

  In other words, the TFT according to the present invention includes an amorphous semiconductor thin film formed on an insulating substrate, a gate insulating film formed on the amorphous semiconductor thin film, a lower gate electrode formed on the gate insulating film, and A gate electrode composed of an upper gate electrode and an LDD structure composed of a high concentration impurity introduction region and a low concentration impurity introduction region formed in the amorphous semiconductor thin film are provided. The difference in impurity concentration between the low-concentration impurity introduction region and the high-concentration impurity introduction region corresponds to the concentration of the impurity blocked by the lower gate electrode. Further, no gate electrode exists on the low concentration impurity introduction region.

  The difference in impurity concentration between the low-concentration impurity introduction region and the high-concentration impurity introduction region corresponds to the impurity concentration blocked by the lower gate electrode. This means that the gate insulating film and the lower gate electrode are compared with the amorphous semiconductor thin film. It means that impurities are introduced through That is, in the amorphous semiconductor thin film, a region where only the gate insulating film is formed is a high concentration impurity introduction region, and a region where both the gate insulating film and the lower gate electrode are formed is a low concentration impurity introduction region. It becomes. The absence of the gate electrode on the low-concentration impurity introduction region means that the exposed portion of the lower gate electrode (the lower gate electrode on the low-concentration impurity introduction region) is removed by etching using the upper gate electrode as a mask. To do. If the gate electrode does not exist on the low concentration impurity introduction region, the electric field from the gate electrode to the low concentration impurity introduction region is weaker than that in the case where the gate electrode is on the low concentration impurity introduction region, so that the leakage current is reduced. .

  The amorphous semiconductor thin film is, for example, a polysilicon thin film. Polysilicon thin films are suitable for forming integrated circuits because of their high carrier mobility. The amorphous semiconductor thin film is not limited to a polysilicon thin film, but may be a microcrystal silicon thin film or an amorphous silicon thin film.

  The TFT manufacturing method according to the present invention includes a first step of forming an amorphous semiconductor thin film on an insulating substrate, a second step of forming a gate insulating film on the amorphous semiconductor thin film, and on the gate insulating film. In addition, a third step of forming a gate electrode composed of a lower gate electrode made of a wide microcrystalline silicon and an upper gate electrode made of a narrow width, and an impurity is introduced into the amorphous semiconductor thin film through the gate electrode and the gate insulating film. A fourth step of simultaneously forming a source / drain region and an LDD region in the amorphous semiconductor thin film, and a fifth step of etching and removing the lower gate electrode using the upper gate electrode as a mask. The third step includes a step of forming a multi-layered conductive film on the gate insulating film, and a photoresist on the uppermost layer of the conductive film. And forming the upper gate electrode by subjecting the conductive film to isotropic etching using the photoresist film as a mask, and subjecting the conductive film to anisotropic etching. Forming the lower gate electrode, and the fourth step is a step of forming a film of the gate insulating film having a depth from the surface of the gate insulating film at which the impurity has a maximum value in the source / drain region. It is a step of introducing the impurity by ion implantation so as to be equal to the thickness.

  In other words, the TFT manufacturing method according to the present invention includes a first step of forming an amorphous semiconductor thin film on an insulating substrate, a second step of forming a gate insulating film on the amorphous semiconductor thin film, and a gate insulating film. A third step of forming a gate electrode composed of a wide lower gate electrode and a narrow upper gate electrode; and introducing an impurity into the amorphous semiconductor thin film through the gate electrode and the gate insulating film, thereby forming an amorphous semiconductor A fourth step of simultaneously forming a source / drain region and an LDD region on the thin film; and a fifth step of removing the lower gate electrode by etching using the upper gate electrode as a mask.

  The third step may include a step of forming a conductive film including a plurality of layers over the gate insulating film and a step of forming a gate electrode by selectively etching these conductive films. Alternatively, the third step is a step of forming a conductive film including a plurality of layers on the gate insulating film, a step of selectively forming a photoresist film on the uppermost layer of the conductive film, and using the photoresist film as a mask. Forming an upper gate electrode by subjecting the conductive film to isotropic etching, and forming a lower gate electrode by subjecting the conductive film to anisotropic etching. The isotropic etching in this case may be wet etching.

  In the present invention, a lower gate electrode larger than the upper gate electrode is formed at the time of forming the gate electrode, that is, by forming a gate electrode having a convex cross section, a single pass through the gate insulating film and the lower gate electrode is performed. By the impurity introduction step, an overlap LDD structure that can be activated at a low temperature can be obtained. Moreover, in the overlap LDD structure that realizes process saving in this way, an LDD-TFT with a low leakage current can be obtained by etching the exposed portion of the lower gate electrode using the upper gate electrode as a mask. Examples of the impurity introduction method include an ion implantation method and a diffusion method.

  Also, using the photoresist film as a mask, an upper gate electrode is formed by performing isotropic etching on the conductive film, and a lower gate electrode is formed by performing anisotropic etching on the conductive film, High throughput and low cost can be realized in that it is not necessary to prepare a photoresist mask for each layer of the upper gate electrode and the lower gate electrode.

  According to the present invention, after a single impurity introduction step through the gate insulating film and the lower gate electrode, the exposed portion of the lower gate electrode is etched using the upper gate electrode as a mask, so that the gate located on the LDD region Since the electrode can be easily removed, an LDD-TFT with reduced process and low leakage current can be obtained.

It is sectional drawing which shows 1st embodiment of TFT which concerns on this invention, and its manufacturing method. It is sectional drawing which shows 2nd embodiment of TFT which concerns on this invention, and its manufacturing method. It is a top view which shows one Embodiment of LCD which concerns on this invention. It is a graph which shows B concentration profile in silicon. 6 is a graph comparing Vg-Id characteristics of a conventional top gate TFT, an overlap LDD structure TFT described in Patent Document 6, and a TFT according to the present invention. It is sectional drawing which shows TFT manufactured using dry etching instead of wet etching in Example 2 of this invention. It is sectional drawing which shows the manufacturing method of the conventional LDD-TFT. 10 is a cross-sectional view showing an overlap type LDD structure TFT described in Patent Document 6. FIG.

  Next, the best mode for carrying out the present invention will be specifically described with reference to the accompanying drawings. FIG. 1 is a cross-sectional view showing a first embodiment of a TFT and a manufacturing method thereof according to the present invention, and the process proceeds in the order of FIG. 1 [1] to FIG. 1 [6]. Hereinafter, description will be given based on this drawing.

  The TFT 10 of this embodiment can be manufactured as follows. First, as shown in FIG. 1 [1], a base insulating film 11 is deposited on an insulating substrate (not shown). Subsequently, a silicon thin film is deposited on the entire surface, a polysilicon thin film 12 is formed by laser annealing using CW laser light or pulsed laser light, patterned into an island shape, and then a gate insulating film 13 is formed thereon. accumulate. Subsequently, after depositing a microcrystalline silicon thin film 14 to be a lower gate electrode at a temperature of 350 [° C.] or less using a plasma CVD method so as to have a film thickness of 70 [nm] or more, a metal film to be an upper gate electrode 15 is continuously deposited, and a photoresist film 16 is selectively formed on the metal film 15.

  Subsequently, as shown in FIG. 1 [2], the metal film 15 is patterned by an etching process using the photoresist film 16 as a mask to form an upper gate electrode of the gate electrode.

  Subsequently, as shown in FIG. 1 [3], a photoresist film 17 is formed on the metal film 15 and the microcrystal silicon thin film 14.

  Subsequently, as shown in FIG. 1 [4], the microcrystalline silicon thin film 14 is etched using the photoresist film 17 as a mask so as to be larger than the upper gate electrode made of the metal film 15. A lower gate electrode made of is formed.

  Subsequently, as shown in FIG. 1 [5], using an ion implantation method or the like, the gate insulating film 13, the lower gate electrode made of the microcrystal silicon thin film 14 and the metal film 15, and the upper gate electrode are used to Impurities are activated by selectively introducing impurities into the silicon thin film 12 to simultaneously form the source / drain regions 18 and the LDD regions 19 and heat-treating them at, for example, 500 [° C.]. At this time, the difference in impurity concentration between the LDD region 19 and the source / drain region 18 corresponds to the concentration of the impurity that is prevented from being introduced by the lower gate electrode made of the microcrystal silicon thin film 14.

  Subsequently, as shown in FIG. 1 [6], the exposed portion of the microcrystalline silicon thin film 14 of the lower gate electrode is removed by etching using the metal film 15 of the upper gate electrode as a mask. Thereby, the basic structure of the TFT 10 having no gate electrode on the LDD region 19 is completed.

  Although not shown in the drawings, after depositing an interlayer insulating film, a contact hole exposing the source / drain region 18 is opened. Finally, a metal thin film such as aluminum is formed, and this is patterned to form a metal wiring in contact with the source / drain region 18, thereby completing the manufacturing process of the TFT 10.

  In this way, a channel region composed of the polysilicon thin film 12, source / drain regions 18 and LDD regions 19 on both sides thereof, and a gate having a two-layer structure laminated between these regions via the gate insulating film 13 A top gate type TFT 10 having an electrode is obtained. This two-layered gate electrode is composed of a microcrystalline silicon thin film 14 as a lower gate electrode and a metal film 15 as an upper gate electrode. Therefore, the exposed portion of the microcrystalline silicon thin film 14 of the lower gate electrode can be etched using the metal film 15 of the upper gate electrode as a mask. Therefore, an LDD structure TFT having a low leakage current can be formed at low cost and in a process-saving manner. The reason for the low leakage current is that the lower gate electrode is not present on the LDD region 19, and the electric field from the lower gate electrode to the LDD region 19 is greater than when the lower gate electrode is on the LDD region 19. It can be weakened.

  FIG. 2 is a cross-sectional view showing a second embodiment of a TFT and a manufacturing method thereof according to the present invention, and the process proceeds in the order of FIG. 2 [1] to FIG. 2 [5]. Hereinafter, description will be given based on this drawing.

  As shown in FIG. 2 [1], the steps up to the deposition of the microcrystalline silicon thin film 14 and the metal film 15 and the formation of the photoresist film 16 are the same as in the first embodiment.

  Subsequently, as shown in FIG. 2 [2], only the metal film 15 is over-etched using the photoresist film 16 as a mask.

  Subsequently, as shown in FIG. 2 [3], the microcrystal silicon thin film 14 is etched using the same photoresist film 16 as a mask. As a result, two-layer gate electrodes having different widths, that is, an upper gate electrode made of the metal film 15 and a lower gate electrode made of the microcrystal silicon thin film 14 are formed.

  Subsequently, as shown in FIG. 2 [4], after removing the photoresist film 16 on the gate electrode, the lower gate electrode and the upper gate electrode made of the gate insulating film 13, the metal film 15, and the microcrystal silicon thin film 14 are formed. Then, impurities are selectively introduced into the polysilicon thin film 12 by ion implantation or the like. Then, the polysilicon thin film 12 under the microcrystal silicon thin film 14 that protrudes from the upper gate electrode becomes an LDD region 19 because the impurity concentration decreases as the impurities pass through the microcrystal silicon thin film 14. On the other hand, the polysilicon thin film 12 removed from the microcrystal silicon thin film 14 becomes a high concentration source / drain region 18 because impurities are not blocked by the microcrystal silicon thin film 14. Thus, in the present embodiment, the source / drain region 18 and the LDD region 19 can be formed simultaneously.

  The steps after impurity activation are the same as in the first embodiment. Thus, the manufacturing process of the TFT 20 is completed.

  According to the present embodiment, in addition to the same effects as those of the first embodiment, the convex gate electrode can be formed by a single photoresist process, so that it has an LDD structure with a low leakage current through a further process saving. A TFT can be formed.

  In the first and second embodiments, the LDD region 19 is provided on both the source side and the drain side, but may be provided only on the drain side. The gate electrode is a two-layer film of a microcrystal silicon thin film 14 as a lower gate electrode and a metal film 15 as an upper gate electrode. The lower gate electrode can be formed by processing a single layer film so that the cross section is convex. The upper gate electrode may be formed, or the lower gate electrode and the upper gate electrode may each be a multilayer film. Furthermore, the upper gate electrode is patterned first, and then the lower gate electrode is patterned. Conversely, the lower gate electrode may be patterned first, and then the upper gate electrode may be patterned.

  FIG. 3 is a plan view showing an embodiment of the LCD according to the present invention. Hereinafter, description will be given based on this drawing.

  The LCD 30 of this embodiment includes a liquid crystal element (not shown) sandwiched between an insulating substrate 31 on which the TFTs (not shown) of the first and second embodiments are formed, and the insulating substrate 31 and the counter substrate 32. And a drive circuit (scanning circuit 34, etc.) for driving the liquid crystal element via the TFT. These drive circuits are scanning circuits 34 and 37, level shifter / timing buffer 35, level shifter 36, data register 38, latch circuit 39, DAC circuit 40, selector circuit 41, and the like.

  The display unit 33 includes an active matrix having gate lines 42 and data lines 43 arranged in a matrix, TFTs provided at intersections of the gate lines 42 and the data lines 43, and liquid crystal elements connected to the TFTs. It is a type. A TFT (not shown) constituting the drive circuit or the like is a polysilicon TFT formed on the insulating substrate 31 simultaneously with the TFT constituting the display unit 33.

  According to the LCD 30 of the present embodiment, the display unit 33 configured by the TFT of the above-described embodiment is provided, so that high-quality display can be realized while being inexpensive. This is because the TFT of the above-described embodiment can realize a low-leakage TFT in a process-saving manner, so that the contrast ratio can be increased, color unevenness can be reduced, and good image quality can be obtained. Since details of the drive circuit and the like are well-known techniques (see, for example, Japanese Patent Application Laid-Open No. 2004-46054), the description is omitted here, but when the TFT of the above-described embodiment is used for the drive circuit, There is an advantage that malfunction can be prevented because of low leakage.

  Next, a result of actually manufacturing a top gate type TFT and evaluating its characteristics according to the first embodiment of the TFT and the manufacturing method thereof according to the present invention will be described.

First, “OA-2 substrate” manufactured by Nippon Electric Glass Co., Ltd. was used as the low temperature glass substrate. Then, using a plasma CVD method, a silicon dioxide thin film as a base insulating film was deposited to a thickness of 300 nm using SiH ₄ and N ₂ O as source gases.

Subsequently, an amorphous silicon thin film was deposited by 60 [nm] using Si ₂ H ₆ as a source gas by using a low pressure CVD method. At this time, deposition was performed for 50 minutes under the conditions of Si ₂ H ₆ flow rate of 200 [sccm], pressure of 13 [Pa], and substrate temperature of 450 [° C.]. A polysilicon thin film was formed by using a laser annealing method in which this amorphous silicon thin film was irradiated with XeCl excimer laser light having a wavelength of 308 [nm]. At this time, the laser beam was scanned and irradiated under the conditions of an energy density of 396 [mJ / cm ² ] and a beam overlap rate of 90 [%]. The polysilicon thin film was formed into an island by dry etching after patterning by a normal photoresist process.

Subsequently, a 120 nm thick silicon dioxide thin film serving as a gate insulating film was deposited on the island-formed polysilicon thin film by plasma CVD using SiH ₄ and O ₂ as source gases. At this time, TEOS flow rate 185 [sccm], O ₂ flow rate 3500 [sccm], He flow rate 100 [sccm], pressure 125 [Pa], substrate temperature 410 [° C.] and discharge power 0.33 [W / cm ⁻² ]. Deposition was performed for 70 seconds under the conditions described above. Similar results were obtained when the silicon dioxide thin film serving as the gate insulating film was set to 100 [nm] or 80 [nm].

Subsequently, a plasma CVD method was used to deposit a microcrystalline silicon thin film serving as a lower gate electrode to a thickness of 100 [nm] using SiH ₄ , PH ₃ (H ₂ dilution 5 [%]), and H ₂ as source gases. At this time, SiH ₄ flow rate 20 [sccm], PH ₃ flow rate 65 [sccm], H ₂ flow rate 2500 [sccm], pressure 260 [Pa], discharge power density 1.37 [W / cm ² ], and substrate temperature 390 Deposited for 4 minutes under the condition of [° C.].

  Here, the resistivity of the microcrystalline silicon thin film greatly depends on the film thickness. This is because the crystal component in the microcrystal silicon grows as the film thickness increases. In consideration of application to the lower gate electrode, the resistivity of the film is desirably 1 [Ωcm] or less. Therefore, the thickness of the microcrystal silicon thin film needs to be 70 [nm] or more. Further, since the growth of crystal components is promoted when the substrate temperature is high, it is desirable that the substrate temperature be high. However, excessive temperature causes a decrease in throughput and an increase in apparatus cost and process cost. Therefore, the substrate temperature is suitably up to about 350 [° C.] that can be realized by a normal plasma CVD apparatus.

Subsequently, a chromium thin film serving as an upper gate electrode was deposited by 200 [nm] using a sputtering method. Ar is used as the sputtering gas, and deposition is performed for 0.23 minutes under the conditions of an Ar flow rate of 100 [sccm], a pressure of 0.3 [Pa], a discharge power density of 2 [W / cm ² ], and a substrate temperature of 150 [° C.]. did. The resistivity of this chromium thin film was 9 × 10 ⁻³ [Ωcm]. Then, the upper layer gate electrode which consists of a chromium thin film was patterned using the normal photoresist method.

Subsequently, the chromium thin film was dry-etched with Cl ₂ , O _2, and He using a dry etching method. At this time, Cl ₂ flow rate 250 [sccm], O ₂ flow rate 150 [sccm], He flow rate 150 [sccm], pressure 40 [Pa], and discharge power density 1.3 [W / cm ² ] for 5 minutes. Etched. After the etching of the chromium thin film, the lower gate electrode was patterned again using the photoresist method.

Subsequently, dry etching of the microcrystalline silicon thin film was performed using Cl ₂ and CF ₄ as etching gases. At this time, etching was performed under the conditions of a Cl ₂ flow rate of 100 [sccm], a CF ₄ flow rate of 40 [sccm], a pressure of 3 [Pa], and a discharge power density of 0.48 [W / cm ² ]. Etching was performed.

Subsequently, after removing the photoresist film on the gate electrode, self-aligned impurity introduction using the gate electrode as a mask was performed using B ⁺ by ion implantation. The doping conditions were an acceleration voltage of 70 [keV], a dose of 2.2 × 10 ¹⁴ [cm ⁻² ], and a pressure of 0.02 [Pa]. Here, FIG. 4 will be described. FIG. 4 is a graph obtained when B ⁺ is doped from the silicon surface by ion implantation. The horizontal axis represents the depth from the silicon surface, and the vertical axis represents the impurity concentration. Since the difference can be ignored in the case of the silicon-based material of the present embodiment, the impurity concentration of the high concentration impurity introduction region (high concentration source / drain region) of the polysilicon thin film is 120 nm [silicon dioxide thin film of the gate insulating film]. ] Is a value at a depth of 120 [nm] corresponding to. On the other hand, the impurity concentration of the low concentration impurity introduction region (LDD region) is a depth of 220 [nm] corresponding to the silicon dioxide thin film 120 [nm] of the gate insulating film + the microcrystal silicon thin film 100 [nm] of the lower gate electrode. Is the value of Thus, the B concentration decreased by about an order of magnitude due to the influence of the lower layer gate electrode having a film thickness of 100 [nm].

  FIG. 4 also shows the case where the acceleration voltage is 80 [keV] and 90 [keV] for reference. It can be seen that the higher the acceleration voltage, the deeper the impurity concentration peak. Further, the depth value at which the B concentration becomes the maximum value is about 120 nm at 70 keV, about 135 nm at 80 keV, and about 155 nm at 90 keV. The depth at which the decrease of the concentration with respect to the depth becomes somewhat gentle (that is, the change in depth when the B concentration changes from 1E + 19 to 1E + 18) is about 100 nm at 70 keV and about 120 nm at 80 keV. , 90 keV is about 130 nm.

Subsequently, the exposed portion of the lower gate electrode was etched using Cl ₂ and CF ₄ as an etching gas. Etching conditions were a Cl ₂ flow rate of 100 [sccm], a CF ₄ flow rate of 40 [sccm], a pressure of 3 [Pa], and a discharge power density of 0.29 [W / cm ² ].

Subsequently, SiH ₄ , PH ₃ (H ₂ dilution 5 [%]) and H ₂ were deposited by plasma CVD using a silicon oxide film of 100 nm, and then annealing for activation was performed. Then, again using SiH ₄ , PH ₃ (H ₂ dilution 5 [%]) and H ₂ by plasma CVD, a silicon oxide film is deposited by 300 [nm], contact holes are opened by dry etching, and sputtering is performed. Then, an aluminum film was deposited to 500 [nm] and patterned to form a metal wiring. Finally, annealing was performed to complete the TFT.

  The completed TFT is manufactured at a lower process temperature, higher throughput, and lower cost than conventional TFTs, has high gate electrode reliability, and eliminates overlap between the lower gate electrode and the LDD region. As a result, an increase in leakage current is suppressed. FIG. 5 compares the Vg-Id characteristics of the conventional top gate TFT (solid line C), the overlap type LDD structure TFT described in Patent Document 6 (solid line B), and the TFT of this example (solid line A). It is a graph. The TFT of this embodiment (solid line A) has a significantly reduced leakage current compared to the conventional top gate TFT (solid line C) and the overlap type LDD structure TFT described in Patent Document 6 (solid line B). In other words, according to the top gate type TFT according to the present invention, an LDD-TFT having an effect of reducing leakage current can be formed by a mask-saving process.

  Next, a result of actually manufacturing a top gate type TFT and evaluating its characteristics according to the second embodiment of the TFT and the manufacturing method thereof according to the present invention will be described.

  First. In the same manner as in Example 1, a polysilicon thin film was formed on a glass substrate to form an island, and a gate insulating film, a microcrystal silicon thin film, and a chromium thin film were deposited.

  Subsequently, the gate electrode was patterned in substantially the same manner as in Example 1. At this time, however, the upper layer was over-etched using a wet etching method. The etchant used here was an aqueous solution of dicerium ammonium nitrate and perchloric acid at room temperature, and the etching time was 210 seconds. Then, the lower gate electrode was dry etched under the same conditions as in Example 1 while leaving the photoresist film used in the previous step. As a result, the width of the upper gate electrode is narrower by 1 [μm] on the left and right than the lower gate electrode.

  In this example, since wet etching was used, the amount of side etching could be increased as compared with the case where dry etching was used, so that a sufficient LDD region could be obtained. The wet etching may be divided into two times, and the etching accuracy may be improved by halving the etchant concentration the second time.

Subsequently, as in Example 1, impurities were introduced by ion implantation. At a portion where the gate electrode does not exist, impurities are introduced into the polysilicon thin film only through the gate insulating film, and the dose amount is 2.2 × 10 ¹⁴ [cm ⁻² ] as in the first embodiment. On the other hand, the dose amount was 3.3 × 10 ¹³ [cm ⁻² ] in the polysilicon region immediately below the portion where the upper gate electrode was side-etched to expose the lower gate electrode. As shown in FIG. 4, the B concentration decreased by about one digit due to the influence of the lower layer gate electrode having a film thickness of 100 [nm].

  After the etching process of the exposed portion, the process was the same as that in Example 1, thereby completing the LDD-TFT. The completed LDD-TFT has a lower process temperature than conventional LDD-TFTs, requires fewer impurity introductions, uses fewer masks, is manufactured with high throughput and low cost, and has low leakage current derived from the gate electrode. Met.

  Further, when the gate electrode forming step was performed by replacing the wet etching with the dry etching in this embodiment, a residue 21 made of a derivative of the lower gate electrode was generated after etching of the exposed portion, as shown in FIG. The residue 21 is an oxide of microcrystal silicon that is generated when the etching gas is in contact with the surface of the exposed microcrystalline silicon thin film when side etching is performed by dry etching or when impurities are introduced by doping. is there. If the residue 21 is present, TFT characteristics vary depending on the capacitance component, and wirings stacked thereon are damaged. Therefore, since the residue 21 is not generated and the amount of side etching cannot be sufficiently obtained by dry etching, it is preferable to use wet etching for etching the upper gate electrode as in this embodiment.

  Needless to say, the present invention is not limited to the above-described embodiments and examples. For example, in the above embodiment, amorphous silicon is used as an initial material for laser annealing, but the same effect can be obtained by using another silicon film such as polysilicon or microcrystal silicon as the initial material. It was. Further, the same effect can be obtained even when another insulating film such as a silicon nitride film or a silicon oxynitride film is used as the gate insulating film instead of the silicon oxide film. The same effect was obtained when other metal such as aluminum, tungsten silicide, molybdenum, molybdenum silicide, or tungsten molybdenum alloy was used instead of chromium as the upper gate electrode. Similarly, in the above embodiment, a p-ch TFT is manufactured using B as an impurity, but the same effect was obtained when an n-ch TFT was manufactured using P as an impurity.

[Appendix 1] From an amorphous semiconductor thin film formed on an insulating substrate, a gate insulating film formed on the amorphous semiconductor thin film, a lower gate electrode and an upper gate electrode formed on the gate insulating film A thin film transistor comprising a gate electrode and an LDD structure including a high concentration impurity introduction region and a low concentration impurity introduction region formed in the amorphous semiconductor thin film,
The impurity concentration difference between the low-concentration impurity introduction region and the high-concentration impurity introduction region corresponds to the concentration of impurities blocked by the lower gate electrode,
The gate electrode does not exist on the low concentration impurity introduction region,
A thin film transistor.

[Appendix 2] The amorphous semiconductor thin film is a polysilicon thin film.
The thin film transistor according to appendix 1, wherein:

[Appendix 3] A first step of forming an amorphous semiconductor thin film on an insulating substrate;
A second step of forming a gate insulating film on the amorphous semiconductor thin film;
A third step of forming a gate electrode comprising a wide lower gate electrode and a narrow upper gate electrode on the gate insulating film;
A fourth step of simultaneously forming a source / drain region and an LDD region in the amorphous semiconductor thin film by introducing impurities into the amorphous semiconductor thin film through the gate electrode and the gate insulating film;
A fifth step of removing the lower gate electrode by etching using the upper gate electrode as a mask;
A method for producing a thin film transistor, comprising:

[Appendix 4] The third step is:
Forming a conductive film comprising a plurality of layers on the gate insulating film;
Forming the gate electrode by selectively etching these conductive films;
The manufacturing method of the thin-film transistor of Additional remark 3 characterized by the above-mentioned.

[Supplementary Note 5] The third step includes
Forming a conductive film comprising a plurality of layers on the gate insulating film;
Selectively forming a photoresist film on the uppermost layer of the conductive film;
Forming the upper gate electrode by subjecting the conductive film to isotropic etching using the photoresist film as a mask, and forming the lower gate electrode by subjecting the conductive film to anisotropic etching; ,
The manufacturing method of the thin-film transistor of Additional remark 3 characterized by the above-mentioned.

[Appendix 6] The isotropic etching is wet etching.
The method for producing a thin film transistor according to appendix 5, wherein:

[Appendix 7] The gate insulating film is a silicon dioxide thin film,
The multi-layered conductive film is a lower microcrystal silicon thin film and an upper chromium thin film,
The wet etchant is an aqueous solution of ceric ammonium nitrate and perchloric acid,
The method for producing a thin film transistor according to appendix 6, wherein:

[Appendix 8] The amorphous semiconductor thin film is a polysilicon thin film.
8. The method for manufacturing a thin film transistor according to any one of appendices 3 to 7, wherein:

[Appendix 9] The insulating substrate on which the thin film transistor according to appendix 1 or 2 is formed, a liquid crystal element sandwiched between the insulating substrate and a counter substrate, and a drive circuit for driving the liquid crystal element through the thin film transistor. When,
A liquid crystal display device comprising:

10,20 TFT
11 Underlying insulating film 12 Polysilicon thin film 13 Gate insulating film 14 Microcrystal silicon thin film (lower gate electrode)
15 Metal film (upper gate electrode)
16, 17 Photoresist film 18 Source / drain region 19 LDD region 30 LCD

Claims (5)

An amorphous semiconductor thin film formed on an insulating substrate, a gate insulating film formed on the amorphous semiconductor thin film, and a gate electrode composed of a lower gate electrode and an upper gate electrode formed on the gate insulating film, A thin film transistor comprising an LDD structure including a high concentration impurity introduction region and a low concentration impurity introduction region formed in the amorphous semiconductor thin film,
The impurity concentration difference between the low-concentration impurity introduction region and the high-concentration impurity introduction region corresponds to the concentration of impurities blocked by the lower gate electrode,
The gate electrode does not exist on the surface of the gate insulating film on the low-concentration impurity introduction region, and a shape reflecting the residue exists.
A thin film transistor. The residue is an oxide of microcrystal silicon generated when impurities are introduced by doping after the formation of the lower gate electrode.
The thin film transistor according to claim 1. The depth from the surface of the gate insulating film that is the maximum value of the impurity concentration in the high concentration impurity introduction region is equal to the film thickness of the gate insulating film,
The thin film transistor according to claim 1 or 2, A first step of forming an amorphous semiconductor thin film on an insulating substrate;
A second step of forming a gate insulating film on the amorphous semiconductor thin film;
On the gate insulating film, a third step of forming a gate electrode composed of a lower gate electrode made of a wide microcrystalline silicon and an upper gate electrode made of a narrow width,
A fourth step of simultaneously forming a source / drain region and an LDD region in the amorphous semiconductor thin film by introducing impurities into the amorphous semiconductor thin film through the gate electrode and the gate insulating film;
And a fifth step of etching and removing the lower gate electrode using the upper gate electrode as a mask,
The third step includes
Forming a conductive film comprising a plurality of layers on the gate insulating film;
Selectively forming a photoresist film on the uppermost layer of the conductive film;
Forming the upper gate electrode by subjecting the conductive film to isotropic etching using the photoresist film as a mask, and forming the lower gate electrode by subjecting the conductive film to anisotropic etching; Including,
In the fourth step, a single ion implantation is performed so that the depth from the surface of the gate insulating film at which the impurity concentration is maximum in the source / drain region is equal to the film thickness of the gate insulating film. A step of introducing the impurity by a method,
A method for manufacturing a thin film transistor. 4. The insulating substrate on which the thin film transistor according to claim 1, 2 or 3 is formed, a liquid crystal element sandwiched between the insulating substrate and a counter substrate, and a drive circuit for driving the liquid crystal element through the thin film transistor; ,
A liquid crystal display device comprising:

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