JP2010067740A - Thin-film transistor and thin-film transistor array - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a thin-film transistor that can enhance characteristics of a thin-film transistor and keep high performance even if the number of photo-masking steps is reduced by eliminating a metal-insulator-semiconductor structure (MIS structure) formed in an accumulation capacity part so as to stabilize values of a capacitor, and to provide a display device using the same. <P>SOLUTION: The thin-film transistor array substrate includes a thin-film transistor 216 that is manufactured through photo mask steps of four times or smaller, and an accumulation capacity part 217 wherein an active semiconductor layer not contributing to the formation of a channel is silicided. <P>COPYRIGHT: (C)2010,JPO&INPIT

Description

  The present invention relates to a thin film transistor and a thin film transistor array, and more particularly to a thin film transistor and a thin film transistor array used in a liquid crystal display device and an organic EL display device.

Thin film transistors are used in many devices as switching elements. The thin film transistor is incorporated in a liquid crystal display device, an organic EL display device, or the like in order to drive each pixel arranged in a matrix.
In recent years, in display devices such as liquid crystal display devices and organic EL display devices, high performance and miniaturization of thin film transistor elements, and inexpensive process methods have been realized in order to realize low power consumption, high contrast ratio, and low cost. Development is required.

In general, in order to improve the performance of the thin film transistor element, it is necessary to reduce the parasitic resistance in the middle of the current path. This parasitic resistance can be roughly divided into two.
One is the resistance (contact resistance) existing at the interface between the active semiconductor layer and the source and drain electrodes, and the other is the resistance of the active semiconductor layer itself existing between the source and drain electrodes and the channel. (Transverse resistance).
Here, the channel is a conductive layer formed by an electric field effect in the active semiconductor layer, and hereinafter, the channel is used in this sense in this specification.

In order to reduce the contact resistance and efficiently use the applied voltage, a general method of manufacturing a thin film transistor includes a step of forming a conductive ohmic contact film between the source and drain electrodes and the active semiconductor film. It is.
This is to reduce the Schottky barrier formed when the metal of the source and drain electrodes and the active semiconductor layer are in direct contact.
There are several types of ohmic contact films. For example, an n + film obtained by doping a semiconductor film with P (phosphorus) using a phosphine (PH3) gas is one of the commonly used ohmic contact films.

It is disclosed that a thin film transistor having an ohmic contact film such as an n + film can be classified into two types depending on a structure when the n + film is removed by etching (for example, see Non-Patent Document 1).
According to this Non-Patent Document 1, one is a channel etch type thin film transistor that removes the n + film by over-etching a part of the active semiconductor layer that forms the channel, and the other forms the channel. It is shown that this is a channel protection type thin film transistor in which a protective film is newly formed immediately above the active semiconductor layer to prevent overetching of the active semiconductor layer that occurs when the n + film is removed.

  In recent years, in a thin film transistor array substrate for a display device whose area is rapidly increasing, cost reduction and simplification of a manufacturing process are important issues. In particular, since reducing the number of mask processes using a photomask directly leads to the solution of the above problem, research is actively conducted to reduce the five mask processes to four times or forcibly three times.

For this reason, channel etch type thin film transistors, which have a smaller number of mask processes and processes than channel protection types, are often used in thin film transistor array substrates fabricated by four or three mask steps.
Ikuhiro Ukai “All about Thin Film Transistor Technology” Chapter 3 Device Structure and Characteristics of Thin Film Transistors Device structure and electrical characteristics of a-Si TFT 34 items

However, in the channel etch type thin film transistor described above as the prior art, a toxic gas is used when forming the ohmic film, the manufacturing equipment becomes complicated, and the active semiconductor layer is removed by an etching process for removing the ohmic contact film. It is necessary to laminate the film thickly.
In particular, the process of laminating the active semiconductor layer thickly has a problem that not only the cost increases, but also causes an increase in transverse resistance and a deterioration in display performance due to an increase in light leakage current.

  For channel-etched thin film transistors, reduction of the transverse resistance due to the thickness of the active semiconductor layer is an important issue for improving the characteristics. If the channel length is set short in order to increase the current value, the ratio of the transverse resistance to the resistance of the entire thin film transistor element is increased, the mobility is decreased, and the switching characteristics are greatly deteriorated.

  As a solution to this transverse resistance, it is conceivable to use a known channel protection type thin film transistor in which a protective film is deposited on the active semiconductor layer. The formation of the protective film prevents the active semiconductor layer from being over-etched when the ohmic contact film is etched, and enables the active semiconductor layer to be thinned.

  However, in general, the channel protection type thin film transistor as described above has a problem that the number of photomasks is one more and the manufacturing cost is increased as compared with the channel etch type. Therefore, it is not suitable for a thin film transistor array substrate manufactured by a four-time mask process or a three-time mask process aiming at reducing the cost and simplifying the manufacturing process by reducing the number of photomasks.

In addition, a new problem has arisen in the thin film transistor array substrate manufactured by the four-time mask process or the three-time mask process.
This is a problem that a storage capacitor portion provided for holding a voltage includes an active semiconductor layer and forms a metal-insulator- (active) semiconductor structure (MIS structure).
As a result, the capacitance depends on the voltage, which adversely affects the display performance. Further, in the channel etch type thin film transistor array substrate, since the active semiconductor layer is stacked thick, the capacitance greatly varies depending on the voltage.

  An object of the present invention is to provide a thin film transistor having high performance and a method for manufacturing a display device using the same while simplifying a manufacturing process.

  In order to solve the above problems, a thin film transistor of the present invention is an active semiconductor made of non-single crystal silicon in a thin film transistor comprising an active semiconductor layer made of non-single crystal silicon, a source electrode, a drain electrode, and a gate electrode on a substrate. A feature is that a silicide layer containing silicide as a main component is formed between the surface of the layer and a channel formed by an electric field effect.

  That is, the thin film transistor includes at least a gate electrode, a gate insulating film, an active semiconductor layer, a source electrode and a drain electrode, a channel formed by a field effect, the source electrode, the drain electrode, and the In the thin film transistor constituted by the ohmic contact film existing between the channel, the thin film transistor is formed by adopting a structure in which the ohmic contact film is brought closer to the channel.

  More preferably, the ohmic contact film and the channel are formed by direct connection.

The ohmic contact film is formed by reacting the active semiconductor layer with the constituent materials of the source electrode and the drain electrode.
Alternatively, a layer containing a substance to be reacted separately may be provided on the active semiconductor layer and then reacted with the active semiconductor layer. Here, the reactant with the active semiconductor is referred to as silicide.

  The silicide layer is formed at least 5 nm or more in the active semiconductor layer. Preferably, the source and drain electrodes and the channel are directly connected via the silicide layer.

  Preferably, the active semiconductor layer has a thickness of 30 nm to 200 nm.

  In order to solve the above problems, a thin film transistor array of the present invention includes at least a gate wiring, a gate electrode, and a storage capacitor electrode, a gate insulating film, an active semiconductor layer, a source wiring, a source electrode, and a drain electrode on a substrate. In the thin film transistor array including the protective film and the pixel electrode, a part of the semiconductor layer formed on the storage capacitor electrode is formed by a silicide layer containing silicide as a main component.

  According to the present invention, the manufacturing process of the conventional ohmic contact film can be omitted, so that the manufacturing process can be simplified and the thin film transistor can be manufactured at low cost.

  Further, according to the present invention, it is not necessary to form a thick active semiconductor layer, and the film formation time can be shortened. This makes it possible to form a high-quality active semiconductor layer by low-speed film formation and improve the performance of the thin film transistor.

  Further, according to the present invention, the transverse resistance due to the thickness of the active semiconductor layer can be reduced, and the characteristics of the thin film transistor can be improved.

Furthermore, when such a thin film transistor is used in a display device such as a liquid crystal display device or an organic EL display device, light leakage current due to light from the light emitting portion can be reduced because the active semiconductor layer is thin.
In addition, when the reduction of the number of photomasks is studied, the MIS structure formed in the storage capacitor portion can be eliminated. Accordingly, high display performance can be maintained while reducing manufacturing costs.

  Prior to the detailed description of the embodiments, the structure of the thin film transistor and the thin film transistor array according to the present invention will be described as being used for a display device. The display device here refers to, for example, a flat panel display such as a liquid crystal display device or an organic EL display device.

FIG. 1 shows a pixel on a thin film transistor array substrate according to the present invention.
In FIG. 1, a pixel indicates a region surrounded by adjacent gate wiring 1 and source wiring 2. Since many gate lines 1 and source lines 2 are arranged in parallel on the substrate, the pixels are arranged in a matrix. In the pixel, at least one thin film transistor 3, a pixel electrode 4, and a storage capacitor 5 are provided.

The thin film transistor 3 includes a gate electrode 6 connected from the gate wiring 1, a source electrode 7 connected from the source wiring 2, and a drain electrode 8 connected to the pixel electrode 4.
Note that the thin film transistor 3 in the pixel is used as a switching element that transfers the display voltage to the display region, but a plurality of thin film transistors 3 may be provided as necessary.

  The gate electrode 6 of the thin film transistor 3 is connected to the gate wiring 1 and is connected to the drive circuit via the gate terminal electrode 9 at the end of the gate wiring 1. Similarly, the source electrode 7 is also connected to the source line 2 and connected to another drive circuit via the source terminal electrode 10 at the end of the source line 2.

The switching method of the thin film transistor 3 will be briefly described as follows.
A gate signal input from the gate terminal electrode 9 applies a voltage to the gate electrode 6 via the gate wiring 1. As a result, when the thin film transistor 3 is turned on, a current flows from the source electrode 7, and a display voltage is applied from the source electrode 7 to the drain electrode 8.
The storage capacitor 5 is used to hold a signal voltage when the thin film transistor 3 is off. The illustrated storage capacitor 5 is formed using a part of another gate wiring 1, but may be formed using a dedicated wiring separately.

<< First Embodiment >>
Hereinafter, a first embodiment of the best mode for carrying out the present invention will be described in detail with reference to FIG.
FIG. 2 is a cross-sectional view showing a commonly used method in order to make it easy to see the main components of the thin film transistor according to the present invention.

In FIG. 2, 100 is a substrate, 6 is a gate electrode formed on the substrate, 101 is a gate insulating film formed on the gate electrode, and 106 is formed by a field effect when a gate voltage is applied. A channel layer 102 is an active semiconductor layer provided to form the channel, 105 is a silicide layer serving as an ohmic contact film, and 7 and 8 are connected to the active semiconductor layer or channel via the silicide layer 105. Source electrode and drain electrode.
Reference numeral 103 provided so as to cover the thin film transistor is a protective film. Reference numeral 104 denotes a contact hole provided for making electrical contact with an external device.

Here, the silicide layer 105 proceeds from the surface of the active semiconductor layer 102 toward the channel layer 106 side by at least 5 nm or more.
In addition, the thickness of the active semiconductor layer 102 is desirably 30 nm or more and 200 nm or less.

Next, a manufacturing example of a thin film transistor will be described.
First, the substrate 100 is prepared and cleaned using an appropriate solution or the like depending on the situation. Examples of the substrate include a glass substrate.
Next, a metallic thin film to be the gate electrode 6 is formed on the substrate 100 by a sputtering method or the like.
Thereafter, a resist made of a photosensitive resin is uniformly applied on the metal thin film by spin coating, and exposure and development are performed. Thereby, the photoresist is patterned into a desired shape (photolithography process).
Thereafter, the metal thin film is etched using a dry etching method or a wet etching method, and then the photoresist is removed. Thereby, the gate electrode 6 is formed (FIG. 2a).

Next, the gate insulating film 101 and the active semiconductor film 102 are continuously formed on the substrate on which the gate electrode 6 is formed using a film forming method such as plasma CVD.
In the thin film transistor of this embodiment formed through the same process as the channel etch type except for the conventional n + film etching process, the back channel effect occurs when the active semiconductor layer 102 is too thin, and the performance deteriorates.
For this reason, it is desirable that the active semiconductor layer 102 has a thickness of 30 nm or more.

In addition, since a heat treatment step for forming silicide is not performed thereafter, it is desirable that the formation temperature of the active semiconductor layer 102 be sufficiently high. The purpose of this is to prevent the active semiconductor layer 102 from being deteriorated by heat treatment during silicide formation.
In this embodiment, since amorphous silicon is used for the active semiconductor layer 102, film formation was performed with the substrate temperature set at 280 degrees.
Thereafter, a photolithography process is performed, and an etching process is performed using a dry etching method or a wet etching method.
Next, when the photoresist is removed, an island pattern of the active semiconductor layer 102 is formed (FIG. 2b).

Next, a metallic thin film to be a constituent part of the source / drain electrodes is formed by sputtering or the like. This metallic thin film contains a material for forming a silicide layer.
Thereafter, a photolithography process is performed, an etching process is performed, the photoresist is removed, and a pattern is formed. Thereby, the source electrode 7 and the drain electrode 8 are formed (FIG. 2c).

Next, the protective film 103 is formed by plasma CVD or the like. The deposition temperature of the protective film 103 needs to be set sufficiently high so as not to be deteriorated by the heat treatment at the time of silicide formation. In this example, the film was formed at 270 degrees.
Thereafter, a photolithography process is performed, an etching process is performed, and the photoresist is removed. This forms contact holes 104 that allow the source / drain electrodes to be in electrical contact with external devices (FIG. 2d).

As the last step, heat treatment is performed in a nitrogen atmosphere or in a vacuum. Thus, the silicide layer 105 can be formed from the interface between the source / drain electrodes and the active semiconductor layer 102.
At this time, it is desirable that the heat treatment is performed at a temperature of 230 ° C. or higher, preferably 250 ° C. or higher for 10 minutes or longer (FIG. 2e).

The thickness of the silicide layer 105 was obtained by measuring the capacitance of a MIS structure element having a metal-insulating film-active semiconductor film fabricated on the same substrate.
As a result, it was found that the transfer characteristics of the thin film transistor can realize the mobility equivalent to that of the thin film transistor sandwiching the n + film formed by the conventional method when the silicide is formed to have a thickness of about 5 nm or more.

Even with a thin film transistor having a channel length of 10 μm or less, sufficient mobility could be obtained despite the lack of a conventional n + film.
The value is 0.4 cm ² / Vs for an element having a channel length (L) of 10 μm and a channel width (W) of 80 μm. An element having L of 4 μm and W of 50 μm obtained 0.3 cm ² / Vs.
The on / off ratio was 7 digits. As described above, the reason why sufficient mobility is obtained even in a short region where L is less than 10 μm is largely due to the fact that the transverse resistance is reduced by making the active semiconductor layer 102 thinner.
Further, since the n + film etching step is not included, it is considered that the back channel effect is suppressed.

In this embodiment, after forming the protective film, silicide is formed by heat treatment. However, the heat treatment forms the active semiconductor layer 102 and activates the metal thin film that becomes the constituent parts of the source electrode 7 and the drain electrode 8. Anytime after the state of being deposited on the semiconductor layer 102 may be performed.
For example, the silicide layer 105 can be formed at the same time by forming the protective film 103 at the appropriate temperature.
Further, for example, heat treatment may be applied after the source electrode 7 and the drain electrode 8 are formed by etching. Furthermore, for example, heat treatment may be performed in a process immediately after the metal thin film is deposited on the active semiconductor layer 102. However, in that case, a process of lightly removing the silicide formed on the upper part of the channel later by an appropriate method is required.

<< Second Embodiment >>
Hereinafter, a second embodiment of the best mode for carrying out the present invention will be described in detail with reference to FIG.
FIG. 3 is a diagram showing the structure of the second embodiment of the thin film transistor according to the present invention.

As shown in FIG. 3A, a structure is employed in which the width of the island of the active semiconductor layer 102 is made smaller than the width of the gate electrode 6.
As a result, the metal components of the source electrode 7 and the drain electrode 8 and the channel layer 106 are directly connected via the silicide layer 105, and the sufficiently high mobility can be realized even with a short channel length by reducing the transverse resistance as much as possible. It becomes possible.

  Further, by adopting this structure, even if the active semiconductor layer 102 is formed thick, the transverse resistance does not increase. This makes it possible to increase the thickness of the active semiconductor layer 102 and reduce the back channel effect as much as possible, thereby improving the performance of the thin film transistor.

Even in the structure shown in FIG. 3B, the same effect as that shown in FIG. 3A can be obtained. By crushing the active semiconductor layer 102 between the source electrode 7 and drain electrode 8 and the channel layer 106 by silicidation, the transverse resistance can be reduced as much as possible.
In the case of adopting this structure, the active semiconductor layer 102 needs to be stacked sufficiently thin so as not to affect the characteristics.

<< Third Embodiment >>
Hereinafter, a third embodiment of the best mode for carrying out the present invention will be described in detail with reference to FIG.
FIG. 4 is a diagram showing the structure of the third embodiment of the thin film transistor according to the present invention.

The thin film transistor shown in the third embodiment is formed from the same structure as that of the first embodiment and the second embodiment, but the manufacturing process is partially changed.
That is, a substance for forming the silicide layer 105 is thinly formed between the step of forming the active semiconductor layer 102 and the step of forming a metal thin film for forming the source electrode 7 and the drain electrode 8. There is a difference in that there is a film forming process.

First, similarly to the method illustrated in the first embodiment, the gate electrode 6 is formed, and the gate insulating film 101 and the active semiconductor layer 102 are sequentially formed.
At this time, it is desirable that the thickness of the active semiconductor layer 102 be sufficiently thin as long as the characteristics are not adversely affected. For example, 30 nm or more and 200 nm or less are good (FIG. 4a).

Next, a silicide material layer 107 as a material for forming the silicide layer 105 is formed on the active semiconductor layer 102 by a CVD method, a sputtering method, or the like.
As a preferred simple manufacturing process, for example, there is a method in which phosphine (PH 3) gas is decomposed by a CVD method and a silicide material containing P (phosphorus) is deposited on the active semiconductor layer 102.
Thereafter, a metallic thin film that becomes a constituent part of the source electrode 7 and the drain electrode 8 is formed thereon by sputtering or the like. At this point, four layers of the metal thin film 108 for forming the gate insulating film 101, the active semiconductor layer 102, the silicide material layer 107, the source electrode 7, and the drain electrode 8 are formed on the gate electrode 6 ( FIG. 4b).

Next, similarly to the method illustrated in the first embodiment, a photolithography process is performed, an etching process is performed using a dry etching method or a wet etching method, and the metallic thin film is first etched.
Thereby, the source electrode 7 and the drain electrode 8 are formed. Thereafter, the silicide material layer 107 is removed by a dry etching method, a wet etching method, or other appropriate methods.
For example, in the case of the silicide material layer 107 containing P (phosphorus) used in this embodiment, a method of performing hydrogen plasma treatment by CVD can be considered. As a result, it is possible to combine P (phosphorus) with hydrogen to return to the gaseous state and remove it again. (Fig. 4c)

  Next, the protective film 103 is formed by plasma CVD or the like. The deposition temperature of the protective film 103 needs to be set sufficiently high so as not to be deteriorated by the heat treatment at the time of silicide formation. Thereafter, a photolithography process is performed, an etching process is performed, and the photoresist is removed. This forms contact holes 104 that allow the source / drain electrodes to be in electrical contact with external devices (FIG. 4d).

As the last step, heat treatment is performed in a nitrogen atmosphere or in a vacuum. Thereby, the silicide layer 105 can be formed from the interface of the source electrode 7, the drain electrode 8 and the active semiconductor layer 102.
The heat treatment temperature at this time is 230 ° C. or higher, preferably 250 ° C. or higher and 10 minutes or longer.
Further, as in the second embodiment, it is desirable to silicide all of the active semiconductor layer 105 existing between the channel layer 106 and the source electrode 7 and the drain electrode 8 (FIG. 4e).

In the third embodiment, the silicide layer 105 is formed by heat treatment after the protective film 103 is formed. However, in the heat treatment, the active semiconductor layer 102 is formed and the silicide material layer 107 is formed by the active semiconductor layer 102. It may be done anytime after the state of being deposited on.
For example, the silicide layer 105 can be formed at the same time by forming the protective film 103 at the appropriate temperature. Further, for example, the source electrode 7 and the drain electrode 8 may be formed by etching, and heat treatment may be applied to a process immediately after the silicide material layer 107 on the channel is removed by the above method or the like.
Furthermore, for example, the heat treatment may be performed immediately after the metal thin film is deposited on the active semiconductor layer 102. However, in that case, a process of lightly etching the silicide layer 105 formed on the channel layer 106 later by an appropriate method is required.

<< Fourth Embodiment >>
Hereinafter, the fourth embodiment of the best mode for carrying out the present invention will be described in detail with reference to FIG.
FIG. 5 is a diagram showing a structure of a thin film transistor array substrate manufactured by a three-photomask process of a thin film transistor array substrate according to the present invention as a fourth embodiment.

The thin film transistor array substrate shown in the fourth embodiment can maintain high performance even if the number of photomask processes is reduced by using the first embodiment, the second embodiment, and the third embodiment. A method for manufacturing a thin film transistor array substrate for a display device will be described.
That is, in the fourth embodiment, as shown in FIG. 6, in the thin film transistor array substrate manufactured by the four photomask process, particularly the three photomask process, the thin film transistor is formed in the storage capacitor portion while improving the characteristics of the thin film transistor. A method is provided to eliminate the metal-insulator-semiconductor (MIS) structure.

Hereinafter, the structure of the thin film transistor array substrate of the fourth embodiment will be described by taking a thin film transistor array substrate manufactured by a three-photomask process as an example.
Note that there are many methods other than the example shown below in the three-photomask process, but since the storage capacitor portion includes the MIS structure in any case, the fourth embodiment of the present invention is the It is effective for coping.

First, a first metallic thin film is formed on a transparent insulating substrate 200 using a sputtering method or the like.
Next, a resist is applied onto the substrate 100 by spin coating or the like, exposed through a mask, and developed for the first photomask process.
Thereby, the photoresist is patterned.
Thereafter, the metal thin film is etched using a dry etching method or a wet etching method, and then the photoresist is removed.
As a result, the gate electrode 6, the gate wiring 201, the storage capacitor electrode 201 shared with the gate wiring, and the gate terminal electrode 9 are formed (FIG. 5a).

Next, the gate insulating film 101 and the active semiconductor layer 102 are sequentially formed by using a CVD method or the like, and then the second metallic thin film 202 including the silicide material is formed by using a sputtering method or the like (FIG. 5b). .
At this time, if the second metal thin film 202 does not contain a large amount of silicide material, the step of forming the active semiconductor layer 102 and the second metal thin film are formed as in the third embodiment. It is necessary to include a step of thinly forming a substance for forming the silicide layer 105 between the steps.

Thereafter, a second photomask process is performed. At this time, the mask placed on the channel formation region is formed of a semi-transmissive portion, and the resist is half-exposed. As a result, the resists 203, 204, and 205 are patterned into the shape shown in FIG.
Next, the second metal thin film 202, the active semiconductor layer 102, and the gate insulating film 101 are etched using the patterned resists 203, 204, and 205 as a mask. When the silicide material layer 107 is formed, it is necessary to include a step of removing the silicide material layer 107 between the steps of removing the second metallic thin film and the active semiconductor layer 102. In the step of removing the active semiconductor layer 102, the silicide material layer 107 can also be removed (FIG. 5d).

It should be noted here that a metal-insulator-semiconductor (MIS) structure is formed including the active semiconductor layer 102 on the storage capacitor electrode 202.
When a known channel-etched thin film transistor using an n + film is adopted in the fourth embodiment, the active semiconductor layer 102 is formed thick in consideration of over-etching that occurs when the n + film is etched in a later step. There must be.
Therefore, the capacitance depends on the voltage and adversely affects the display performance. In the fourth embodiment, the active semiconductor layer 102 does not need to be formed thick, and the active semiconductor layer 102 can be silicided and the MIS structure can be eliminated by a subsequent process.

Next, ashing is performed until the low portion of the resist 203 on the channel formation region is completely removed.
Thereafter, using this resist pattern, the second metallic thin film 202 of the thin film transistor constituent portion is etched to form the source electrode 7 and the drain electrode 8.
When the silicide material layer 107 is formed, the silicide material layer 107 is removed by etching or an appropriate technique after the second metallic thin film is etched.
For example, as shown in the third embodiment, in the case of a silicide material layer 107 containing P (phosphorus), a method of performing hydrogen plasma treatment by CVD is conceivable.
As a result, it is possible to combine the P (phosphorus) compound and hydrogen back into the gas state and remove them (FIG. 5e).

  Next, a resist 206 is formed on the gate terminal electrode 9 using a printing technique. Thereby, the number of photomask processes can be reduced once.

Next, a protective film 103 is formed on the front surface. At this time, the silicide layer 105 can be formed in the thin film transistor portion 207 and the storage capacitor portion 208 by setting the temperature during film formation to 230 ° C. or higher, more preferably 250 ° C. or higher.
Alternatively, a heat treatment step for forming the silicide layer 105 may be appropriately performed before and after the protective film 103 is formed. At this time, as a more preferable form, it is desirable that the active semiconductor layer 102 having an adverse effect on the transistor characteristics and display performance is silicided as a whole (FIG. 5f).

  Next, the resist with the protective film on the top is lifted off using a resist remover. As a result, all the resist on the substrate is removed.

Finally, a transparent conductive thin film is formed on the entire surface, and a third photomask process is performed for patterning. Thereafter, the resist is removed and the pixel electrode 4 is formed.
In this way, the thin film transistor array substrate is completed in three photomask processes (FIG. 5g).

As shown in FIG. 6, in the thin film transistor portion 207, the method of siliciding the active semiconductor layer 102 can prevent over-etching of the active semiconductor layer 102 that occurs when the known n + film is removed.
As a result, it is not necessary to form the active semiconductor layer 102 thickly, the transverse resistance can be reduced, and it is possible to directly connect to the channel via the silicide layer, and good characteristics can be obtained.

  At the same time, the metal-insulator-semiconductor structure (MIS) formed in the storage capacitor portion 208 can be eliminated by changing the active semiconductor layer 102 to the silicide layer 105. This stabilizes the capacitance and makes it possible to maintain a good signal voltage.

It is a figure which shows the pixel of the thin-film transistor array substrate which concerns on this invention. It is a figure which shows the manufacturing process of the thin-film transistor which concerns on this Embodiment 1. FIG. It is a figure which shows the structure of the thin-film transistor which concerns on this Embodiment 2. FIG. It is a figure which shows the manufacturing process of the thin-film transistor which concerns on this Embodiment 3. FIG. It is a figure which shows the manufacturing process of the thin-film transistor array substrate which concerns on this Embodiment 4. It is a figure which shows the structure of the thin-film transistor array substrate which concerns on this Embodiment 4.

Explanation of symbols

1 …………………………………… Gate wiring 2 …………………………………… Source wiring 3 …………………………………… Thin film transistor 4 …………………………………… Pixel electrode 5 …………………………………… Storage capacity 6 …………………………………… Gate Electrode 7 …………………………………… Source electrode 8 …………………………………… Drain electrode,
9 …………………………………… Gate terminal electrode 10 …………………………………… Source terminal electrode,
100 ……………………………… Substrate 101 ……………………………… Gate Insulating Film 102 ……………………………… Active Semiconductor Layer 103 ……… ……………………… Protective film 104 ………………………… Contact hole 105 ……………………………… Silicide layer 106 …………………… ………… Channel layer 107 ……………………………… Silicide material layer 108 ………………………… Metal thin film 200 for forming source and drain electrodes. Insulating substrate 201 ……………………………… Gate wiring and storage capacitor electrode 202 ……………………………… Second metallic thin film 203 , 204, 205 ………… Registration 206 ………………………… Registration (printing)
207 ……………………………… Thin film transistor section 208 ……………………………… Storage capacity section

Claims (6)

In a thin film transistor comprising an active semiconductor layer made of non-single-crystal silicon, a source electrode, a drain electrode, and a gate electrode on a substrate,
A thin film transistor, wherein a silicide layer containing silicide as a main component is formed between a surface of an active semiconductor layer made of non-single crystal silicon and a channel formed by an electric field effect. The silicide layer is
2. The thin film transistor according to claim 1, wherein the thin film transistor is formed at least 5 nm or more from the source electrode and the drain electrode side to the channel side. The thickness of the active semiconductor layer is:
The thin film transistor according to claim 1, wherein the thin film transistor has a thickness of 30 nm to 200 nm. The silicide layer is
2. The thin film transistor according to claim 1, wherein the thin film transistor is in direct contact with the channel. The constituent material of the silicide layer is:
It is composed of one or more elements from Mg, Cr, Mo, W, Mn, Fe, Co, Ni, Cu, Ag, Au, Zn and one or more elements from Group 13 to Group 15 of the periodic table. The thin film transistor according to claim 1, wherein the thin film transistor is provided. In a thin film transistor array comprising at least a gate wiring, a gate electrode and a storage capacitor electrode, a gate insulating film, an active semiconductor layer, a source wiring, a source electrode and a drain electrode, a protective film, and a pixel electrode on a substrate,
A thin film transistor array, wherein a part of a semiconductor layer formed on the storage capacitor electrode is formed by a silicide layer containing silicide as a main component.

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