JP2007142263A - Semiconductor device, method for manufacturing the same and electronic equipment - Google Patents

Abstract

<P>PROBLEM TO BE SOLVED: To provide a method for manufacturing a semiconductor device for quickening the responding speed of a thin film transistor, and for reducing stress added to a substrate in comparison with a conventional manner. <P>SOLUTION: This method for manufacturing a semiconductor device comprises a process for forming an island-shaped first semiconductor layer 102a and an island-shaped semiconductor layer 102b on a base insulating film 101, a process for forming a first gate insulating film 103a positioned on the first semiconductor layer 102a and a second gate insulating film 103b positioned on the second semiconductor layer 102a, a process for forming a first conductive film 104 having compression stress on the first gate insulating film 103a and the second gate insulating film 103b, a process for forming a second conductive film 105 having tensile stress on the first conductive film 104, a process for forming a first gate electrode 106a and a second gate electrode 106b by etching the first and second conductive films 104 and 105, and a process for making thin or removing the second conductive film 105b configuring the second gate electrode 106b. <P>COPYRIGHT: (C)2007,JPO&INPIT

Description

  The present invention relates to a semiconductor device manufacturing method, a semiconductor device, and an electronic apparatus.

  It has been conventionally known that the mobility in an n-type thin film transistor is improved by applying a tensile stress to the semiconductor layer of the n-type thin film transistor having a (100) -oriented crystal orientation.

  As a method for increasing the carrier mobility of the n-type thin film transistor, that is, a method for increasing the response speed of the n-type thin film transistor, there is a method in which a tensile stress is applied to the semiconductor substrate serving as the channel region. Since the semiconductor substrate is distorted by the stress, the carrier mobility is increased (for example, see Non-Patent Document 1). In Non-Patent Document 1, a stress generation source is a silicon nitride film formed on an n-type thin film transistor.

A similar technique is also described in Patent Document 1. In Patent Document 1, a tensile stress generation source is a stress adjustment film formed on a gate electrode. The gate electrode and the stress adjustment film are formed by laminating a conductive layer (for example, a TiN layer) serving as a stress adjustment film on a conductive layer (for example, an Al layer) serving as a gate electrode and simultaneously patterning these two conductive layers. (For example, paragraphs 50 and 51 of Patent Document 1).
Nikkei Electronics, August 2005, p87-p94 JP 2001-60691 A (FIG. 1)

  When the above-described conventional technique is applied when forming a plurality of n-type thin film transistors and p-type thin film transistors on the same substrate, a stress adjusting film is also formed on the gate electrode of the p-type thin film transistor. Therefore, the stress applied to the entire substrate is increased and the substrate is distorted.

  In addition, when a thin film transistor is formed over a substrate, a wiring is often formed in the same process as the gate electrode of the transistor. In this case, when the above-described conventional technique is applied, a stress adjusting film is also formed on the wiring, so that a stress applied to the entire substrate is increased and the substrate is distorted.

  In particular, when this technique is applied to an active matrix circuit of a display device, the substrate of the active matrix circuit has been increased in size, so that the distortion of the entire substrate becomes remarkable.

  The present invention has been made in consideration of the above-described circumstances, and an object of the present invention is to provide a semiconductor device manufacturing method and a semiconductor device in which the response speed of the thin film transistor is increased and the stress applied to the substrate is reduced as compared with the prior art. And providing an electronic device.

In order to solve the above problems, a method of manufacturing a semiconductor device according to the present invention includes a step of forming an island-shaped first semiconductor layer and an island-shaped second semiconductor layer on a base insulating film,
Forming a first gate insulating film located on the first semiconductor layer and a second gate insulating film located on the second semiconductor layer;
Forming a first conductive film having compressive stress on the first gate insulating film and the second gate insulating film;
Forming a second conductive film having a tensile stress on the first conductive film;
The first and second conductive films are etched to form a first gate electrode located on the first gate insulating film and a second gate electrode located on the second gate insulating film. And a process of
And thinning or removing the second conductive film constituting the second gate electrode.
“Etching” in the above description means etching by transferring a mask pattern by lithography or the like. Transferring a mask pattern by lithography or the like is defined as including a mask pattern transfer technique using an inkjet method, a mask pattern transfer technique using a nanoimprint method, and the like in addition to a lithography method. The same applies to the following description.

  In the semiconductor device manufactured by the method for manufacturing a semiconductor device, the second gate electrode has a structure in which the thickness of the second conductive film is thinner than that of the second conductive film included in the first gate electrode. Or is formed of only the first conductive film. The first conductive film has a compressive stress, and the second conductive film has a tensile stress.

  For this reason, the stress of the first gate electrode can be a tensile stress, and the stress of the second gate electrode can be a tensile stress smaller than the first gate electrode, 0 GPa, or substantially 0 GPa. Therefore, the response speed of the thin film transistor having the first gate electrode can be increased, and the stress applied to the substrate of the semiconductor device by the first and second gate electrodes can be reduced.

  Further, the stress of the first gate electrode can be a tensile stress, and the stress of the second gate electrode can be a compressive stress. In this case, the response speed of the thin film transistor having the first gate electrode can be increased, and the stress applied to the substrate of the semiconductor device by the first and second gate electrodes can be reduced. Furthermore, the sum of the tensile stress of the first gate electrode and the compressive stress of the second gate electrode can be 0 GPa or approximately 0 GPa. In this case, the first and second gate electrodes can be applied with almost no stress on the substrate of the semiconductor device.

Another method of manufacturing a semiconductor device according to the present invention includes forming an island-shaped first semiconductor layer and an island-shaped second semiconductor layer on a base insulating film,
Forming a first gate insulating film located on the first semiconductor layer and a second gate insulating film located on the second semiconductor layer;
Forming a first conductive film having a tensile stress on the first gate insulating film and the second gate insulating film;
Forming a second conductive film having a compressive stress on the first conductive film;
The first and second conductive films are etched to form a first gate electrode located on the first gate insulating film and a second gate electrode located on the second gate insulating film. And a process of
A step of thinning or removing the second conductive film constituting the first gate electrode.

  In the semiconductor device manufactured by the method for manufacturing a semiconductor device, the second conductive film included in the second gate electrode is thicker than the second conductive film included in the first gate electrode. The first conductive film has a tensile stress, and the second conductive film has a compressive stress.

  For this reason, the stress of the first gate electrode can be used as a tensile stress, and the tensile stress of the second gate electrode can be reduced or a compressive stress. Accordingly, the response speed of the thin film transistor having the first gate electrode can be increased, and the stress applied to the substrate of the semiconductor device by the first and second gate electrodes can be reduced, or 0 GPa or approximately 0 GPa. .

Another method of manufacturing a semiconductor device according to the present invention includes forming an island-shaped first semiconductor layer and an island-shaped second semiconductor layer on a base insulating film,
Forming a first gate insulating film located on the first semiconductor layer and a second gate insulating film located on the second semiconductor layer;
Forming a first conductive film having compressive stress on or above the base insulating film, on the first gate insulating film, and on the second gate insulating film;
Forming a second conductive film having a tensile stress on the first conductive film;
Etching the first and second conductive films to form a first gate electrode located on the first gate insulating film, a second gate electrode located on the second gate insulating film, and the Forming a wiring located above or above the base insulating film;
And thinning or removing the second conductive film forming the wiring and the second conductive film constituting the second gate electrode.

  In the semiconductor device manufactured by the method for manufacturing a semiconductor device, the second gate electrode and the wiring have the second conductive film having a thickness of the second conductive film that the first gate electrode has. It has a thinner structure or is formed of only the first conductive film. The first conductive film has a compressive stress, and the second conductive film has a tensile stress.

  For this reason, the stress of the first gate electrode is set to a tensile stress, and the stress of the second gate electrode and the stress of the wiring are set to a tensile stress smaller than the first gate electrode, 0 GPa, or approximately 0 GPa. can do. Accordingly, the response speed of the thin film transistor having the first gate electrode can be increased, and the stress applied to the substrate of the semiconductor device by the first and second gate electrodes and the wiring can be reduced.

  Further, the stress of the first gate electrode can be a tensile stress, and the stress of the second gate electrode and the stress of the wiring can be a compressive stress. In this case, the response speed of the thin film transistor having the first gate electrode can be increased, and the stress applied to the substrate of the semiconductor device by the first and second gate electrodes and the wiring can be reduced. Furthermore, the sum of the tensile stress of the first gate electrode, the compressive stress of the second gate electrode, and the compressive stress of the wiring can be 0 GPa or approximately 0 GPa. In this case, it is possible that the first and second gate electrodes and the wiring hardly apply stress to the substrate of the semiconductor device.

Another method of manufacturing a semiconductor device according to the present invention includes forming an island-shaped first semiconductor layer and an island-shaped second semiconductor layer on a base insulating film,
Forming a first gate insulating film located on the first semiconductor layer and a second gate insulating film located on the second semiconductor layer;
Forming a first conductive film having a tensile stress on or above the base insulating film, on the first gate insulating film, and on the second gate insulating film;
Forming a second conductive film having a compressive stress on the first conductive film;
Etching the first and second conductive films to form a first gate electrode located on the first gate insulating film, a second gate electrode located on the second gate insulating film, and the Forming a wiring located above or above the base insulating film;
And thinning or removing the second conductive film constituting the first gate electrode.

  In the semiconductor device manufactured by the method for manufacturing a semiconductor device, the second conductive film included in the second gate electrode and the wiring is thicker than the conductive film formed in the first gate electrode. The first conductive film has a tensile stress, and the second conductive film has a compressive stress.

  For this reason, the stress of the first gate electrode can be used as a tensile stress, and the tensile stress of the second gate electrode and the wiring can be reduced or can be a compressive stress. For this reason, the response speed of the thin film transistor having the first gate electrode is increased, and the stress applied to the substrate of the semiconductor device by the first and second gate electrodes and the wiring is reduced, or 0 GPa or substantially 0 GPa. can do.

Another method of manufacturing a semiconductor device according to the present invention includes a step of forming an island-shaped semiconductor layer on a base insulating film,
Forming a gate insulating film located on the semiconductor layer;
Forming a first conductive film having a compressive stress on or above the base insulating film and on the gate insulating film;
Forming a second conductive film having a tensile stress on the first conductive film;
Etching the first and second conductive films to form a wiring located on or above the base insulating film and a gate electrode located on the gate insulating film;
A step of thinning or removing the second conductive film constituting the wiring.

Another method of manufacturing a semiconductor device according to the present invention includes a step of forming an island-shaped semiconductor layer on a base insulating film,
Forming a gate insulating film located on the semiconductor layer;
Forming a first conductive film having a tension on or above the base insulating film and on the gate insulating film;
Forming a second conductive film having a compressive stress on the first conductive film;
Etching the first and second conductive films to form a wiring located on or above the base insulating film and a gate electrode located on the gate insulating film;
A step of thinning or removing the second conductive film constituting the gate electrode.

Another method of manufacturing a semiconductor device according to the present invention includes forming an island-shaped first semiconductor layer and an island-shaped second semiconductor layer on a base insulating film,
Forming a first gate insulating film located on the first semiconductor layer and a second gate insulating film located on the second semiconductor layer;
Forming a first conductive film having compressive stress on the first gate insulating film and the second gate insulating film;
Forming a second conductive film having a tensile stress on the first conductive film;
Thinning or removing the second conductive film located on the second gate insulating film than the second conductive film located on the first gate insulating film;
The first and second conductive films are etched to form a first gate electrode located on the first gate insulating film and a second gate electrode located on the second gate insulating film. The process to comprise.

Another method of manufacturing a semiconductor device according to the present invention includes forming an island-shaped first semiconductor layer and an island-shaped second semiconductor layer on a base insulating film,
Forming a first gate insulating film located on the first semiconductor layer and a second gate insulating film located on the second semiconductor layer;
Forming a first conductive film having a tensile stress on the first gate insulating film and the second gate insulating film;
Forming a second conductive film having a compressive stress on the first conductive film;
Thinning or removing the second conductive film located on the first gate insulating film than the second conductive film located on the second gate insulating film;
The first and second conductive films are etched to form a first gate electrode located on the first gate insulating film and a second gate electrode located on the second gate insulating film. The process to comprise.

Another method of manufacturing a semiconductor device according to the present invention includes forming an island-shaped first semiconductor layer and an island-shaped second semiconductor layer on a base insulating film,
Forming a first gate insulating film located on the first semiconductor layer and a second gate insulating film located on the second semiconductor layer;
Forming a first conductive film having a compressive stress on or above the base insulating film, on the first gate insulating film, and on the second gate insulating film;
Forming a second conductive film having a tensile stress on the first conductive film;
The second conductive film positioned on the second gate insulating film and the second conductive film positioned on or above the base insulating film are positioned on the first gate insulating film. Thinning or removing the second conductive film;
Etching the first and second conductive films to form a first gate electrode located on the first gate insulating film, a second gate electrode located on the second gate insulating film, and the Forming a wiring located above or above the base insulating film.

Another method of manufacturing a semiconductor device according to the present invention includes forming an island-shaped first semiconductor layer and an island-shaped second semiconductor layer on a base insulating film,
Forming a first gate insulating film located on the first semiconductor layer and a second gate insulating film located on the second semiconductor layer;
Forming a first conductive film having a tensile stress on or above the base insulating film, on the first gate insulating film, and on the second gate insulating film;
Forming a second conductive film having a compressive stress on the first conductive film;
The second conductive film positioned on the first gate insulating film, the second conductive film positioned on the second gate insulating film, and the above-described upper conductive film positioned on or above the base insulating film Thinning or removing each of the second conductive films;
Etching the first and second conductive films to form a first gate electrode located on the first gate insulating film, a second gate electrode located on the second gate insulating film, and the Forming a wiring located above or above the base insulating film.

Another method of manufacturing a semiconductor device according to the present invention includes a step of forming an island-shaped semiconductor layer on a base insulating film,
Forming a gate insulating film located on the semiconductor layer;
Forming a first conductive film having a compressive stress on or above the base insulating film and on the gate insulating film;
Forming a second conductive film having a tensile stress on the first conductive film;
Thinning or removing the second conductive film located on or above the base insulating film from the second conductive film located on the gate insulating film; and
Etching the first and second conductive films to form a wiring located above or above the base insulating film and a gate electrode located on the gate insulating film.

Another method of manufacturing a semiconductor device according to the present invention includes a step of forming an island-shaped semiconductor layer,
Forming a gate insulating film located on the semiconductor layer;
Forming a first conductive film having a tension on or above the base insulating film and on the gate insulating film;
Forming a second conductive film having a compressive stress on the first conductive film;
Making the second conductive film positioned on the gate insulating film thinner or removing the second conductive film positioned on or above the base insulating film;
Etching the first and second conductive films to form a wiring located above or above the base insulating film and a gate electrode located on the gate insulating film.

  In the semiconductor device manufacturing method, the first gate electrode is, for example, a gate electrode of an n-type transistor, and the second gate electrode is, for example, a gate electrode of a p-type transistor.

  Further, in the step of etching the first and second conductive films, the gate length of the first conductive film constituting the first gate electrode is set to the second length constituting the first gate electrode. The gate length of the first conductive film constituting the second gate electrode is longer than the gate length of the second conductive film constituting the second gate electrode. May be. In the step of etching the first and second conductive films, the gate length of the first conductive film constituting the gate electrode is set to be greater than the gate length of the second conductive film constituting the gate electrode. It may be longer.

  In these cases, when impurity regions are introduced to form impurity regions serving as the source and drain of the thin film transistor, a low-concentration impurity region adjacent to the impurity region can be formed in a self-aligned manner.

  Here, the gate length is the length of the gate electrode in the direction in which the drain current of the field effect thin film transistor flows, that is, the direction in which carriers move in the channel direction during transistor operation. In the gate electrode composed of two different conductive layers, the gate length can be defined for each layer. For example, in a gate electrode including a first conductive film and a second conductive film formed over the first conductive film, the gate length of the first conductive film is equal to that of the first conductive film. The gate length in the second conductive film is defined by the length of the second conductive film. The same applies hereinafter.

The first semiconductor device according to the present invention has a base insulating film,
An island-shaped first semiconductor layer formed on the base insulating film;
A first gate insulating film formed on the first semiconductor layer;
A first gate electrode composed of a first conductive film formed on the first gate insulating film and a second conductive film formed on the first conductive film;
A first thin film transistor comprising:
An island-shaped second semiconductor layer formed on the base insulating film;
A second gate insulating film formed on the second semiconductor layer;
A second gate electrode composed of a third conductive film formed on the second gate insulating film and a fourth conductive film formed on the third conductive film;
A second thin film transistor comprising:
A wiring composed of a fifth conductive film formed on or above the base insulating film and a sixth conductive film formed on the fifth conductive film;
Have
The first conductive film, the third conductive film, and the fifth conductive film have compressive stress,
The second conductive film, the fourth conductive film, and the sixth conductive film have tensile stress,
The film thickness of the fourth conductive film and the film thickness of the sixth conductive film are thinner than the film thickness of the second conductive film,
The first gate electrode has a tensile stress;
The second thin film transistor is a p-type thin film transistor,
The first thin film transistor is an n-type thin film transistor.

The second semiconductor device according to the present invention has a base insulating film,
An island-shaped first semiconductor layer formed on the base insulating film;
A first gate insulating film formed on the first semiconductor layer;
A first gate electrode composed of a first conductive film formed on the first gate insulating film and a second conductive film formed on the first conductive film;
A first thin film transistor comprising:
An island-shaped second semiconductor layer formed on the base insulating film;
A second gate insulating film formed on the second semiconductor layer;
A second gate electrode composed of a third conductive film formed on the second gate insulating film and a fourth conductive film formed on the third conductive film;
A second thin film transistor comprising:
A wiring composed of a fifth conductive film formed on or above the base insulating film and a sixth conductive film formed on the fifth conductive film;
Have
The first conductive film, the third conductive film, and the fifth conductive film have tensile stress,
The second conductive film, the fourth conductive film, and the sixth conductive film have compressive stress,
The film thickness of the fourth conductive film and the film thickness of the sixth conductive film are thicker than the film thickness of the second conductive film,
The first gate electrode has a tensile stress;
The second thin film transistor is a p-type thin film transistor,
The first thin film transistor is an n-type thin film transistor.

A third semiconductor device according to the present invention has a base insulating film,
An island-shaped first semiconductor layer formed on the base insulating film;
A first gate insulating film formed on the first semiconductor layer;
A first gate electrode composed of a first conductive film formed on the first gate insulating film and a second conductive film formed on the first conductive film;
A first thin film transistor comprising:
An island-shaped second semiconductor layer formed on the base insulating film;
A second gate insulating film formed on the second semiconductor layer;
A second gate electrode composed of a third conductive film formed on the second gate insulating film and a fourth conductive film formed on the third conductive film;
A second thin film transistor comprising:
Have
The first conductive film and the third conductive film have compressive stress,
The second conductive film and the fourth conductive film have a tensile stress,
The film thickness of the fourth conductive film is thinner than the film thickness of the second conductive film,
The first gate electrode has a tensile stress;
The second thin film transistor is a p-type thin film transistor,
The first thin film transistor is an n-type thin film transistor.

A fourth semiconductor device according to the present invention has a base insulating film,
An island-shaped first semiconductor layer formed on the base insulating film;
A first gate insulating film formed on the first semiconductor layer;
A first gate electrode composed of a first conductive film formed on the first gate insulating film and a second conductive film formed on the first conductive film;
A first thin film transistor comprising:
An island-shaped second semiconductor layer formed on the base insulating film;
A second gate insulating film formed on the second semiconductor layer;
A second gate electrode composed of a third conductive film formed on the second gate insulating film and a fourth conductive film formed on the third conductive film;
A second thin film transistor comprising:
Have
The first conductive film and the third conductive film have a tensile stress,
The second conductive film and the fourth conductive film have compressive stress,
The film thickness of the fourth conductive film is thicker than the film thickness of the second conductive film,
The first gate electrode has a tensile stress;
The second thin film transistor is a p-type thin film transistor,
The first thin film transistor is an n-type thin film transistor.

A fifth semiconductor device according to the present invention has a base insulating film,
An island-shaped semiconductor layer formed on the base insulating film;
A gate insulating film formed on the semiconductor layer;
A gate electrode composed of a first conductive film formed on the gate insulating film and a second conductive film formed on the first conductive film;
A thin film transistor comprising:
A wiring composed of a third conductive film formed on or above the base insulating film and a fourth conductive film formed on the third conductive film;
Have
The first conductive film and the third conductive film have compressive stress,
The second conductive film and the fourth conductive film have a tensile stress,
The film thickness of the fourth conductive film is thinner than the film thickness of the second conductive film,
The gate electrode has a tensile stress;
The thin film transistor is an n-type thin film transistor.

A sixth semiconductor device according to the present invention has a base insulating film,
An island-shaped semiconductor layer formed on the base insulating film;
A gate insulating film formed on the semiconductor layer;
A gate electrode composed of a first conductive film formed on the gate insulating film and a second conductive film formed on the first conductive film;
A thin film transistor comprising:
A wiring composed of a third conductive film formed on or above the base insulating film and a fourth conductive film formed on the third conductive film;
Have
The first conductive film and the third conductive film have a tensile stress,
The second conductive film and the fourth conductive film have compressive stress,
The film thickness of the fourth conductive film is thicker than the film thickness of the second conductive film,
The gate electrode has a tensile stress;
The thin film transistor is an n-type thin film transistor.

A seventh semiconductor device according to the present invention has a base insulating film,
An island-shaped first semiconductor layer formed on the base insulating film;
A first gate insulating film formed on the first semiconductor layer;
A first gate electrode composed of a first conductive film formed on the first gate insulating film and a second conductive film formed on the first conductive film;
A first thin film transistor comprising:
An island-shaped second semiconductor layer formed on the base insulating film;
A second gate insulating film formed on the second semiconductor layer;
A second gate electrode made of a third conductive film, formed on the second gate insulating film;
A second thin film transistor comprising:
A wiring composed of a fourth conductive film formed on or above the base insulating film;
Have
The first conductive film, the third conductive film, and the fourth conductive film have compressive stress,
The second conductive film has a tensile stress,
The first gate electrode has a tensile stress;
The second thin film transistor is a p-type thin film transistor,
The first thin film transistor is an n-type thin film transistor.

An eighth semiconductor device according to the present invention has a base insulating film,
An island-shaped first semiconductor layer formed on the base insulating film;
A first gate insulating film formed on the first semiconductor layer;
A first gate electrode composed of a first conductive film formed on the first gate insulating film;
A first thin film transistor comprising:
An island-shaped second semiconductor layer formed on the base insulating film;
A second gate insulating film formed on the second semiconductor layer;
A second gate electrode comprising: a second conductive film formed on the second gate insulating film; and a third conductive film formed on the second conductive film;
A second thin film transistor comprising:
A wiring composed of a fourth conductive film formed on or above the base insulating film and a fifth conductive film formed on the fourth conductive film;
Have
The first conductive film, the second conductive film, and the fourth conductive film have tensile stress,
The third conductive film and the fifth conductive film have compressive stress,
The second thin film transistor is a p-type thin film transistor,
The first thin film transistor is an n-type thin film transistor.

A ninth semiconductor device according to the present invention has a base insulating film,
An island-shaped first semiconductor layer formed on the base insulating film;
A first gate insulating film formed on the first semiconductor layer;
A first gate electrode composed of a first conductive film formed on the first gate insulating film and a second conductive film formed on the first conductive film;
A first thin film transistor comprising:
An island-shaped second semiconductor layer formed on the base insulating film;
A second gate insulating film formed on the second semiconductor layer;
A second gate electrode made of a third conductive film, formed on the second gate insulating film;
A second thin film transistor comprising:
Have
The first conductive film and the third conductive film have compressive stress,
Having a second conductive film tensile stress;
The first gate electrode has a tensile stress;
The second thin film transistor is a p-type thin film transistor,
The first thin film transistor is an n-type thin film transistor.

A tenth semiconductor device according to the present invention has a base insulating film,
An island-shaped first semiconductor layer formed on the base insulating film;
A first gate insulating film formed on the first semiconductor layer;
A first gate electrode composed of a first conductive film formed on the first gate insulating film;
A first thin film transistor comprising:
An island-shaped second semiconductor layer formed on the base insulating film;
A second gate insulating film formed on the second semiconductor layer;
A second gate electrode comprising: a second conductive film formed on the second gate insulating film; and a third conductive film formed on the second conductive film;
A second thin film transistor comprising:
Have
The first conductive film and the second conductive film have a tensile stress,
The third conductive film has a compressive stress,
The second thin film transistor is a p-type thin film transistor,
The first thin film transistor is an n-type thin film transistor.

An eleventh semiconductor device according to the present invention has a base insulating film,
An island-shaped semiconductor layer formed on the base insulating film;
A gate insulating film formed on the semiconductor layer;
A gate electrode composed of a first conductive film formed on the gate insulating film and a second conductive film formed on the first conductive film;
A thin film transistor comprising:
A wiring composed of a third conductive film formed on or above the base insulating film;
Have
The first conductive film and the third conductive film have compressive stress,
The second conductive film has a tensile stress,
The gate electrode has a tensile stress;
The thin film transistor is an n-type thin film transistor.

A twelfth semiconductor device according to the present invention has a base insulating film,
An island-shaped semiconductor layer formed on the base insulating film;
A gate insulating film formed on the semiconductor layer;
A gate electrode made of a first conductive film formed on the gate insulating film;
A thin film transistor comprising:
A wiring composed of a second conductive film formed on or above the base insulating film and a third conductive film formed on the second conductive film;
Have
The first conductive film and the second conductive film have a tensile stress,
The third conductive film has a compressive stress,
The thin film transistor is an n-type thin film transistor.

  In the first, second, third, fourth, eighth, or tenth semiconductor device, the stress of the second gate electrode is a tensile having a value smaller than the tensile stress of the first gate electrode. The stress, compressive stress, 0 GPa, or approximately 0 GPa is preferable.

  In the first, second, or eighth semiconductor device, the wiring stress is preferably a tensile stress having a value smaller than the tensile stress of the first gate electrode. In the fifth, sixth, or twelfth semiconductor device, the wiring stress may be a tensile stress having a value smaller than a tensile stress of the gate electrode.

  In the first, second, fifth, sixth, eighth, or twelfth semiconductor device, the stress of the wiring may be compressive stress, 0 GPa, or approximately 0 GPa.

  In the first, second, or eighth semiconductor device, the stress of the second gate electrode and the stress of the wiring are tensile stress and compressive stress having values smaller than the tensile stress of the first gate electrode. , 0 GPa, or approximately 0 GPa.

In any one of the first to third semiconductor devices, a gate length of the third conductive film constituting the second gate electrode is greater than a gate length of the fourth conductive film. Is also preferably long.
In this semiconductor device or the first, second, third, fourth, seventh, or ninth semiconductor device, the gate length of the first conductive film that constitutes the first gate electrode Is preferably longer than the gate length of the second conductive film.

  In the fifth, sixth, or eleventh semiconductor device, the gate length of the first conductive film constituting the gate electrode is longer than the gate length of the second conductive film. Is preferred.

  In the eighth, tenth, or twelfth semiconductor device, the gate length of the second conductive film constituting the second gate electrode is longer than the gate length of the third conductive film. Is also preferably long.

  In each of the semiconductor devices described above, it is desirable that the orientation ratio in the crystal orientation of the semiconductor layer is the highest in the (100) direction. The semiconductor layer is preferably silicon, germanium, or silicon germanium.

  An electronic apparatus according to the present invention includes the above-described semiconductor device.

  According to the present invention, by applying a tensile stress to the semiconductor layer of the n-type thin film transistor by applying a tensile stress to the gate electrode of the n-type thin film transistor, the mobility of the n-type thin film transistor is improved and the response speed of the thin film transistor is increased. The stress applied to the substrate of the semiconductor device by the gate electrode and the wiring of the p-type thin film transistor can be reduced.

  In particular, the higher the (100) orientation ratio in the crystal orientation of the semiconductor layer of the n-type thin film transistor, the higher the mobility of the n-type thin film transistor.

  In addition, the above-described effects can be obtained only by changing the gate electrode film formation conditions and adding a stress adjustment etching process to an existing process. For this reason, a large increase in the number of processes is not required.

BEST MODE FOR CARRYING OUT THE INVENTION

(First embodiment)
The method for manufacturing the semiconductor device according to the first embodiment will be described below using the cross-sectional views shown in FIGS. This embodiment is a method of forming an n-type thin film transistor, a p-type thin film transistor, and a wiring located in the same layer as the gate electrode of each thin film transistor on the same substrate. The semiconductor device manufactured according to the present embodiment is, for example, an active matrix substrate.

  First, as illustrated in FIG. 1A, a base insulating film 101 is formed on a substrate 100.

  The substrate 100 is a glass substrate, a quartz substrate, a substrate formed of an insulator such as alumina, a plastic substrate having heat resistance that can withstand a processing temperature in a later process, a silicon substrate, or a metal plate. The substrate 100 may be a substrate in which an insulating film such as silicon oxide or silicon nitride is formed on the surface of a metal substrate such as stainless steel or a semiconductor substrate. When a plastic substrate is used as the substrate 100, a substrate having a relatively high glass transition point such as PC (polycarbonate), PES (polyethersulfone), PET (polyethylene terephthalate), or PEN (polyethylene naphthalate) should be used. preferable.

  The base insulating film 101 is a film that prevents impurities from diffusing from the substrate 100. The base insulating film 101 is a film in which a silicon oxide film (SiOx) is stacked on, for example, a silicon nitride (SiNx) film, but other insulators (for example, silicon oxynitride (SiOxNy) (x> y) or silicon nitride oxide) (SiNxOy) (x> y)). Note that a nitride film may be formed on the surface of the base insulating film 101 by performing nitriding treatment with high-density plasma on the surface of the base insulating film 101 including a silicon oxide film, a silicon oxynitride film, or the like. The thickness of the base insulating film 101 is, for example, 100 nm.

  Next, an amorphous semiconductor film (for example, an amorphous silicon film) 102 d is formed over the base insulating film 101.

  Next, as illustrated in FIG. 1B, the amorphous semiconductor film 102 d is crystallized to form the crystalline semiconductor film 102. In the case where the crystalline semiconductor film 102 is a crystalline silicon film (for example, a polysilicon film), it is preferable that the ratio of crystal grains whose crystal orientation is (100) is high.

  As a method for crystallizing the amorphous semiconductor film 102d, a method of irradiating laser light, an element for promoting crystallization (for example, a metal element such as nickel) is added to the amorphous semiconductor film 102d, and then heated. There is a method of crystallizing by this, or a method of adding an element for promoting crystallization of a semiconductor film to the amorphous semiconductor film 102d and heating to crystallize, and then irradiating a laser beam. Of course, there is a method of thermally crystallizing the amorphous semiconductor film 102d without using the above elements, but the substrate is limited to a substrate that can withstand high temperatures such as a quartz substrate or a silicon wafer.

In the case of using laser irradiation, a continuous wave laser beam (CW laser beam) or a pulsed laser beam (pulse laser beam) can be used. Laser beams that can be used here are gas lasers such as Ar laser, Kr laser, and excimer laser, single crystal YAG, YVO ₄ , forsterite (Mg ₂ SiO ₄ ), YAlO _3, GdVO ₄ , or polycrystalline ( (Ceramics) YAG, Y ₂ O ₃ , YVO ₄ , YAlO ₃ , GdVO ₄ with one or more of Nd, Yb, Cr, Ti, Ho, Er, Tm, Ta added as dopants Lasers oscillated from one or more of laser, glass laser, ruby laser, alexandrite laser, Ti: sapphire laser, copper vapor laser or gold vapor laser as a medium can be used. By irradiating the fundamental wave of such a laser beam and the second to fourth harmonics of these fundamental waves, a crystal having a large grain size can be obtained. For example, the second harmonic (532 nm) or the third harmonic (355 nm) of an Nd: YVO ₄ laser (fundamental wave 1064 nm) can be used. Energy density of the laser, 0.01 to 100 MW / cm ² about (preferably 0.1 to 10 MW / cm ²⁾ is required. Moreover, the scanning speed at the time of irradiation is about 10-2000 cm / sec.

Note that single crystal YAG, YVO ₄ , forsterite (Mg ₂ SiO ₄ ), YAlO ₃ , GdVO ₄ , or polycrystalline (ceramic) YAG, Y ₂ O ₃ , YVO ₄ , YAlO ₃ , GdVO ₄ , dopants Nd, Yb, Cr, Ti, Ho, Er, Tm, Ta as a medium, a laser, Ar ion laser, or Ti: sapphire laser with one or more added as a medium should be continuously oscillated It is also possible to perform pulse oscillation at an oscillation frequency of 10 MHz or more by performing Q switch operation, mode synchronization, or the like. When a laser beam is oscillated at an oscillation frequency of 10 MHz or higher, the semiconductor film is irradiated with the next pulse during the period from when the semiconductor film is melted by the laser to solidification. Therefore, unlike the case of using a pulse laser having a low oscillation frequency, the solid-liquid interface can be continuously moved in the semiconductor film, so that crystal grains continuously grown in the scanning direction can be obtained.

  When ceramic (polycrystal) is used as the medium, it is possible to form the medium in a free shape in a short time and at low cost. When a single crystal is used, a cylindrical medium having a diameter of several millimeters and a length of several tens of millimeters is usually used. However, when ceramic is used, a larger one can be made.

  Since the concentration of dopants such as Nd and Yb in the medium that directly contributes to light emission cannot be changed greatly regardless of whether it is single crystal or polycrystal, there is a certain limit to the improvement in laser output by increasing the concentration. However, in the case of ceramic, since the size of the medium can be remarkably increased as compared with the single crystal, a great improvement in output can be expected.

  Further, in the case of ceramic, a medium having a parallelepiped shape or a rectangular parallelepiped shape can be easily formed. When a medium having such a shape is used to cause oscillation light to travel in a zigzag manner inside the medium, the oscillation optical path can be made longer. As a result, amplification is increased and oscillation can be performed with high output. Further, since the laser beam emitted from the medium having such a shape has a quadrangular cross-sectional shape at the time of emission, it is advantageous for shaping into a linear beam as compared with a round beam. By shaping the emitted laser beam using an optical system, a linear beam having a short length of 1 mm or less and a long length of several mm to several m can be easily obtained. . Further, by irradiating the medium with the excitation light uniformly, the linear beam has a uniform energy distribution in the longitudinal direction.

  By irradiating the semiconductor film with this linear beam, the entire surface of the semiconductor film can be annealed more uniformly. When uniform annealing is required up to both ends of the linear beam, it is necessary to arrange a slit at both ends to shield the energy attenuating portion.

  When a semiconductor film is annealed using a linear beam having a uniform intensity obtained in this manner and an electronic device is manufactured using this semiconductor film, the characteristics of the electronic device become good and uniform.

  Further, as a method for crystallizing the amorphous semiconductor film 102d using an element that promotes crystallization, a technique described in JP-A-8-78329 can be used. The technology described in this publication adds a metal element that promotes crystallization to an amorphous semiconductor film (for example, an amorphous silicon film) and heat-treats the amorphous semiconductor film from the added region as a starting point. It is to make it.

  In this method, the amorphous semiconductor film 102d can be crystallized by irradiation with strong light instead of heat treatment. In this case, any one of infrared light, visible light, and ultraviolet light or a combination thereof can be used. Typically, a halogen lamp, a metal halide lamp, a xenon arc lamp, a carbon arc lamp, a high pressure Light emitted from a sodium lamp or a high-pressure mercury lamp is used. The lamp light source is turned on for 1 to 60 seconds, preferably 30 to 60 seconds, and this is repeated 1 to 10 times, preferably 2 to 6 times. The emission intensity of the lamp light source is arbitrary, but the semiconductor film is instantaneously heated to about 600 to 1000 ° C. Note that if necessary, heat treatment for releasing hydrogen contained in the amorphous semiconductor film 102d may be performed before irradiation with strong light. Alternatively, the amorphous semiconductor film 102d may be crystallized by performing both heat treatment and strong light irradiation.

  In order to increase the crystallization rate of the crystalline semiconductor film (the ratio of the crystal component in the entire volume of the film) after the heat treatment and repair defects remaining in the crystal grains, the crystalline semiconductor film 102 is exposed to the atmosphere. Alternatively, irradiation may be performed in an oxygen atmosphere. As the laser light, those described above can be used.

Note that it is necessary to remove the added element from the crystalline semiconductor film 102. An example of the method will be described below.
First, by treating the surface of the crystalline semiconductor film 102 with an aqueous solution containing ozone (typically ozone water), a barrier layer made of an oxide film (called chemical oxide) is formed on the surface of the crystalline semiconductor film 102 to 1 nm to 10 nm. The thickness is formed. The barrier layer functions as an etching stopper when only the gettering layer is selectively removed in a later step.

  Next, a gettering layer containing a rare gas element is formed over the barrier layer. Here, a semiconductor film containing a rare gas element is formed as a gettering layer by a CVD method or a sputtering method. When forming the gettering layer, the sputtering conditions are adjusted as appropriate so that a rare gas element is added to the gettering layer. As the rare gas element, one or more selected from helium (He), neon (Ne), argon (Ar), krypton (Kr), and xenon (Xe) are used.

Note that when a source gas containing phosphorus, which is an impurity element, is used, or when a gettering layer is formed using a target containing phosphorus, gettering is performed using the Coulomb force of phosphorus in addition to gettering by a rare gas element. It can be performed.
Further, during gettering, a metal element (for example, nickel) tends to move to a region having a high oxygen concentration, so that the oxygen concentration contained in the gettering layer is, for example, 5 × 10 ¹⁸ cm ⁻³ or more. Is desirable.

  Next, the crystalline semiconductor film 102, the barrier layer, and the gettering layer are subjected to heat treatment (for example, heat treatment or treatment for irradiating intense light) to perform gettering of a metal element (for example, nickel). A metal element is reduced in concentration or removed.

  Next, a known etching method is performed using the barrier layer as an etching stopper, and only the gettering layer is selectively removed. Thereafter, the barrier layer made of an oxide film is removed by, for example, an etchant containing hydrofluoric acid.

  Here, impurity ions may be doped in consideration of threshold characteristics of a manufactured TFT.

  Next, as shown in FIG. 1C, a photoresist film (not shown) is applied on the crystalline semiconductor film 102, and this photoresist film is exposed and developed. Thereby, a resist pattern is formed on the crystalline semiconductor film 102. Next, the crystalline semiconductor film 102 is etched using this resist pattern as a mask. Thus, island-shaped crystalline semiconductor layers 102 a and 102 b are formed over the base insulating film 101.

  Next, as shown in FIG. 1D, after the surfaces of the crystalline semiconductor layers 102a and 102b are cleaned with a hydrofluoric acid-containing etchant or the like, the gate insulating film 103a located on the crystalline semiconductor layer 102a, and the crystalline A gate insulating film 103b located over the semiconductor layer 102b is formed by a CVD method. The gate insulating film 103a is a gate insulating film of an n-type thin film transistor, and the gate insulating film 103b is a gate insulating film of a p-type thin film transistor. The gate insulating films 103a and 103b have a thickness of 10 nm to 110 nm and are, for example, silicon oxide films, but other insulating films (for example, a silicon nitride film, a silicon oxynitride film, a silicon nitride oxide film, etc.). It may be formed. Moreover, you may form by PVD method. The gate insulating films 103a and 103b may be a single layer or a laminated film. Note that the insulating film 103 is also formed over the base insulating film 101.

  Next, as illustrated in FIG. 1E, a first conductive film 104 is formed on each of the gate insulating films 103 a and 103 b and the insulating film 103 by a sputtering method, and is further positioned on the first conductive film 104. The second conductive film 105 is formed by a sputtering method. The first conductive film 104 is a TaN film, for example, and has a compressive stress. The second conductive film 105 is a W film, for example, and has a tensile stress. The film thicknesses of the first conductive film 104 and the second conductive film 105 are set so that these laminated films have tensile stress as a whole. For example, the thickness of the first conductive film 104 is 30 nm, and the thickness of the second conductive film 105 is 570 nm.

  Note that the direction and magnitude of stress in the first conductive film 104 and the second conductive film 105 can be controlled by pressure during film formation. For example, the first conductive film 104 has compressive stress when the pressure during film formation is 0.3 Pa or more and 0.4 Pa or less. Further, the second conductive film 105 has tensile stress when the pressure during film formation is about 2.0 Pa.

  Next, as shown in FIG. 2A, a photoresist film (not shown) is applied on the second conductive film 105, and this photoresist film is exposed and developed. As a result, a resist pattern is formed on the second conductive film 105. Next, the second conductive film 105 is etched using this photoresist film as a mask. As a result, the second conductive film 105 becomes thin except for a portion located above the gate insulating film 103a, and the film thickness becomes, for example, 370 nm. Accordingly, the tensile stress of the stacked film of the second conductive film 105 and the first conductive film 104 is reduced or becomes 0 GPa or approximately 0 GPa except for a portion located above the gate insulating film 103a. . Note that by adjusting the thickness of the second conductive film 105, the stress of the stacked film can be changed to a compressive stress except for a portion located above the gate insulating film 103a.

  FIG. 4 is a graph showing how the stress of the stacked film of the first conductive film 104 and the second conductive film 105 changes depending on the thickness of the second conductive film 105. In this graph, the second conductive film 105 is a W film, and two types of samples having different film formation conditions for the second conductive film 105 (different input values in the sputtering method (PVD method)) are measured. . As shown in this graph, in the sample with a deposition power of 3 kW, the stacked film of the first conductive film 104 and the second conductive film 105 is provided by changing the thickness of the second conductive film 105. The stress can be varied from compressive stress to tensile stress.

Thereafter, the resist pattern is removed.
Next, as shown in FIG. 2B, a photoresist film (not shown) is applied again on the second conductive film 105, and this photoresist film is exposed and developed. As a result, a resist pattern is formed again on the second conductive film 105. Next, the second conductive film 105 is etched using this photoresist film as a mask. Etching may be performed by either dry etching or wet etching. Accordingly, the second conductive film 105 is patterned, and the second conductive film 105a located above the gate insulating film 103a, the second conductive film 105b located above the gate insulating film 103b, and the insulating film 103 are formed. A second conductive film 105c located at is formed. Thereafter, the resist pattern is removed.

  Next, a photoresist film (not shown) is applied on each of the second conductive films 105a to 105c and on the first conductive film 104, and this photoresist film is exposed and developed. As a result, a resist pattern is formed on each of the second conductive films 105 a to 105 c and on the first conductive film 104. Next, the first conductive film 104 is etched using this photoresist film as a mask. Etching may be performed by either dry etching or wet etching. As a result, the first conductive film 104 is patterned, and the first insulating film 104a located under the second conductive film 105a, the first insulating film 104b located under the second conductive film 105b, and A first insulating film 104c located under the second conductive film 105c is formed. The width of each of the first conductive films 104a to 104c is wider than the width of each of the second conductive films 105a to 105c. That is, the gate length of the first conductive film 104a is longer than the gate length of the second conductive film 105a, and the gate length of the first conductive film 104b is longer than the gate length of the second conductive film 105b.

In this manner, the gate electrode 106a in which the first conductive film 104a and the second conductive film 105a are stacked in this order, the gate electrode 106b in which the first conductive film 104b and the second conductive film 105b are stacked in this order, and A wiring 106c in which the first conductive film 104c and the second conductive film 105c are stacked in this order is formed. The gate electrode 106a is a gate electrode of an n-type thin film transistor, and the gate electrode 106b is a gate electrode of a p-type thin film transistor. By the process shown in FIG. 2A, can the tensile stress of the stacked film of the second conductive film 105 and the first conductive film 104 be reduced except for a portion located above the gate insulating film 103a? Or 0 GPa or approximately 0 GPa. Therefore, the tensile stress of the gate electrode 106b and the wiring 106c is smaller than the tensile stress of the gate electrode 106a, or 0 GPa or approximately 0 GPa.
Thereafter, the resist pattern is removed.

  Thereafter, as shown in FIG. 2C, a photoresist film 120 is formed on the entire surface including the upper part of the crystalline semiconductor layer 102b, and the photoresist film 120 is exposed and developed. Thereby, the photoresist film 120 is removed except for a portion located above the crystalline semiconductor layer 102b.

  Next, an n-type impurity (eg, P or As) is implanted into the crystalline semiconductor layer 102a using the photoresist film 120 and the gate electrode 106a as a mask. As an impurity implantation method, an ion implantation method, a plasma doping method, or an ion shower doping method can be used. As a result, two low-concentration impurity regions 107a are formed in a self-aligned manner in a region of the crystalline semiconductor layer 102a that is covered only by the first conductive film 104a, and the first and second conductive films 104a are formed. , 105a, two n-type impurity regions 108a are formed in a region not covered by any of them. The two impurity regions 108a function as the source and drain of the n-type thin film transistor, respectively.

  Thereafter, as shown in FIG. 2D, the photoresist film 120 is removed. Next, a photoresist film 121 is formed over the entire surface including the upper part of the crystalline semiconductor layer 102a, and the photoresist film 121 is exposed and developed. Thereby, the photoresist film 121 is removed except for a portion located above the crystalline semiconductor layer 102a.

  Next, a p-type impurity (for example, B) is implanted into the crystalline semiconductor layer 102b using the photoresist film 121 and the gate electrode 106b as a mask. As an impurity implantation method, an ion implantation method, a plasma doping method, or an ion shower doping method can be used. As a result, two low-concentration impurity regions 107b are formed in a self-aligned manner in a region of the crystalline semiconductor layer 102b that is covered only by the first conductive film 104b, and the first and second conductive films 104b are formed. , 105b, two p-type impurity regions 108b are formed in the region that is not covered by any of them. The two impurity regions 108a function as the source and drain of the p-type thin film transistor, respectively.

  Thereafter, as shown in FIG. 2E, the photoresist film 121 is removed. In this manner, an n-type thin film transistor, a p-type thin film transistor, and a wiring 106c are formed over the substrate 100.

  Next, as illustrated in FIG. 3A, the insulating film 109 is formed over the entire surface including the n-type thin film transistor, the p-type thin film transistor, and the wiring 106 c, and the interlayer insulating film 110 is further formed over the insulating film 109. . The insulating film 109 is a silicon oxide film or a silicon oxynitride film, and the interlayer insulating film 110 is an inorganic film such as a silicon oxide film, or an organic film such as acrylic or polyimide.

  Next, as shown in FIG. 3B, a photoresist film (not shown) is formed on the interlayer insulating film 110, and this photoresist film is exposed and developed. Thereby, a resist pattern is formed on the interlayer insulating film 110. Next, the interlayer insulating film 110 and the insulating film 109 are etched using this resist pattern as a mask. Thus, connection holes 110a, 110b, and 110c are formed in the interlayer insulating film 110 and the insulating film 109. The connection hole 110a is formed on each of the two impurity regions 108a, and the connection hole 110b is formed on each of the two impurity regions 108b. The connection hole 110c is formed on the wiring 106c. Thereafter, the resist pattern is removed.

  Next, a conductive film 111 is formed in each of the connection holes 110 a to 110 c and on the interlayer insulating film 110. The conductive film 111 is formed of an element washed from Al, Ti, Ag, Cu, or Mo, or an alloy material or a chemical material containing these elements as main components. The conductive film 111 may be a single layer film or a laminated film. The conductive film 111 may be a light-transmitting film (for example, ITO).

  Next, as shown in FIG. 3C, a photoresist film (not shown) is applied on the conductive film 111, and this photoresist film is exposed and developed. Thereby, a resist pattern is formed on the conductive film 111. Next, the conductive film 111 is etched using this resist pattern as a mask. As a result, the conductive film 111 is patterned to form two wirings 111a, two wirings 111b, and a wiring 111c. The wiring 111a is partially connected to the impurity region 108a by being embedded in the connection hole 110a, and the wiring 111b is connected to the impurity region 108b by being partially embedded in the connection hole 110b. A part of the wiring 111c is connected to the wiring 106c by being embedded in the connection hole 110b. Thereafter, the resist pattern is removed.

  As described above, according to the first embodiment, each of the gate electrode 106a of the n-type thin film transistor, the gate electrode 106b of the p-type thin film transistor, and the wiring 106c in the same layer as the gate electrodes 106a and 106b has the first conductivity having compressive stress. Each of the films 104a, 104b, and 104c has a structure in which the second conductive films 105a, 105b, and 105c having tensile stress are stacked. The second conductive films 105b and 105c are thinner than the second conductive film 105a. Therefore, the stress of the gate electrode 106a can be used as tensile stress, and the stress of the gate electrode 106b and the wiring 106c can be reduced, or 0 GPa or approximately 0 GPa.

  Therefore, compressive stress can be applied to the crystalline semiconductor layer 102a which becomes the channel region of the n-type thin film transistor, and the response speed of the n-type thin film transistor can be increased. In the case where the crystalline semiconductor film 102a is a polysilicon film, this effect becomes more significant as the ratio of crystal grains having a crystal orientation of (100) is higher. In addition, since the stress of the gate electrode 106b and the wiring 106c of the p-type thin film transistor is small, or 0 GPa or approximately 0 GPa, the stress applied to the substrate 100 by the gate electrodes 106a and 106b and the wiring 106c should be reduced as compared with the conventional case. Can do.

  Note that when the gate electrode 106b and the wiring 106c of the p-type thin film transistor have compressive stress, the stress applied to the substrate 100 by the gate electrodes 106a and 106b and the wiring 106c can be 0 GPa or approximately 0 GPa.

  Further, a single crystal semiconductor film (eg, a single crystal silicon film) may be formed instead of the crystalline semiconductor film 102. In the case of a single crystal silicon film, the crystal orientation is preferably (100).

(Second Embodiment)
Each drawing in FIG. 5 is a cross-sectional view for explaining the method for manufacturing a semiconductor device according to the second embodiment. This embodiment is different from the first embodiment in the timing of thinning the second conductive film constituting the gate electrode 106b and the wiring 106c. Hereinafter, the same components as those of the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  First, as shown in FIG. 5A, a base insulating film 101 is formed on a substrate 100, and crystalline semiconductor layers 102a and 102b, gate insulating films 103a and 103b, an insulating film 103, first and second films are formed. Conductive films 104 and 105 are formed. These forming methods are the same as those in the first embodiment.

  Next, as shown in FIG. 5B, a photoresist film (not shown) is applied on the second conductive film 105, and this photoresist film is exposed and developed. As a result, a resist pattern is formed on the second conductive film 105. Next, the first and second conductive films 104 and 105 are etched using this resist pattern as a mask. As a result, the first and second conductive films 104 and 105 are patterned to form gate electrodes 106a and 106b and a wiring 106c.

The etching rate for forming the gate electrodes 106 a and 106 b and the wiring 106 c is higher for the second conductive film 105 than for the first conductive film 104. Therefore, the width of each of the second conductive films 105a to 105c is narrower than the width of each of the first conductive films 104a to 104c.
Thereafter, the resist pattern is removed.

Next, as shown in FIG. 5C, a photoresist film (not shown) is applied on the entire surface including the gate electrodes 106a and 106b and the wiring 106c, and this photoresist film is exposed and developed. As a result, the photoresist film is patterned, and the photoresist film located on each of the gate electrode 106b and the wiring 106c is removed. Next, by performing etching using this photoresist film as a mask, the second conductive film 105b included in the gate electrode 106b and the second conductive film 105c included in the wiring 106c are thinned.
Thereafter, the photoresist film is removed.

  Next, as shown in FIG. 5D, the low concentration impurity regions 107a and 107b, the impurity regions 108a and 108b, the insulating film 109, the interlayer insulating film 110, the connection holes 110a, 110b, and 110c, and the wirings 111a, 111b, and 111c. Form. These forming methods are the same as those in the first embodiment.

  As described above, also in the second embodiment, the same effect as that in the first embodiment can be obtained.

(Third embodiment)
6 and 7 are cross-sectional views for explaining a method for manufacturing a semiconductor device according to the third embodiment. This embodiment is different from the second embodiment in the timing of thinning the second conductive films 105b and 105c included in the gate electrode 106b and the wiring 106c. Hereinafter, the same components as those of the second embodiment are denoted by the same reference numerals, and description thereof is omitted.

  First, as shown in FIG. 6A, a base insulating film 101 is formed on a substrate 100, and crystalline semiconductor layers 102a and 102b, gate insulating films 103a and 103b, an insulating film 103, gate electrodes 106a and 106b, Then, the wiring 106c is formed. These forming methods are the same as those in the first embodiment.

  Next, as illustrated in FIG. 6B, only the upper portion of the crystalline semiconductor layer 102 b is covered with a photoresist film 120. Next, n-type impurities are implanted into the crystalline semiconductor layer 102a using the photoresist film 120 and the gate electrode 106a as a mask. Thereby, the low concentration impurity region 107a and the impurity region 108a are formed.

  Thereafter, as shown in FIG. 6C, the photoresist film 120 is removed. Next, the second conductive film 105b included in the gate electrode 106b and the second conductive film 105c included in the wiring 106c are thinned. This method is the same as in the second embodiment.

  Next, as shown in FIG. 7A, only the upper part of the crystalline semiconductor layer 102 a is covered with a photoresist film 121. Next, p-type impurities are implanted into the crystalline semiconductor layer 102b using the photoresist film 121 and the gate electrode 106b as a mask. Thereby, the low concentration impurity region 107b and the impurity region 108b are formed.

  Thereafter, as shown in FIG. 7B, the photoresist film 121 is removed.

  Next, as shown in FIG. 7C, an insulating film 109, an interlayer insulating film 110, connection holes 110a, 110b, and 110c, and wirings 111a, 111b, and 111c are formed. These forming methods are the same as those in the first embodiment.

  As described above, also in the third embodiment, the same effect as that in the first embodiment can be obtained.

(Fourth embodiment)
8 and 9 are cross-sectional views for explaining the method for manufacturing a semiconductor device according to the fourth embodiment. This embodiment is different from the third embodiment in the timing of thinning the second conductive films 105b and 105c included in the gate electrode 106b and the wiring 106c. Hereinafter, the same components as those of the third embodiment are denoted by the same reference numerals, and description thereof is omitted.

  First, as shown in FIG. 8A, a base insulating film 101 is formed on a substrate 100, and crystalline semiconductor layers 102a and 102b, gate insulating films 103a and 103b, an insulating film 103, gate electrodes 106a and 106b, Then, the wiring 106c is formed. These forming methods are the same as those in the third embodiment.

  Next, as illustrated in FIG. 8B, only the upper portion of the crystalline semiconductor layer 102 b is covered with a photoresist film 120. Next, n-type impurities are implanted into the crystalline semiconductor layer 102a using the photoresist film 120 and the gate electrode 106a as a mask. Thereby, the low concentration impurity region 107a and the impurity region 108a are formed.

  Thereafter, as shown in FIG. 8C, the photoresist film 120 is removed. Next, only the upper part of the crystalline semiconductor layer 102 a is covered with the photoresist film 121. Next, p-type impurities are implanted into the crystalline semiconductor layer 102b using the photoresist film 121 and the gate electrode 106b as a mask. Thereby, the low concentration impurity region 107b and the impurity region 108b are formed.

  Thereafter, the photoresist film 121 is removed as shown in FIG.

  Next, as illustrated in FIG. 9B, the second conductive film 105b included in the gate electrode 106b and the second conductive film 105c included in the wiring 106c are thinned. This method is the same as in the third embodiment.

  Next, as shown in FIG. 9C, an insulating film 109, an interlayer insulating film 110, connection holes 110a, 110b, and 110c, and wirings 111a, 111b, and 111c are formed. These forming methods are the same as those in the third embodiment.

  As described above, also in the fourth embodiment, the same effect as that in the first embodiment can be obtained.

(Fifth embodiment)
Each drawing in FIG. 10 is a cross-sectional view for explaining the method for manufacturing a semiconductor device according to the fifth embodiment. The semiconductor device manufactured by this embodiment is the same as that of the fourth embodiment except for the configuration of the gate electrode 106b and the wiring 106c. Hereinafter, the same components as those in the fourth embodiment are denoted by the same reference numerals, and description thereof is omitted.

  First, as shown in FIG. 10A, a base insulating film 101 is formed on a substrate 100, and crystalline semiconductor layers 102a and 102b, gate insulating films 103a and 103b, an insulating film 103, gate electrodes 106a and 106b, Wiring 106c, low-concentration impurity regions 107a and 107b, and impurity regions 108a and 108b are formed. These forming methods are the same as those in the fourth embodiment.

  Next, as illustrated in FIG. 10B, the second conductive film 105b included in the gate electrode 106b and the second conductive film 105c included in the wiring 106c are removed. This method is the same as the method of thinning the second conductive films 105b and 105c in the fourth embodiment except that the etching conditions change (for example, the etching time becomes long).

  Next, as shown in FIG. 10C, an insulating film 109, an interlayer insulating film 110, connection holes 110a, 110b, and 110c, and wirings 111a, 111b, and 111c are formed. These forming methods are the same as those in the fourth embodiment.

  As described above, according to the fifth embodiment, the gate electrode 106a of the n-type thin film transistor has a structure in which the second conductive film 105a having tensile stress is stacked on the first conductive film 104a having compressive stress. The gate electrode 106a has a tensile stress as a whole. On the other hand, the gate electrode 106b of the p-type thin film transistor and the wiring 106c in the same layer as the gate electrodes 106a and 106b are each composed of only the first conductive films 104b and 104c having compressive stress. Therefore, the gate electrode 106b and the wiring 106c have a compressive stress.

  Therefore, by adjusting the compressive stress of the first conductive films 104b and 104c, the stress applied to the substrate 100 by the gate electrodes 106a and 106b and the wiring 106c is reduced as compared with the conventional case, or 0 GPa or approximately 0 GPa. be able to. In addition, when the second conductive films 105b and 105c are removed, the first conductive films 104b and 104c can be used as etching stoppers, so that in-plane variation of the gate electrode 106b and the wiring 106c can be suppressed. .

  Note that in the method described in any of the first to third embodiments, the second conductive film 105b included in the gate electrode 106b and the first wiring 106c included in the wiring 106c can be obtained by changing etching conditions (for example, etching time becomes long). Each of the two conductive films 105c may be removed.

(Sixth embodiment)
11 and 12 are cross-sectional views for explaining a method for manufacturing a semiconductor device according to the sixth embodiment of the present invention. In the semiconductor device manufactured according to the present embodiment, the first conductive films 104a, 104b, and 104c have tensile stress, and the second conductive films 105a, 105b, and 105c have compressive stress. This is different from the first embodiment. Hereinafter, the same components as those in the first embodiment are denoted by the same reference numerals, and description thereof is omitted.

  First, as shown in FIG. 11A, a base insulating film 101 is formed on a substrate 100, and crystalline semiconductor layers 102a and 102b, gate insulating films 103a and 103b, an insulating film 103, a first conductive film 104, Then, a second conductive film 105 is formed. In the present embodiment, the first conductive film 104 has a tensile stress, and the second conductive film 105 has a compressive stress. Whether the first and second conductive films 104 and 105 have a compressive stress or a tensile stress can be determined by the formation conditions of the first and second conductive films 104 and 105. Note that the tensile stress of the second conductive film 105 is offset with the compressive stress of the first conductive film 104, and the stress is reduced as the stacked film of the first and second conductive films 104 and 105, or 0 GPa. Or almost 0GPa

  Next, as illustrated in FIG. 11B, the portion of the second conductive film 105 located above the crystalline semiconductor layer 1002a is thinned. The method for thinning the second conductive film 105 is the same as in the first embodiment.

  Next, as shown in FIG. 11C, the first and second conductive films 104 and 105 are patterned to form gate electrodes 106a and 106b and a wiring 106c. These forming methods are the same as those in the first embodiment. Since the second conductive film 105a forming the gate electrode 106a is thinned by the process described with reference to FIG. 11B, the gate electrode 106a has a tensile stress as a whole. Note that the gate electrode 106b and the wiring 106c have a small stress as a whole, or 0 GPa or approximately 0 GPa.

  Next, as illustrated in FIG. 11D, only the upper portion of the crystalline semiconductor layer 102 b is covered with a photoresist film 120. Next, n-type impurities are implanted into the crystalline semiconductor layer 102a using the photoresist film 120 and the gate electrode 106a as a mask. Thereby, the low concentration impurity region 107a and the impurity region 108a are formed.

  Thereafter, as shown in FIG. 12A, the photoresist film 120 is removed. Next, only the upper part of the crystalline semiconductor layer 102 a is covered with the photoresist film 121. Next, p-type impurities are implanted into the crystalline semiconductor layer 102b using the photoresist film 121 and the gate electrode 106b as a mask. Thereby, the low concentration impurity region 107b and the impurity region 108b are formed.

  Thereafter, as shown in FIG. 12B, the photoresist film 121 is removed.

  Next, as shown in FIG. 12C, an insulating film 109, an interlayer insulating film 110, connection holes 110a, 110b, and 110c, and wirings 111a, 111b, and 111c are formed. These forming methods are the same as those in the first embodiment.

As described above, according to the sixth embodiment, the gate electrodes 106a and 106b and the wiring 106c are formed on the first conductive films 104a, 104b, and 104c having tensile stress, respectively, and the second conductive film 105a having compressive stress. , 105b, 105c are stacked. The second conductive film 105a is thinner than the second conductive films 105b and 105c. Therefore, the stress of the gate electrode 106a can be used as tensile stress, and the stress of the gate electrode 106b and the wiring 106c can be reduced, or 0 GPa or approximately 0 GPa. Further, the stress of the gate electrode 106b and the wiring 106c can be a compressive stress.
Therefore, according to this embodiment, the same effect as that of the first embodiment can be obtained.

(Seventh embodiment)
Each drawing in FIG. 13 is a cross-sectional view for explaining the method for manufacturing a semiconductor device according to the seventh embodiment. This embodiment is different from the sixth embodiment in the timing of thinning the second conductive film constituting the gate electrode 106b and the wiring 106c. Hereinafter, the same components as those of the sixth embodiment are denoted by the same reference numerals, and description thereof is omitted.

  First, as shown in FIG. 13A, a base insulating film 101 is formed on a substrate 100, and crystalline semiconductor layers 102a and 102b, gate insulating films 103a and 103b, an insulating film 103, and a first conductive film 104 are formed. , And a second conductive film 105 are formed.

  Next, as shown in FIG. 13B, a photoresist film (not shown) is applied on the second conductive film 105, and this photoresist film is exposed and developed. As a result, a resist pattern is formed on the second conductive film 105. Next, the first and second conductive films 104 and 105 are etched using this resist pattern as a mask. As a result, the first and second conductive films 104 and 105 are patterned to form gate electrodes 106a and 106b and a wiring 106c.

The etching rate for forming the gate electrodes 106 a and 106 b and the wiring 106 c is higher for the second conductive film 105 than for the first conductive film 104. Therefore, the width of each of the second conductive films 105a to 105c is narrower than the width of each of the first conductive films 104a to 104c.
Thereafter, the resist pattern is removed.

Next, as shown in FIG. 13C, a photoresist film is applied on the entire surface including the gate electrodes 106a and 106b and the wiring 106c, and this photoresist film is exposed and developed. As a result, the photoresist film is patterned, and the photoresist film located on the gate electrode 106a is removed. Next, the second conductive film 105a included in the gate electrode 106a is thinned by performing etching using the photoresist film as a mask.
Thereafter, the photoresist film is removed.

  Next, as shown in FIG. 13D, the low concentration impurity regions 107a and 107b, the impurity regions 108a and 108b, the insulating film 109, the interlayer insulating film 110, the connection holes 110a, 110b, and 110c, and the wirings 111a, 111b, and 111c. Form. These forming methods are the same as those in the sixth embodiment.

  Also in this embodiment, the same effect as that in the sixth embodiment can be obtained.

(Eighth embodiment)
14 and 15 are cross-sectional views for explaining the method for manufacturing a semiconductor device according to the eighth embodiment. This embodiment is different from the seventh embodiment in the timing of thinning the second conductive film 105a included in the gate electrode 106a. Hereinafter, the same components as those of the seventh embodiment are denoted by the same reference numerals, and description thereof is omitted.

  First, as shown in FIG. 14A, a base insulating film 101 is formed on a substrate 100, and crystalline semiconductor layers 102a and 102b, gate insulating films 103a and 103b, an insulating film 103, gate electrodes 106a and 106b, Then, the wiring 106c is formed. These forming methods are the same as those in the seventh embodiment.

  Next, as shown in FIG. 14B, only the upper part of the crystalline semiconductor layer 102 b is covered with a photoresist film 120. Next, n-type impurities are implanted into the crystalline semiconductor layer 102a using the photoresist film 120 and the gate electrode 106a as a mask. Thereby, the low concentration impurity region 107a and the impurity region 108a are formed.

  Thereafter, as shown in FIG. 14C, the photoresist film 120 is removed. Next, the second conductive film 105a included in the gate electrode 106a is thinned. This method is the same as in the seventh embodiment.

  Next, as shown in FIG. 15A, only the upper part of the crystalline semiconductor layer 102 a is covered with a photoresist film 121. Next, p-type impurities are implanted into the crystalline semiconductor layer 102b using the photoresist film 121 and the gate electrode 106b as a mask. Thereby, the low concentration impurity region 107b and the impurity region 108b are formed.

  Thereafter, as shown in FIG. 15B, the photoresist film 121 is removed.

  Next, as shown in FIG. 15C, an insulating film 109, an interlayer insulating film 110, connection holes 110a, 110b, and 110c, and wirings 111a, 111b, and 111c are formed. These forming methods are the same as those in the seventh embodiment.

  As described above, also in the eighth embodiment, the same effect as in the sixth embodiment can be obtained.

(Ninth embodiment)
16 and 17 are cross-sectional views for explaining the method for manufacturing a semiconductor device according to the ninth embodiment. This embodiment is different from the eighth embodiment in the timing of thinning the second conductive films 105b and 105c included in the gate electrode 106b and the wiring 106c. Hereinafter, the same components as those in the eighth embodiment are denoted by the same reference numerals, and description thereof is omitted.

  First, as shown in FIG. 16A, a base insulating film 101 is formed on a substrate 100, and crystalline semiconductor layers 102a and 102b, gate insulating films 103a and 103b, an insulating film 103, gate electrodes 106a and 106b, Then, the wiring 106c is formed. These forming methods are the same as those in the eighth embodiment.

  Next, as illustrated in FIG. 16B, only the upper portion of the crystalline semiconductor layer 102 b is covered with a photoresist film 120. Next, n-type impurities are implanted into the crystalline semiconductor layer 102a using the photoresist film 120 and the gate electrode 106a as a mask. Thereby, the low concentration impurity region 107a and the impurity region 108a are formed.

  Thereafter, as shown in FIG. 16C, the photoresist film 120 is removed. Next, only the upper part of the crystalline semiconductor layer 102 a is covered with the photoresist film 121. Next, p-type impurities are implanted into the crystalline semiconductor layer 102b using the photoresist film 121 and the gate electrode 106b as a mask. Thereby, the low concentration impurity region 107b and the impurity region 108b are formed.

  Thereafter, the photoresist film 121 is removed as shown in FIG.

  Next, as illustrated in FIG. 17B, the second conductive film 105a included in the gate electrode 106a is thinned. This method is the same as in the eighth embodiment.

  Next, as shown in FIG. 17C, an insulating film 109, an interlayer insulating film 110, connection holes 110a, 110b, and 110c, and wirings 111a, 111b, and 111c are formed. These forming methods are the same as those in the eighth embodiment.

  As described above, the ninth embodiment can provide the same effects as those of the sixth embodiment.

(Tenth embodiment)
Each drawing in FIG. 18 is a cross-sectional view for explaining the method for manufacturing the semiconductor device according to the tenth embodiment. The semiconductor device manufactured by this embodiment is the same as that of the ninth embodiment except for the configuration of the gate electrode 106a. Hereinafter, the same components as those of the ninth embodiment are denoted by the same reference numerals, and description thereof is omitted.

  First, as shown in FIG. 18A, a base insulating film 101 is formed on a substrate 100, and crystalline semiconductor layers 102a and 102b, gate insulating films 103a and 103b, an insulating film 103, gate electrodes 106a and 106b, Wiring 106c, low-concentration impurity regions 107a and 107b, and impurity regions 108a and 108b are formed. These forming methods are the same as those in the ninth embodiment.

  Next, as shown in FIG. 18B, the second conductive film 105a included in the gate electrode 106a is removed. This method is the same as the method of thinning the second conductive film 105a in the ninth embodiment except that the etching conditions change (for example, the etching time becomes long).

  Next, as shown in FIG. 18C, an insulating film 109, an interlayer insulating film 110, connection holes 110a, 110b, and 110c, and wirings 111a, 111b, and 111c are formed. These forming methods are the same as those in the ninth embodiment.

  As described above, according to the tenth embodiment, the gate electrode 106a of the n-type thin film transistor is configured only by the first conductive film 104a having tensile stress. On the other hand, each of the gate electrode 106b and the wiring 106c of the p-type thin film transistor has second conductive films 105b and 105c having compressive stress on the first conductive films 104b and 104c having tensile stress. Therefore, the gate electrode 106a has tensile stress, and the stress of the gate electrode 106b and the wiring 106c can be reduced, or can be 0 GPa or approximately 0 GPa. Further, the stress of the gate electrode 106b and the wiring 106c can be a compressive stress.

  Therefore, the tenth embodiment can provide the same effects as those of the sixth embodiment. In addition, when the second conductive film 105a is removed, the first conductive film 104a can be used as an etching stopper, so that in-plane variation of the gate electrode 106a can be suppressed.

  Note that in the methods described in the sixth to eighth embodiments, the second conductive film 105a included in the gate electrode 106a may be removed by changing the etching conditions (for example, the etching time becomes longer).

  In the first to tenth embodiments described above, the first conductive film 104 and the second conductive film 105 are formed of different materials, but may be continuously formed of the same material. In this case, by changing the film formation conditions during film formation, the lower layer has compressive stress and the upper layer has tensile stress, or the lower layer has tensile stress and the upper layer has compressive stress. A film can be formed. In this case, since only one film forming apparatus and one film forming material are required, the manufacturing cost is reduced.

  Further, the insulating film 103 may be removed before the first insulating film 104 and the second insulating film 105 are formed. In this case, the wiring 106 c is formed directly on the base insulating film 101.

  In each of the above steps, a mask pattern may be formed by an ink jet method or a nanoimprint method instead of the resist pattern, and the second conductive film 105 may be etched using the mask pattern as a mask.

(First embodiment)
FIG. 19 is a plan view for explaining a configuration of a pixel included in the display device according to the first example of the present invention. The display device is, for example, a liquid crystal display device, an organic EL display device, or an inorganic EL display device. In this display device, the signal wiring 208a and the source wiring 208b are arranged in parallel with each other (extending in the vertical direction in the drawing) and separated from each other. The plurality of gate wirings 205 extend in a direction substantially perpendicular to the signal wiring 208a (the left-right direction in the figure) and are arranged to be separated from each other. A substantially rectangular space is surrounded by the signal wiring 208a, the source wiring 208b, and the gate wiring 205, and pixels of the display device are arranged in this space. An n-type thin film transistor 221 and a p-type thin film transistor 222 for driving the pixel are arranged above the pixel in the drawing.

  The gate wiring 205 is connected to the gate electrode 221a of the n-type thin film transistor 221. The n-type thin film transistor 221 includes impurity layers 201a and 201b that function as a source or a drain.

The impurity layer 201b is connected to the gate electrode 222a of the p-type thin film transistor 222 through the contact hole 202b, the wiring 208c, and the contact hole 202c.
The p-type thin film transistor 222 includes an impurity layer 201c serving as a source and an impurity layer 201d serving as a drain. The impurity layer 201c is connected to the source wiring 208b through the contact hole 202d, and the impurity layer 201d is connected to the pixel electrode 210 through the contact hole (not shown), the conductive layer 208d, and the via hole 202e. .

  Each of the impurity layers 201a to 201d is obtained by introducing impurities into an island-shaped crystalline semiconductor layer (for example, a polysilicon layer) formed on a substrate (not shown). The gate electrodes 221a and 222a and the gate wiring 205 are located in a layer above the impurity layers 201a to 201d with a gate insulating film (not shown) interposed therebetween. The signal wiring 208a, the source wiring 208b, the wiring 208c, and the conductive layer 208d are located on a layer above the gate electrode 221a with a first interlayer insulating film (not shown) interposed therebetween. The pixel electrode 210 is located in a layer above the signal wiring 208a with a second interlayer insulating film (not shown) interposed therebetween.

  A part of the gate electrode 222a of the p-type thin film transistor 222 is located below the gate wiring 208b via the first interlayer insulating film. This portion of the gate electrode 222a is further located above the impurity layer 201 via the gate insulating film. With such a structure, part of the gate electrode 222a forms the capacitor 212 together with the gate wiring 208b and the first interlayer insulating film, and the impurity layer 201 and the gate insulating film.

  Each of the n-type thin film transistor 221 and the p-type thin film transistor 222 has the same structure as the n-type thin film transistor and the p-type thin film transistor described in the first to tenth embodiments. That is, the gate electrode 221a has the same structure as any of the gate electrodes 106a shown in the first to tenth embodiments. Similarly, the gate electrode 222a and the gate wiring 205 have the same structure as any of the gate electrode 106b and the wiring 106c shown in the first to tenth embodiments.

  For this reason, according to the display apparatus which concerns on a present Example, the effect similar to 1st-10th embodiment can be acquired. Further, since the stress applied to the substrate is reduced, the reliability of the display device is increased.

(Second embodiment)
FIG. 20A is a plan view for explaining the configuration of the display module according to the second embodiment, and FIG. 20B is a cross-sectional view taken along the line AA ′ of FIG. This display module is an organic EL display device, and the display device shown in the first embodiment is used.

  This display module includes an active matrix substrate 3610. A counter substrate 3604 is disposed at a position facing the active matrix substrate 3610. These two substrates are bonded to each other with a sealant 3605. There is a space 3607 sealed with a sealant 3605 between the two substrates.

  A pixel region 3602 is provided in the center of the active matrix substrate 3610. The pixel region 3602 is located inside the space 3607 and has a plurality of pixels. Each pixel includes an n-type thin film transistor 3611, a p-type thin film transistor 3612, and an organic EL element 3618.

  An n-type thin film transistor 3611 and a p-type thin film transistor 3612 correspond to the n-type thin film transistor 221 and the p-type thin film transistor 222 shown in the first embodiment, respectively.

  The organic EL element 3618 is obtained by stacking an anode electrode 3613, an organic EL layer 3616, and a cathode electrode 3617 in this order. The anode electrode 3613 functions as a pixel electrode and corresponds to the pixel electrode 210 shown in the first embodiment.

  An insulating layer 3614 is provided between the anode electrode 3613 and the active matrix substrate 3610. The insulating layer 3614 is formed from, for example, an organic material. Although the organic EL layer 3616 is formed by an evaporation method, the insulating matrix 3614 is provided, whereby the active matrix substrate 3610 can be protected from process damage when the organic EL layer 3616 is evaporated.

  In addition, wiring 3608 is disposed in the periphery of the active matrix substrate 3610. A flexible printed circuit (hereinafter referred to as FPC) 3609 and an external IC chip 3619 are attached to the end of the wiring 3608.

  A signal wiring driver circuit 3601 is provided between the pixel region 3602 and the wiring 3608. The signal wiring drive circuit 3601 is located inside the space 3607 and is connected to the signal wiring 208a shown in the first embodiment. The signal wiring driver circuit 3601 includes an n-type thin film transistor 3620 and a p-type thin film transistor 3621. The n-type thin film transistor 3620 and the p-type thin film transistor 3621 have the same structure as the n-type thin film transistor and the p-type thin film transistor described in the first to tenth embodiments.

  In addition, gate wiring driving circuits 3603 and 3606 are provided around the pixel region 3602. Gate wiring drive circuits 3603 and 3606 are located in the space 3607 and are connected to the gate wiring 205 shown in the first embodiment. The gate wiring drive circuits 3603 and 3606 have an n-type thin film transistor and a p-type thin film transistor (both not shown) having the structure shown in the first to tenth embodiments.

  According to the display device according to the present embodiment, the reliability of the display module is increased by the same operation as that of the first embodiment.

(Third embodiment)
FIG. 21A is a plan view for explaining a display module according to the third embodiment. This display module has the same structure as that of the second embodiment except that the signal line driving circuit 3601 is located outside the space sealed by the sealing material 3605. Hereinafter, the same components as those of the second embodiment are denoted by the same reference numerals, and description thereof is omitted.
Also with the display device according to the present embodiment, the same effects as those of the second embodiment can be obtained.

(Fourth embodiment)
FIG. 21B is a plan view for explaining the display module according to the fourth embodiment. This display module has the same structure as that of the second embodiment except that the signal line drive circuit 3601 and the gate line drive circuits 3603 and 3606 are located outside the space sealed by the sealing material 3605. Have Hereinafter, the same components as those of the second embodiment are denoted by the same reference numerals, and description thereof is omitted.
Also with the display device according to the present embodiment, the same effects as those of the second embodiment can be obtained.

(Fifth embodiment)
An electronic apparatus according to a fifth embodiment will be described with reference to FIG. This electronic apparatus has the light emitting device of the present invention, and is mounted with a module as shown in the above-described embodiment.

  As this electronic device, a video camera, a digital camera, a goggle type display (head mounted display), a navigation system, a sound reproduction device (car audio component, etc.), a computer, a game device, a portable information terminal (mobile computer, cellular phone, portable type) A game machine or an electronic book), an image playback device provided with a recording medium (specifically, a device provided with a display capable of playing back a recording medium such as a Digital Versatile Disc (DVD) and displaying the image). It is done. Specific examples of these electronic devices are shown in FIGS.

  FIG. 22A shows a television receiver or a personal computer monitor. A housing 35001, a support base 35002, a display portion 35003, a speaker portion 35004, a video input terminal 35005, and the like are included. For the display portion 35003, the display module shown in any one of the second to fourth embodiments is used. By using this display module, the reliability of a television receiver or a monitor of a personal computer can be increased.

  FIG. 22B shows a digital camera. An image receiving portion 35103 is provided on the front portion of the main body 35101, and a shutter 35106 is provided on the upper surface portion of the main body 35101. Further, a display portion 35102, operation keys 35104, and an external connection port 35105 are provided on the back surface portion of the main body 35101. For the display portion 35102, the display module shown in any of the second to fourth embodiments is used. By having this display module, the reliability of the digital camera can be increased.

  FIG. 22C shows a notebook personal computer. A main body 35201 is provided with a keyboard 35204, an external connection port 35205, and a pointing mouse 35206. In addition, a housing 35202 having a display portion 35203 is attached to the main body 35201. For the display portion 35203, the display module shown in any one of the second to fourth embodiments is used. By having this display module, the reliability of the notebook personal computer can be increased.

  FIG. 22D illustrates a mobile computer, which includes a main body 35301, a display portion 35302, a switch 35303, operation keys 35304, an infrared port 35305, and the like. For the display portion 35302, the display module shown in any of the second to fourth embodiments is used. By having this display module, the reliability of the mobile computer can be increased.

  FIG. 22E shows an image reproducing device. A main body 35401 is provided with a display portion B 35404, a recording medium reading portion 35405, and operation keys 35406. In addition, a housing 35402 including a speaker portion 35407 and a display portion A35403 is attached to the main body 35401. For each of the display portion A 35403 and the display portion B 35404, the display module shown in any of the second to fourth embodiments is used. By having this display module, the reliability of the image reproducing apparatus can be increased.

  FIG. 22F illustrates a head mounted display which includes a main body 35501 having a display portion 35502 and an arm portion 35503. For the display portion 35502, the display module shown in any of the second to fourth embodiments is used. By having this display module, the reliability of the head mounted display can be increased.

  FIG. 22G shows a video camera. A main body 35601 is provided with an external connection port 35604, a remote control receiver 35605, an image receiver 35606, a battery 35607, an audio input unit 35608, an eyepiece 35609, and operation keys 35610. In addition, a housing 35603 including a display portion 35602 is attached to the main body 35601. The display module shown in any one of the second to fourth embodiments is used for the display portion 35602. By having this display module, the reliability of the video camera can be increased.

  FIG. 22H shows a mobile phone, which includes a main body 35701, a housing 35702, a display portion 35703, an audio input portion 35704, an audio output portion 35705, operation keys 35706, an external connection port 35707, an antenna 35708, and the like. For the display portion 35703, the display module shown in any of the second to fourth embodiments is used. By including this display module, the reliability of the mobile phone can be increased.

  Note that the present invention is not limited to the above-described embodiment, and various modifications can be made without departing from the spirit of the present invention.

Sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment. Sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment. Sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 1st Embodiment. 10 is a graph showing how the stress of the stacked film of the first conductive film 104 and the second conductive film 105 changes depending on the thickness of the second conductive film 105. Sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 2nd Embodiment. Sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 3rd Embodiment. Sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 3rd Embodiment. Sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 4th Embodiment. Sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 4th Embodiment. Sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 5th Embodiment. Sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 6th Embodiment. Sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 6th Embodiment. Sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 7th Embodiment. Sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 8th Embodiment. Sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 8th Embodiment. Sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 9th Embodiment. Sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 9th Embodiment. Sectional drawing for demonstrating the manufacturing method of the semiconductor device which concerns on 10th Embodiment. FIG. 3 is a plan view for explaining a configuration of a pixel included in the display device according to the first embodiment. (A) is a top view for demonstrating the structure of the display module which concerns on a 2nd Example, (b) is AA 'sectional drawing of (a). (A) is a top view for demonstrating the display module which concerns on a 3rd Example, (b) is a top view for demonstrating the display module which concerns on a 4th Example. Each figure is a perspective view for explaining an electronic apparatus according to a fifth embodiment.

Explanation of symbols

101 ... Underlying insulating films 102a, 102b ... Semiconductor layers 103a, 103b ... Gate insulating films 104, 104a-104c ... First conductive films 105, 105a-105c ... Second conductive films 106a, 106b ... Gate electrodes 106c ... Wiring

Claims (43)

Forming an island-shaped first semiconductor layer and an island-shaped second semiconductor layer over the base insulating film;
Forming a first gate insulating film located on the first semiconductor layer and a second gate insulating film located on the second semiconductor layer;
Forming a first conductive film having compressive stress on the first gate insulating film and the second gate insulating film;
Forming a second conductive film having a tensile stress on the first conductive film;
The first and second conductive films are etched to form a first gate electrode located on the first gate insulating film and a second gate electrode located on the second gate insulating film. And a process of
Thinning or removing the second conductive film constituting the second gate electrode;
A method for manufacturing a semiconductor device comprising: Forming an island-shaped first semiconductor layer and an island-shaped second semiconductor layer over the base insulating film;
Forming a first gate insulating film located on the first semiconductor layer and a second gate insulating film located on the second semiconductor layer;
Forming a first conductive film having a tensile stress on the first gate insulating film and the second gate insulating film;
Forming a second conductive film having a compressive stress on the first conductive film;
The first and second conductive films are etched to form a first gate electrode located on the first gate insulating film and a second gate electrode located on the second gate insulating film. And a process of
Thinning or removing the second conductive film constituting the first gate electrode;
A method for manufacturing a semiconductor device comprising: Forming an island-shaped first semiconductor layer and an island-shaped second semiconductor layer over the base insulating film;
Forming a first gate insulating film located on the first semiconductor layer and a second gate insulating film located on the second semiconductor layer;
Forming a first conductive film having compressive stress on or above the base insulating film, on the first gate insulating film, and on the second gate insulating film;
Forming a second conductive film having a tensile stress on the first conductive film;
Etching the first and second conductive films to form a first gate electrode located on the first gate insulating film, a second gate electrode located on the second gate insulating film, and the Forming a wiring located above or above the base insulating film;
Thinning or removing the second conductive film forming the wiring and the second conductive film constituting the second gate electrode;
A method for manufacturing a semiconductor device comprising: Forming an island-shaped first semiconductor layer and an island-shaped second semiconductor layer over the base insulating film;
Forming a first gate insulating film located on the first semiconductor layer and a second gate insulating film located on the second semiconductor layer;
Forming a first conductive film having a tensile stress on or above the base insulating film, on the first gate insulating film, and on the second gate insulating film;
Forming a second conductive film having a compressive stress on the first conductive film;
Etching the first and second conductive films to form a first gate electrode located on the first gate insulating film, a second gate electrode located on the second gate insulating film, and the Forming a wiring located above or above the base insulating film;
Thinning or removing the second conductive film constituting the first gate electrode;
A method for manufacturing a semiconductor device comprising: Forming an island-shaped semiconductor layer over the base insulating film;
Forming a gate insulating film located on the semiconductor layer;
Forming a first conductive film having a compressive stress on or above the base insulating film and on the gate insulating film;
Forming a second conductive film having a tensile stress on the first conductive film;
Etching the first and second conductive films to form a wiring located on or above the base insulating film and a gate electrode located on the gate insulating film;
Thinning or removing the second conductive film constituting the wiring; and
A method for manufacturing a semiconductor device comprising: Forming an island-shaped semiconductor layer over the base insulating film;
Forming a gate insulating film located on the semiconductor layer;
Forming a first conductive film having a tension on or above the base insulating film and on the gate insulating film;
Forming a second conductive film having a compressive stress on the first conductive film;
Etching the first and second conductive films to form a wiring located on or above the base insulating film and a gate electrode located on the gate insulating film;
Thinning or removing the second conductive film constituting the gate electrode;
A method for manufacturing a semiconductor device comprising: Forming an island-shaped first semiconductor layer and an island-shaped second semiconductor layer over the base insulating film;
Forming a first gate insulating film located on the first semiconductor layer and a second gate insulating film located on the second semiconductor layer;
Forming a first conductive film having compressive stress on the first gate insulating film and the second gate insulating film;
Forming a second conductive film having a tensile stress on the first conductive film;
Thinning or removing the second conductive film located on the second gate insulating film than the second conductive film located on the first gate insulating film;
The first and second conductive films are etched to form a first gate electrode located on the first gate insulating film and a second gate electrode located on the second gate insulating film. And a process of
A method for manufacturing a semiconductor device comprising: Forming an island-shaped first semiconductor layer and an island-shaped second semiconductor layer over the base insulating film;
Forming a first gate insulating film located on the first semiconductor layer and a second gate insulating film located on the second semiconductor layer;
Forming a first conductive film having a tensile stress on the first gate insulating film and the second gate insulating film;
Forming a second conductive film having a compressive stress on the first conductive film;
Thinning or removing the second conductive film located on the first gate insulating film than the second conductive film located on the second gate insulating film;
The first and second conductive films are etched to form a first gate electrode located on the first gate insulating film and a second gate electrode located on the second gate insulating film. And a process of
A method for manufacturing a semiconductor device comprising: Forming an island-shaped first semiconductor layer and an island-shaped second semiconductor layer over the base insulating film;
Forming a first gate insulating film located on the first semiconductor layer and a second gate insulating film located on the second semiconductor layer;
Forming a first conductive film having a compressive stress on or above the base insulating film, on the first gate insulating film, and on the second gate insulating film;
Forming a second conductive film having a tensile stress on the first conductive film;
The second conductive film positioned on the second gate insulating film and the second conductive film positioned on or above the base insulating film are positioned on the first gate insulating film. Thinning or removing the second conductive film;
Etching the first and second conductive films to form a first gate electrode located on the first gate insulating film, a second gate electrode located on the second gate insulating film, and the Forming a wiring located above or above the base insulating film;
A method for manufacturing a semiconductor device comprising: Forming an island-shaped first semiconductor layer and an island-shaped second semiconductor layer over the base insulating film;
Forming a first gate insulating film located on the first semiconductor layer and a second gate insulating film located on the second semiconductor layer;
Forming a first conductive film having a tensile stress on or above the base insulating film, on the first gate insulating film, and on the second gate insulating film;
Forming a second conductive film having a compressive stress on the first conductive film;
The second conductive film positioned on the first gate insulating film, the second conductive film positioned on the second gate insulating film, and the above-described upper conductive film positioned on or above the base insulating film Thinning or removing each of the second conductive films;
Etching the first and second conductive films to form a first gate electrode located on the first gate insulating film, a second gate electrode located on the second gate insulating film, and the Forming a wiring located above or above the base insulating film;
A method for manufacturing a semiconductor device comprising: Forming an island-shaped semiconductor layer over the base insulating film;
Forming a gate insulating film located on the semiconductor layer;
Forming a first conductive film having a compressive stress on or above the base insulating film and on the gate insulating film;
Forming a second conductive film having a tensile stress on the first conductive film;
Thinning or removing the second conductive film located on or above the base insulating film from the second conductive film located on the gate insulating film; and
Etching the first and second conductive films to form a wiring located above or above the base insulating film and a gate electrode located on the gate insulating film;
A method for manufacturing a semiconductor device comprising: Forming an island-shaped semiconductor layer over the base insulating film;
Forming a gate insulating film located on the semiconductor layer;
Forming a first conductive film having a tension on or above the base insulating film and on the gate insulating film;
Forming a second conductive film having a compressive stress on the first conductive film;
Making the second conductive film positioned on the gate insulating film thinner or removing the second conductive film positioned on or above the base insulating film;
Etching the first and second conductive films to form a wiring located on or above the base insulating film and a gate electrode located on the gate insulating film;
A method for manufacturing a semiconductor device comprising: The first gate electrode is a gate electrode of an n-type transistor;
The method for manufacturing a semiconductor device according to claim 1, wherein the second gate electrode is a gate electrode of a p-type transistor.   In the step of etching the first and second conductive films, the gate length of the first conductive film constituting the first gate electrode is set to be the second conductive film constituting the first gate electrode. And the gate length of the first conductive film constituting the second gate electrode is longer than the gate length of the second conductive film constituting the second gate electrode. Item 14. The method for manufacturing a semiconductor device according to any one of Items 1-4, 7-10, and 13.   In the step of etching the first and second conductive films, the gate length of the first conductive film constituting the gate electrode is made longer than the gate length of the second conductive film constituting the gate electrode. The method for manufacturing a semiconductor device according to claim 5, 6, 11, or 12. Having a base insulating film,
An island-shaped first semiconductor layer formed on the base insulating film;
A first gate insulating film formed on the first semiconductor layer;
A first gate electrode composed of a first conductive film formed on the first gate insulating film and a second conductive film formed on the first conductive film;
A first thin film transistor comprising:
An island-shaped second semiconductor layer formed on the base insulating film;
A second gate insulating film formed on the second semiconductor layer;
A second gate electrode composed of a third conductive film formed on the second gate insulating film and a fourth conductive film formed on the third conductive film;
A second thin film transistor comprising:
A wiring composed of a fifth conductive film formed on or above the base insulating film and a sixth conductive film formed on the fifth conductive film;
Have
The first conductive film, the third conductive film, and the fifth conductive film have compressive stress,
The second conductive film, the fourth conductive film, and the sixth conductive film have tensile stress,
The film thickness of the fourth conductive film and the film thickness of the sixth conductive film are thinner than the film thickness of the second conductive film,
The first gate electrode has a tensile stress;
The second thin film transistor is a p-type thin film transistor,
The semiconductor device, wherein the first thin film transistor is an n-type thin film transistor. Having a base insulating film,
An island-shaped first semiconductor layer formed on the base insulating film;
A first gate insulating film formed on the first semiconductor layer;
A first gate electrode composed of a first conductive film formed on the first gate insulating film and a second conductive film formed on the first conductive film;
A first thin film transistor comprising:
An island-shaped second semiconductor layer formed on the base insulating film;
A second gate insulating film formed on the second semiconductor layer;
A second gate electrode composed of a third conductive film formed on the second gate insulating film and a fourth conductive film formed on the third conductive film;
A second thin film transistor comprising:
A wiring composed of a fifth conductive film formed on or above the base insulating film and a sixth conductive film formed on the fifth conductive film;
Have
The first conductive film, the third conductive film, and the fifth conductive film have tensile stress,
The second conductive film, the fourth conductive film, and the sixth conductive film have compressive stress,
The film thickness of the fourth conductive film and the film thickness of the sixth conductive film are thicker than the film thickness of the second conductive film,
The first gate electrode has a tensile stress;
The second thin film transistor is a p-type thin film transistor,
The semiconductor device, wherein the first thin film transistor is an n-type thin film transistor. Having a base insulating film,
An island-shaped first semiconductor layer formed on the base insulating film;
A first gate insulating film formed on the first semiconductor layer;
A first gate electrode composed of a first conductive film formed on the first gate insulating film and a second conductive film formed on the first conductive film;
A first thin film transistor comprising:
An island-shaped second semiconductor layer formed on the base insulating film;
A second gate insulating film formed on the second semiconductor layer;
A second gate electrode composed of a third conductive film formed on the second gate insulating film and a fourth conductive film formed on the third conductive film;
A second thin film transistor comprising:
Have
The first conductive film and the third conductive film have compressive stress,
The second conductive film and the fourth conductive film have a tensile stress,
The film thickness of the fourth conductive film is thinner than the film thickness of the second conductive film,
The first gate electrode has a tensile stress;
The second thin film transistor is a p-type thin film transistor,
The semiconductor device, wherein the first thin film transistor is an n-type thin film transistor. Having a base insulating film,
An island-shaped first semiconductor layer formed on the base insulating film;
A first gate insulating film formed on the first semiconductor layer;
A first gate electrode composed of a first conductive film formed on the first gate insulating film and a second conductive film formed on the first conductive film;
A first thin film transistor comprising:
An island-shaped second semiconductor layer formed on the base insulating film;
A second gate insulating film formed on the second semiconductor layer;
A second gate electrode composed of a third conductive film formed on the second gate insulating film and a fourth conductive film formed on the third conductive film;
A second thin film transistor comprising:
Have
The first conductive film and the third conductive film have a tensile stress,
The second conductive film and the fourth conductive film have compressive stress,
The film thickness of the fourth conductive film is thicker than the film thickness of the second conductive film,
The first gate electrode has a tensile stress;
The second thin film transistor is a p-type thin film transistor,
The semiconductor device, wherein the first thin film transistor is an n-type thin film transistor. Having a base insulating film,
An island-shaped semiconductor layer formed on the base insulating film;
A gate insulating film formed on the semiconductor layer;
A gate electrode composed of a first conductive film formed on the gate insulating film and a second conductive film formed on the first conductive film;
A thin film transistor comprising:
A wiring composed of a third conductive film formed on or above the base insulating film and a fourth conductive film formed on the third conductive film;
Have
The first conductive film and the third conductive film have compressive stress,
The second conductive film and the fourth conductive film have a tensile stress,
The film thickness of the fourth conductive film is thinner than the film thickness of the second conductive film,
The gate electrode has a tensile stress;
The semiconductor device, wherein the thin film transistor is an n-type thin film transistor. Having a base insulating film,
An island-shaped semiconductor layer formed on the base insulating film;
A gate insulating film formed on the semiconductor layer;
A gate electrode composed of a first conductive film formed on the gate insulating film and a second conductive film formed on the first conductive film;
A thin film transistor comprising:
A wiring composed of a third conductive film formed on or above the base insulating film and a fourth conductive film formed on the third conductive film;
Have
The first conductive film and the third conductive film have a tensile stress,
The second conductive film and the fourth conductive film have compressive stress,
The film thickness of the fourth conductive film is thicker than the film thickness of the second conductive film,
The gate electrode has a tensile stress;
The semiconductor device, wherein the thin film transistor is an n-type thin film transistor. Having a base insulating film,
An island-shaped first semiconductor layer formed on the base insulating film;
A first gate insulating film formed on the first semiconductor layer;
A first gate electrode composed of a first conductive film formed on the first gate insulating film and a second conductive film formed on the first conductive film;
A first thin film transistor comprising:
An island-shaped second semiconductor layer formed on the base insulating film;
A second gate insulating film formed on the second semiconductor layer;
A second gate electrode made of a third conductive film, formed on the second gate insulating film;
A second thin film transistor comprising:
A wiring composed of a fourth conductive film formed on or above the base insulating film;
Have
The first conductive film, the third conductive film, and the fourth conductive film have compressive stress,
The second conductive film has a tensile stress,
The first gate electrode has a tensile stress;
The second thin film transistor is a p-type thin film transistor,
The semiconductor device, wherein the first thin film transistor is an n-type thin film transistor. Having a base insulating film,
An island-shaped first semiconductor layer formed on the base insulating film;
A first gate insulating film formed on the first semiconductor layer;
A first gate electrode composed of a first conductive film formed on the first gate insulating film;
A first thin film transistor comprising:
An island-shaped second semiconductor layer formed on the base insulating film;
A second gate insulating film formed on the second semiconductor layer;
A second gate electrode comprising: a second conductive film formed on the second gate insulating film; and a third conductive film formed on the second conductive film;
A second thin film transistor comprising:
A wiring composed of a fourth conductive film formed on or above the base insulating film and a fifth conductive film formed on the fourth conductive film;
Have
The first conductive film, the second conductive film, and the fourth conductive film have tensile stress,
The third conductive film and the fifth conductive film have compressive stress,
The second thin film transistor is a p-type thin film transistor,
The semiconductor device, wherein the first thin film transistor is an n-type thin film transistor. Having a base insulating film,
An island-shaped first semiconductor layer formed on the base insulating film;
A first gate insulating film formed on the first semiconductor layer;
A first gate electrode composed of a first conductive film formed on the first gate insulating film and a second conductive film formed on the first conductive film;
A first thin film transistor comprising:
An island-shaped second semiconductor layer formed on the base insulating film;
A second gate insulating film formed on the second semiconductor layer;
A second gate electrode made of a third conductive film, formed on the second gate insulating film;
A second thin film transistor comprising:
Have
The first conductive film and the third conductive film have compressive stress,
Having a second conductive film tensile stress;
The first gate electrode has a tensile stress;
The second thin film transistor is a p-type thin film transistor,
The semiconductor device, wherein the first thin film transistor is an n-type thin film transistor. Having a base insulating film,
An island-shaped first semiconductor layer formed on the base insulating film;
A first gate insulating film formed on the first semiconductor layer;
A first gate electrode composed of a first conductive film formed on the first gate insulating film;
A first thin film transistor comprising:
An island-shaped second semiconductor layer formed on the base insulating film;
A second gate insulating film formed on the second semiconductor layer;
A second gate electrode comprising: a second conductive film formed on the second gate insulating film; and a third conductive film formed on the second conductive film;
A second thin film transistor comprising:
Have
The first conductive film and the second conductive film have a tensile stress,
The third conductive film has a compressive stress,
The second thin film transistor is a p-type thin film transistor,
The semiconductor device, wherein the first thin film transistor is an n-type thin film transistor. Having a base insulating film,
An island-shaped semiconductor layer formed on the base insulating film;
A gate insulating film formed on the semiconductor layer;
A gate electrode composed of a first conductive film formed on the gate insulating film and a second conductive film formed on the first conductive film;
A thin film transistor comprising:
A wiring composed of a third conductive film formed on or above the base insulating film;
Have
The first conductive film and the third conductive film have compressive stress,
The second conductive film has a tensile stress,
The gate electrode has a tensile stress;
The semiconductor device, wherein the thin film transistor is an n-type thin film transistor. Having a base insulating film,
An island-shaped semiconductor layer formed on the base insulating film;
A gate insulating film formed on the semiconductor layer;
A gate electrode made of a first conductive film formed on the gate insulating film;
A thin film transistor comprising:
A wiring composed of a second conductive film formed on or above the base insulating film and a third conductive film formed on the second conductive film;
Have
The first conductive film and the second conductive film have a tensile stress,
The third conductive film has a compressive stress,
The semiconductor device, wherein the thin film transistor is an n-type thin film transistor. In claim 16, claim 17, claim 18, claim 19, claim 23, or claim 25,
2. The semiconductor device according to claim 1, wherein the stress of the second gate electrode is a tensile stress having a value smaller than the tensile stress of the first gate electrode. In claim 16, claim 17, claim 18, claim 19, claim 23, or claim 25,
The semiconductor device according to claim 1, wherein the stress of the second gate electrode is a compressive stress. In claim 16, claim 17, claim 18, claim 19, claim 23, or claim 25,
The semiconductor device, wherein the stress of the second gate electrode is 0 GPa or approximately 0 GPa. In claim 16, claim 17, or claim 23,
The semiconductor device according to claim 1, wherein the wiring stress is a tensile stress having a value smaller than a tensile stress of the first gate electrode. In claim 20, claim 21 or claim 27,
The semiconductor device according to claim 1, wherein the wiring stress is a tensile stress having a value smaller than a tensile stress of the gate electrode. In claim 16, claim 17, claim 20, claim 21, claim 23, or claim 27,
The semiconductor device characterized in that the stress of the wiring is a compressive stress. In claim 16, claim 17, claim 20, claim 21, claim 23, or claim 27,
A stress of the wiring is 0 GPa or approximately 0 GPa. In claim 16, claim 17, or claim 23,
2. The semiconductor device according to claim 1, wherein the stress of the second gate electrode and the stress of the wiring are tensile stresses having values smaller than the tensile stress of the first gate electrode. In claim 16, claim 17, or claim 23,
The semiconductor device according to claim 1, wherein the stress of the second gate electrode and the stress of the wiring are compressive stresses. In claim 16, claim 17, or claim 23,
The semiconductor device according to claim 1, wherein the stress of the second gate electrode and the stress of the wiring are 0 GPa or approximately 0 GPa. In any one of claims 16 to 19,
The semiconductor device according to claim 1, wherein a gate length of the third conductive film constituting the second gate electrode is longer than a gate length of the fourth conductive film. In claim 16, claim 17, claim 18, claim 19, claim 22, claim 24, or claim 38,
The semiconductor device according to claim 1, wherein a gate length of the first conductive film constituting the first gate electrode is longer than a gate length of the second conductive film. In claim 20, claim 21 or claim 26,
The semiconductor device according to claim 1, wherein a gate length of the first conductive film constituting the gate electrode is longer than a gate length of the second conductive film. In claim 23, claim 25, or claim 27,
The semiconductor device according to claim 1, wherein a gate length of the second conductive film constituting the second gate electrode is longer than a gate length of the third conductive film. In any one of claims 16 to 41,
The semiconductor device is characterized in that the crystal orientation of the first semiconductor layer is the highest in the (100) direction. An electronic apparatus comprising the semiconductor device according to any one of claims 16 to 42.

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