JPH11135797A - Working method for shape of laminated film and manufacture of thin-film transistor by making use of the same - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a manufacturing method for a thin-film transistor, in which the end face of a lower-layer metal film at 10 atomic % of Mo-W and that of a laminated gate electrode at 0.9 atomic % of Al-Zr are controlled, in which the coverage state of an inter-layer insulating layer is made good and whose insulating characteristic is not lowered. SOLUTION: A polycrystalline silicon layer as a semiconductor layer 2 is formed on a glass substrate 1. An SiO2 layer as a gate-insulating layer 4 is formed on it. In addition, a laminated film which is composed of a first gate electrode 5 in a film thickness of 100 nm and at 10 atomic % of No-W and of a second gate electrode 6 in a film thickness of 100 nm and at 0.9 atomic % of Al-Zr is formed by a sputtering method, and a first etching operation is performed by a mixed acid of phosphoric acid, acetic acid and water. In succession, without removing a photoresist 7, the gate electrode layer 5 is etched by a mixed acid of phosphoric acid and water, and the side-etching operation of the second gate electrode layer 6 is made to advance. Thereby, the coverage property of an inter-layer insulating film 8 which is formed in a later process can be ensured.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a thin film transistor applied to a liquid crystal display device, an image sensor, and the like.

[0002]

2. Description of the Related Art In recent years, a liquid crystal display device is mounted on a viewfinder of a home video camera, a notebook computer, and the like. Among these liquid crystal display devices, an active matrix type liquid crystal display device capable of displaying a high quality image is provided. Has received particular attention. In this active matrix type liquid crystal display device, as a switching element of a pixel electrode,
Thin Film Transi
(hereinafter, abbreviated as TFT) is often used.

The present applicant has already proposed a TFT array shown in FIG. 3 in Japanese Patent Application No. 8-285426.
This is because the semiconductor layer 2 is formed on the glass substrate 1, the gate insulating layer 4 is formed thereon, and the gate electrodes thereon are formed of Mo of the first gate electrode layer 5 and Al of the second gate electrode layer 6. −
It is formed of a laminated film of Nd 3.5%. Then, source / drain regions 3 are formed so as to be connected to the semiconductor layer 2. Then, an interlayer insulating layer 8, a contact hole, and a source / drain electrode 9 are formed to form a TFT array.

In the conventional TFT array configured as described above, for example, a laminated film of Mo-W 10 atomic% and Al-Zr 0.9% is used as a gate electrode. Since the etching of the laminated film can be easily performed by using an etching solution containing phosphoric acid and nitric acid which is often used as an etching solution for Al, the processing has been performed by one etching using this solution.

[0005]

However, in the above-described structure, since it is difficult to control the shape of the end face of the stacked gate electrode, the withstand voltage of the interlayer insulating layer between the gate electrode and the source / drain electrodes is reduced, There is a problem that a short circuit is likely to occur. The problem will be described below.

Since the gate electrode is a laminated film, the shape of the etching solution,
It is necessary to at least optimize the etching solution temperature, the material composition of the gate electrode, and the thickness configuration of the gate electrode. Also, the difference in the etching rate between the single-layer film and the laminated film due to the battery effect derived from the laminated structure of the dissimilar metals, and the difference in the etching state due to the etching pattern shape due to the supply state and how the etchant is supplied to the substrate surface, etc. Occur. For these reasons, it is difficult to control the end face shape of the laminated gate electrode with good reproducibility for each substrate or within the substrate. For example, the progress of side etching of the upper gate electrode is slow,
Sometimes it became a so-called eaves. When an interlayer insulating layer is formed on such a gate electrode, the coverage characteristics of the interlayer insulating layer at the end face of the gate electrode are deteriorated, and a decrease in withstand voltage with source / drain electrodes and a short circuit between wirings are likely to occur. Had issues. For this reason, a method of improving the end face shape of the stacked gate electrode so as not to lower the insulating characteristics of the interlayer insulating layer has been expected.

In view of the foregoing, the present invention controls the shape of the end surface of a gate electrode formed by laminating a lower metal film containing Mo as a main component and an upper metal film containing Al as a main component, and improves the insulating characteristics of the interlayer insulating layer. It is an object of the present invention to provide a method for manufacturing a thin film transistor which does not cause a reduction.

[0008]

Means for solving the problem according to the present invention have two configurations of 1) and 2). 1) In a manufacturing process of a thin film transistor in which a semiconductor layer, a gate insulating layer, and a gate electrode are sequentially stacked on an insulating substrate, the step of forming a gate electrode mainly includes a lower metal film mainly composed of Mo and Al. A step of depositing a laminated film with an upper metal film as a component, a step of etching the laminated film at a time and processing it into a predetermined shape, and using Al as a main component while leaving an etching mask material used at the time of the etching. Selectively etching the end face of the upper metal film.

2) In a manufacturing process of a thin film transistor in which a semiconductor layer, a gate insulating layer, and a gate electrode are sequentially laminated on an insulating substrate, a step of forming a gate electrode is performed by M
depositing a laminated film of a lower metal film mainly composed of o and an upper metal film mainly composed of Al, etching the laminated film at a time and processing it into a predetermined shape; Selectively etching and removing the upper metal film.

The present invention has the following effects due to the above two configurations. 1) The upper metal film is further selectively etched while leaving the etching mask for etching the laminated gate electrode. Thereby, the side etching of the end surface of the upper metal film proceeds more than the end surface of the lower metal film. Therefore, both end surfaces of the stacked gate electrode are substantially aligned or have a stepped shape, and the coverage characteristics of the interlayer insulating layer formed thereon in the subsequent steps are not impaired.

2) After etching the stacked gate electrode, only the upper metal film is selectively removed by etching. This allows
Only the lower metal film remains and the end face shape of the gate electrode is stable,
Subsequent steps do not impair the coverage characteristics of the interlayer insulating layer formed thereon.

[0012]

DESCRIPTION OF THE PREFERRED EMBODIMENTS The invention according to claim 1 of the present invention is characterized in that, in the pattern shape of a laminated film of a lower metal film mainly composed of Mo and an upper metal film mainly composed of Al, At once, and a method of processing the shape of the laminated film, characterized by comprising a step of selectively etching the upper metal film containing Al as a main component and processing it into a predetermined shape, After etching the stacked film, only the upper metal film is selectively etched. This has the effect of stabilizing the end face shape of the laminated film and not impairing the coverage characteristics of a thin film and the like formed thereon in subsequent steps.

According to a second aspect of the present invention, in the step of selectively etching the upper metal film mainly composed of Al and processing it into a predetermined shape, etching is performed with an etching solution containing at least phosphoric acid. 2. The method for processing the shape of a laminated film according to claim 1, wherein etching can be easily and selectively performed by an etching solution containing phosphoric acid, and thin films other than the upper metal film are etched by the etching solution. This has an effect that it is useful when the speed is low.

According to a third aspect of the present invention, in the step of selectively etching the upper metal film mainly composed of Al and processing it into a predetermined shape, the upper metal film is etched with an organic alkaline etchant. The method for processing the shape of a laminated film according to claim 1, which can be easily and selectively etched by an organic alkaline etching solution, and a thin film other than the upper metal film has a low etching rate with respect to this etching solution. It has the effect of being useful in some cases.

According to a fourth aspect of the present invention, in the step of selectively etching the upper metal film containing Al as a main component and processing it into a predetermined shape, at least tetra-methyl-ammonium hydroxide (hereinafter referred to as "tetra-methyl-ammonium hydroxide") is used. , TMA
H), which is an etching method using an alkaline etchant containing H.). The method according to claim 1, wherein the etching process can be easily and selectively performed with an alkaline etchant containing at least TMAH. In addition, a thin film other than the upper metal film has an effect that it is useful when the etching rate with respect to this etching solution is low.

According to a fifth aspect of the present invention, the lower metal film containing Mo as a main component is an alloy containing at least 0.5 atomic% and not more than 30 atomic% of W. A method for processing the shape of a laminated film according to any one of claims 1 to 4, wherein the use of a Mo-W alloy improves the stability of the film such as moisture resistance as compared with Mo alone, and the W An alloy containing 0.5 atomic% or more and 30 atomic% or less can be easily etched with an Al etchant containing nitric acid, and has an effect that the etching rate can be controlled by the W concentration.

According to a sixth aspect of the present invention, the upper metal film containing Al as a main component is an alloy containing at least 0.5 atomic% and not more than 10 atomic% of Zr. The method for processing a shape of a laminated film according to any one of claims 1 to 5, wherein the Al-Zr alloy has high heat resistance with respect to generation of hillocks, and thus has an effect that the film has good stability to a heat process. Have.

According to a seventh aspect of the present invention, the upper metal film mainly composed of Al contains at least Nd at 2 atomic%.
The method for processing the shape of a laminated film according to any one of claims 1 to 5, characterized in that the Al-Nd alloy is heat resistant to hillock generation. Has an effect that the stability of the film to the thermal process is good.

According to an eighth aspect of the present invention, in the manufacturing process of a thin film transistor in which a semiconductor layer, a gate insulating layer, and a gate electrode are sequentially laminated on an insulating substrate, the step of forming the gate electrode comprises: A step of depositing a laminated film of a lower metal film mainly composed of Mo and an upper metal film mainly composed of Al, a step of etching the laminated film at a time and processing it into a predetermined shape, and a step of using the etching. A method of manufacturing a thin film transistor, comprising a step of selectively etching an end face of the upper metal film mainly containing Al while leaving the etched mask material. In this method, the upper metal film is further selectively etched while leaving the etching mask for etching the stacked gate electrode. Thereby, the side etching of the end surface of the upper metal film proceeds more than the end surface of the lower metal film. Therefore, both end surfaces of the stacked gate electrode are substantially aligned or have a step-like shape, which has the effect of not impairing the coverage characteristics of the interlayer insulating layer formed thereon in the subsequent steps.

According to a ninth aspect of the present invention, in the manufacturing process of a thin film transistor in which a semiconductor layer, a gate insulating layer, and a gate electrode are sequentially laminated on an insulating substrate, the step of forming the gate electrode includes: Depositing a laminated film of a lower metal film mainly composed of Mo and an upper metal film mainly composed of Al, etching the laminated film at a time and processing it into a predetermined shape, And selectively removing the upper metal film by etching. This means that after etching the stacked gate electrode, only the upper metal film is selectively removed by etching. This has the effect that only the lower metal film remains and the end face shape of the gate electrode is stabilized, and the coverage characteristics of the interlayer insulating layer formed thereon in the subsequent steps are not impaired.

[0021] The invention according to claim 10 of the present invention is characterized in that
10. The method of manufacturing a thin film transistor according to claim 8, wherein, in the step of selectively etching the upper metal film mainly composed of: and processing it into a predetermined shape, etching is performed with an etchant containing at least phosphoric acid. Although this method is employed, it can be easily and selectively etched by an etching solution containing phosphoric acid, and is effective when a thin film other than the upper metal film has a low etching rate with respect to this etching solution.

The invention according to claim 11 of the present invention is characterized in that
10. The method of manufacturing a thin film transistor according to claim 8 or 9, wherein the step of selectively etching the upper metal film mainly composed of: and processing it into a predetermined shape is performed with an organic alkaline etchant. It has an effect that it can be easily and selectively etched by an organic alkaline etching solution, and is useful when a thin film other than the upper metal film has a low etching rate with respect to this etching solution.

According to a twelfth aspect of the present invention, Al
10. The method of manufacturing a thin film transistor according to claim 8, wherein in the step of selectively etching the upper metal film mainly composed of: and processing it into a predetermined shape, etching is performed with an alkaline etchant containing at least TMAH. This method can be easily and selectively etched by an alkaline etching solution containing at least TMAH, and is effective when a thin film other than the upper metal film has a low etching rate with respect to this etching solution.

According to a thirteenth aspect of the present invention, Mo
13. The method of manufacturing a thin film transistor according to claim 8, wherein the lower metal film mainly composed of: an alloy containing at least W in an amount of 0.5 to 30 atomic%. The use of an Mo-W alloy improves the stability of the film such as moisture resistance as compared to Mo alone. In addition, if the alloy contains 0.5 to 10 atomic% of W, nitric acid is used. The etching can be easily performed with an Al etching solution containing Al, and the etching rate can be controlled by the W concentration.

According to a fourteenth aspect of the present invention, there is provided
The upper metal film mainly composed of:
14. The method for manufacturing a thin film transistor according to claim 8, wherein the alloy is an alloy containing at least 30 at.% And at least 30 at.%, Wherein the Al-Zr alloy has heat resistance with respect to generation of hillocks. Has an effect that the stability of the film to the thermal process is good.

The invention according to claim 15 of the present invention is characterized in that
14. The method of manufacturing a thin film transistor according to claim 8, wherein the upper layer metal film mainly composed of: an alloy containing at least 2 at% and at most 5 at% of Nd. Since the Al—Nd alloy has high heat resistance with respect to the generation of hillocks, the Al—Nd alloy has an effect that the stability of the film in a heat process is good.

Hereinafter, an embodiment of the present invention will be described with reference to FIG.
This will be described with reference to FIG. (Embodiment 1) FIG. 1 shows a flow chart (cross-sectional view) of a manufacturing process of a thin film transistor according to Embodiment 1 of the present invention.

First, amorphous silicon having a thickness of 50 nm is formed as a precursor of the semiconductor layer 2 on the glass substrate 1 by a plasma CVD method, and is processed into an island shape using photolithography and etching. Next, thermal annealing is performed at 450 ° C. for 2 hours even in a vacuum, and the amount of hydrogen in the amorphous silicon is reduced so that the hydrogen in the amorphous silicon does not bump and deteriorate the film quality during the next laser annealing. Decrease.

Laser annealing is performed, for example, at a wavelength of 308 nm.
Is irradiated at, for example, about 300 mJ-cm ² to crystallize to form polycrystalline silicon as the semiconductor layer 2. On top of this, a normal pressure CVD is performed as a gate insulating film 4.
A 100-nm-thick silicon oxide is formed by a method.

Further, the first gate electrode 5 has a thickness of 1
A laminated film of 100 nm Mo-W 10 atomic% and 100 nm thick Al-Zr 0.9 atomic% as the second gate electrode 6 is formed by a sputtering method, and is processed using photolithography and etching.

The first etching of the gate electrode layer at this time is, for example, phosphoric acid (specific gravity 1.69): nitric acid (specific gravity 1.38): acetic acid (specific gravity 1.05): water = 16: 1 at 40 ° C. :
It is performed by wet etching of a mixed acid mixed at a ratio of 2: 1 (volume ratio). At this time, the etching end face shape is, for example, as shown in FIG.
It has an eaves shape as shown in FIG. Subsequently, without removing the photoresist 7, for example, phosphoric acid at 40 ° C .:
The second etching of the gate electrode layer is performed with water = 16: 3 (volume ratio), and the side etching of the second gate electrode layer 6 is advanced to obtain an end face shape shown in FIG. By this shape control, the coverage of the interlayer insulating layer 8 formed in the subsequent steps can be secured.

Next, as shown in FIG. 1C, phosphorus serving as a donor is introduced into a partial region of the semiconductor layer 2 using the first gate electrode layer 5 and the second gate electrode layer 6 as a mask. Source / drain regions 3 are formed.

At this time, for example, a method in which a gas is decomposed by high-frequency discharge plasma to generate ions containing at least the element to be introduced, and the ions are accelerated by an accelerating voltage without mass separation and introduced into the active semiconductor thin layer (ion·
Doping method), by introducing phosphorus as a donor using phosphine gas diluted with hydrogen gas,
Impurities can be sufficiently activated by heat treatment at 400 ° C. for about 30 minutes.

Then, as shown in FIG. 1D, as the interlayer insulating layer 8, for example, silicon oxide
After forming a thickness of 00 nm, a contact hole is formed by photolithography and etching.

Further, the source / drain electrodes 9 are formed by forming and etching, for example, Ti having a thickness of 100 nm and Al having a thickness of 400 nm by sputtering. Finally, annealing is performed at 350 ° C. for 60 minutes in a hydrogen atmosphere to compensate for defects in the polycrystalline silicon in the semiconductor layer 2 and the source / drain regions 3, thereby completing the thin film transistor.

The first embodiment configured as described above
The thin film transistor has the following effects. After the first etching of the gate electrode layer, the end face shape is, for example, as shown in FIG.
As shown in FIG. The shape of the second gate electrode layer 6 is controlled by the side etching of the second gate electrode layer 6 by the second etching of the subsequent gate electrode layer to obtain the end face shape shown in FIG. As a result, the coverage of the interlayer insulating layer 8 is improved, and a thin film transistor having good insulating properties between the gate electrode layers 5 and 6 and the source / drain electrodes 9 is obtained.

(Embodiment 2) FIG. 2 shows a flow chart (cross-sectional view) of a manufacturing process of a thin film transistor according to Embodiment 2 of the present invention. The second embodiment will be described below with reference to FIG. First, a film thickness of 50 was formed on a glass substrate 1 as a precursor of a semiconductor layer 2 by a plasma CVD method.
An amorphous silicon film having a thickness of nm is formed and processed into an island shape using photolithography and etching. Next, thermal annealing at 450 ° C. for 2 hours is performed in a vacuum, and the amount of hydrogen in the amorphous silicon is reduced so that the hydrogen in the amorphous silicon does not boil during the next laser annealing to deteriorate the film quality. Decrease. Laser annealing is performed, for example, at a wavelength of 30.
An 8 nm XeCl laser is irradiated at, for example, about 300 mJ / cm ² and crystallized to form polycrystalline silicon as the semiconductor layer 2. Thereon, a stacked film of 100 nm thick silicon oxide by a normal pressure CVD method and 50 nm thick TaOx film by a sputtering method is formed as the gate insulating layer 4.

Further, the first gate electrode 5 has a film thickness of 1
A 100 nm thick Al laminated film is formed as the second gate electrode 6 by sputtering with a thickness of 10 nm of Mo-W of 10 nm and processed by photolithography and etching. At this time, the gate electrode layer is etched by, for example, phosphoric acid (specific gravity 1.69): nitric acid (specific gravity 1.40) at 40 ° C.
38): acetic acid (specific gravity 1.05): water = 16: 1: 2: 1
It is performed by wet etching of a mixed acid mixed at (volume ratio). At this time, the shape of the etched end face is, for example, as shown in FIG.
It is shaped like an eave. Next, TaOx in the upper layer of the gate insulating film 4 is processed as shown in FIG. 2B by photolithography and dry etching. Next, the first
Using the gate electrode layer 5 and the second gate electrode layer 6 as masks, phosphorus serving as a donor is introduced into a partial region of the semiconductor layer 2 by using an ion doping method to form a source / drain region 3. At this time, the amount of phosphorus implanted in the region covered with TaOx is smaller than that in the source / drain region 3, and the region is doped with LDD (lightly doped drain).
Region 10 is formed.

In the case of this embodiment, the Mo-W of 100 nm alone does not have sufficient stopping power for impurities in the channel region during ion doping, and the stopping power is secured by 100 nm Al of the second gate electrode layer 6. doing. Thereafter, using the second gate electrode layer 6 as a mask, TaOx is removed by dry etching. This step of removing TaOx is necessary to sufficiently bring out the transistor characteristics of the LDD structure formed according to the present embodiment.
It is necessary to eliminate the influence of the charge in TaOx in the region.

As a mask for removing the TaOx, a photoresist which is related to mask alignment accuracy cannot be used. Therefore, using the gate electrode layer as a mask, dry etching of TaOx is performed, for example, by CF ₄ + O _2.
It is easiest to do with gas. For this etching, the first gate electrode layer 5 of 10 atomic% of Mo-W does not work as a mask because it is etched. Therefore, Al of the second gate electrode layer is used as an upper layer and used as a mask.

After removing this TaOx, for example, at 40 ° C.
Since phosphoric acid: water = 16: 3 (volume ratio) remains as the second gate electrode layer, its end face shape is as shown in FIG. Therefore, the coverage characteristics of the interlayer insulating layer 8 formed in the subsequent steps can be secured. After 400 nm of silicon oxide is formed as the interlayer insulating layer 8 by, for example, normal pressure CVD, a contact hole is formed by photolithography and etching. Further, the source / drain electrodes 9 are formed by, for example, depositing and etching Ti having a thickness of 100 nm and Al having a thickness of 400 nm by a sputtering method. Finally, in a hydrogen atmosphere at 350 ° C. 60
A minute annealing process is performed to compensate for the defects in the polycrystalline silicon of the semiconductor layer 2 and the source / drain regions 3 to complete the thin film transistor.

The second embodiment configured as described above
The thin film transistor has the following effects. After the first etching of the gate electrode layer, the end face shape is, for example, as shown in FIG.
As shown in FIG. The shape of the second gate electrode layer 6 is controlled by the side etching of the second gate electrode layer 6 by the second etching of the gate electrode layer thereafter to obtain the end face shape shown in FIG. As a result, the coverage of the interlayer insulating film 8 is improved, and a thin film transistor having good insulation between the gate electrode layers 5 and 6 and the source / drain electrodes 9 is obtained. Further, since the Mo-based alloy used for the first gate electrode layer 5 is a material which is relatively unstable with respect to moisture resistance and the like, its surface is kept in the air as much as possible just before forming the upper interlayer insulating layer 8. There is also the effect of preventing deterioration without giving it out.

In the first and second embodiments, a plasma CVD method is used as a method for forming a precursor of a semiconductor layer.
Low pressure CVD, sputtering, vacuum deposition, or optical CV
Any method that can form a predetermined precursor, such as Method D, may be used.

In the first and second embodiments, XeCl laser light is applied to crystallize the precursor of the semiconductor layer. However, any method can be used as long as the precursor can be crystallized. Irradiation or thermal annealing in a furnace may be used.

In the first and second embodiments, polycrystalline silicon is used as the semiconductor layer. However, any material that functions as a semiconductor may be used, such as amorphous silicon, microcrystalline silicon, single crystal silicon, germanium, silicon germanium. Or gallium arsenide.

In the first and second embodiments, SiO2 formed by the normal pressure CVD method is used as the gate insulating layer, but any material may be used as long as it is silicon oxide.
VD method, plasma CVD method, sputtering method, or ECR
-Silicon oxide or the like formed using a film formation technique such as a CVD method may be used.

In the second embodiment, TaOx formed by a sputtering method is used as a gate insulating film. However, any material can be used as long as it functions as a gate insulating layer. For example, low-pressure CVD, plasma CVD, sputtering, Alternatively, S formed by using a film forming technique such as ECR-CVD
iNx or the like may be used.

In the first and second embodiments, the first gate electrode 5 is made of 10 atomic% of Mo-W, but is made of a material containing Mo as a main component, which can be etched with nitric acid and which is made of phosphoric acid. Whatever is not etched,
Mo or an alloy containing Mo as a main component and containing at least 0.5 atomic% or more and 30 atomic% or less of W may be used.

In the first and second embodiments, the second gate electrode 6 is made of 0.9 atomic% of Al—Zr,
However, any metal may be used as long as it is a metal containing Al as a main component.
An alloy containing at least 10 atomic% and not more than atomic% may be used. For example, an alloy containing Al as a main component and containing at least Nd at least 2 atomic% and not more than 5 atomic% may be used.

In the first and second embodiments, an ion doping method is used as a method for introducing a predetermined element. However, any method capable of introducing a predetermined element may be used. It may be a law.

In the first and second embodiments, phosphorus is used as a donor for forming the source / drain regions. However, in the case of manufacturing an n-channel thin film transistor, any material that functions as a donor such as arsenic may be used. In the case of manufacturing a p-channel thin film transistor, any material that works as an acceptor, such as aluminum or boron, may be used.

In the first and second embodiments, the laminated film of Ti and Al is used as the source / drain electrodes. However, any film that functions as an electrode may be used.
A transparent conductive layer such as polycrystalline silicon or ITO that is heavily doped with a metal such as Cr, Ta, Mo, or Al or an impurity may be used.

In the first and second embodiments, SiO2 formed by the normal pressure CVD method is used as the interlayer insulating layer. However, any material can be used as long as it functions as an insulating layer. For example, low pressure CVD method, plasma CVD method, Silicon nitride, tantalum oxide, or the like formed using a film formation technique such as a sputtering method or an ECR-CVD method may be used.

In the first and second embodiments, a glass substrate is used, but any glass substrate may be used as long as it has an insulating surface, such as a plastic substrate, a crystalline silicon substrate having silicon oxide formed on the surface, a metal plate, or the like. May be.

In the first and second embodiments, the step of selectively etching the second gate electrode layer involves phosphoric acid: water =
A ratio of 16: 3 (volume ratio) was used as long as the etching selectivity of the second gate electrode layer 6 was sufficient for the first gate electrode layer 5, for example, phosphoric acid, acetic acid and water. Or an alkaline etching solution containing tetramethylammonium hydroxide (TMAH) as a main component.

[0056]

As described above, according to the present invention, it is possible to control the shape of the end face of the gate electrode of the laminated layer of the lower metal film mainly composed of Mo and the upper metal film mainly composed of Al, and An effective effect of being able to manufacture a thin film transistor which does not deteriorate the insulating characteristics of the present invention can be obtained.

[Brief description of the drawings]

FIG. 1 is a cross-sectional view illustrating a manufacturing process of a thin film transistor in Embodiment 1 of the present invention.

FIG. 2 is a sectional view of a manufacturing process of a thin film transistor according to Embodiment 2 of the present invention.

FIG. 3 is a sectional view of a conventional thin film transistor.

[Explanation of symbols]

 REFERENCE SIGNS LIST 1 glass substrate 2 semiconductor layer 3 source / drain region 4 gate insulating layer 5 first gate electrode layer 6 second gate electrode layer 7 photoresist 8 interlayer insulating layer 9 source / drain electrode 10 LDD region

Continued on the front page (51) Int.Cl. ⁶ Identification symbol FI H01L 21/3205 H01L 21/88 R 21/336 29/78 617V (72) Inventor Ikunori Kobayashi 1006 Kazuma, Kazuma, Osaka Matsushita Electric Industrial Co., Ltd. In company

Claims (15)

[Claims] In a pattern formation of a laminated film of a lower metal film mainly composed of Mo and an upper metal film mainly composed of Al, a step of etching the laminated film at a time,
A process of selectively etching the upper metal film mainly composed of: and processing the upper metal film into a predetermined shape. 2. The lamination according to claim 1, wherein in the step of selectively etching the upper metal film mainly containing Al and processing it into a predetermined shape, etching is performed with an etching solution containing at least phosphoric acid. Method of processing the shape of the film. 3. The laminated film according to claim 1, wherein in the step of selectively etching the upper metal film containing Al as a main component and processing it into a predetermined shape, the upper metal film is etched with an organic alkaline etchant. Shape processing method. 4. The step of selectively etching an upper metal film containing Al as a main component and processing it into a predetermined shape is characterized by etching with an alkaline etching solution containing at least tetramethylammonium hydroxide. The method for processing the shape of a laminated film according to claim 1. 5. The metal film according to claim 1, wherein the lower metal film containing Mo as a main component is an alloy containing at least 0.5 atomic% and not more than 30 atomic% of W. Of forming a laminated film. 6. The method according to claim 1, wherein the upper metal film mainly composed of Al is an alloy containing at least 0.5 at% and at most 10 at% of Zr. Of forming a laminated film. 7. The lamination according to claim 1, wherein the upper metal film containing Al as a main component is an alloy containing at least 2 at% to 5 at% of Nd. Method of processing the shape of the film. 8. A manufacturing process of a thin film transistor in which a semiconductor layer, a gate insulating layer, and a gate electrode are sequentially stacked on an insulating substrate, wherein the step of forming the gate electrode includes the step of forming a lower metal film containing Mo as a main component. A step of depositing a laminated film with an upper metal film containing Al as a main component, a step of etching the laminated film at a time and processing it into a predetermined shape, and removing Al while leaving an etching mask material used at the time of the etching. A method for manufacturing a thin film transistor, comprising a step of selectively etching an end face of the upper metal film as a main component. 9. A manufacturing process of a thin film transistor in which a semiconductor layer, a gate insulating layer, and a gate electrode are sequentially stacked on an insulating substrate, wherein the step of forming the gate electrode comprises the steps of: A step of depositing a laminated film with an upper metal film mainly composed of Al, a step of etching the laminated film at a time and processing it into a predetermined shape, and selectively depositing the upper metal film mainly composed of Al. A method for manufacturing a thin film transistor, comprising a step of etching and removing. 10. A step of selectively etching an upper metal film mainly containing Al and processing it into a predetermined shape,
10. The method of manufacturing a thin film transistor according to claim 8, wherein the etching is performed with an etching solution containing at least phosphoric acid. 11. In a step of selectively etching an upper metal film mainly containing Al and processing it into a predetermined shape,
10. The method for manufacturing a thin film transistor according to claim 8, wherein etching is performed with an organic alkaline etching solution. 12. In a step of selectively etching an upper metal film mainly containing Al and processing it into a predetermined shape,
10. The method of manufacturing a thin film transistor according to claim 8, wherein etching is performed with an alkaline etching solution containing at least tetramethylammonium hydroxide. 13. The lower metal film containing Mo as a main component is an alloy containing at least W of 0.5 at% or more and 30 at% or less. Method for manufacturing thin film transistor. 14. The method according to claim 8, wherein the upper metal film containing Al as a main component is an alloy containing at least 0.5 at% and not more than 10 at% of Zr. Method for manufacturing thin film transistor. 15. The thin film transistor according to claim 8, wherein the upper metal film containing Al as a main component is an alloy containing at least 2 at% and 5 at% or less of Nd. Manufacturing method.