JP2002110631A - Manufacturing method of multi-layer thin film pattern - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a multi-layer film pattern which can fully prevent generation of an overhang part which overhangs from an end plane of a multi-layer film pattern, as well as generation of a failure caused by that overhang in the manufacturing method of a multi-layer film including a process of patterning the multi-layer film pattern in batch using one photomask. SOLUTION: When the patterning of a multi-layer film, composed of a metal film 5 and an amorphous ITO film 4 which covers the metal film 5, is performed, a sequence of processes is executed as follows: (a) etching of the ITO film 4→(b) sufficient etching of the metal film 5→(c) etching to remove overhang part from the metal film 5 of the ITO film 4. Otherwise a sequence of processes as follows is executed: (a) etching of the ITO film 4 under a resist pattern prior to post baking→(b) extension of the resist pattern by the post baking→(c) etching of the metal film 5 under the resist pattern after the post- baking.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] The present invention relates to a method for manufacturing a multilayer thin film pattern. In particular, the present invention relates to a method of collectively patterning a multilayer thin film under one resist pattern in order to manufacture an array substrate for an active matrix liquid crystal display device.

[0002]

2. Description of the Related Art In recent years, flat display devices have been actively developed as display devices replacing CRT displays. Among them, liquid crystal display devices have attracted attention because of their advantages such as light weight, thinness, and low power consumption. . In particular, an active matrix liquid crystal display device in which a switch element is electrically connected to each pixel electrode can realize a good display image without crosstalk between adjacent pixels, and thus has become the mainstream of liquid crystal display devices. I have.

As a switch element provided for each pixel electrode, a thin film transistor (TFT) is generally used.
Amorphous silicon (a-Si: H) is generally used for the semiconductor active layer of this TFT.
It has been studied to integrally form a driving circuit on an array substrate on which pixel electrodes and the like are arranged. In this case, polysilicon (multi-layer) having higher electron mobility than amorphous silicon (a-Si: H) is used. Crystalline silicon) is used as a semiconductor active layer of a TFT.

In the manufacture of a liquid crystal display device, the production cost of an array substrate is high. In particular, the cost of members and processes for producing a TFT having a multilayer film pattern on the array substrate occupies a large portion. Therefore, TFT
It is important to simplify the manufacturing process of the array substrate and reduce the cost.

Therefore, the production of TFTs and array substrates is
Techniques have been introduced to reduce the number of photomasks and photolithography steps to shorten the manufacturing process and significantly improve productivity. Thus, the TFT
In order to manufacture a pattern necessary for forming an array substrate by a small number of patterning, a multilayer film made of a plurality of different materials is formed by using a single photomask, that is, the same resist pattern. Under this, patterning is performed collectively.

[0006]

However, when a multilayer film is continuously etched under the same resist pattern, the degree of side etching of the lower film is less than the degree of side etching of the upper film adjacent thereto. If it is larger, the edge of the upper film may protrude outside the contour of the lower film in an eave (eave) shape.

An example in which the “eave portion” (overhang portion) is formed will be further described with reference to an example shown in FIG.

In the example shown in FIG. 10, the multilayer film is formed of a metal film 5
And a transparent conductive material film 4 directly covering this. After the formation of the resist pattern 9, patterning is first performed on the transparent conductive material film 4, and then patterning is performed on the metal film 5 under the same resist pattern 9. Since it is generally difficult to efficiently and efficiently etch the transparent conductive material film 4 and the metal film 5 at the same time, patterning is performed using an etching agent that selectively etches each of them.

However, as shown in FIG. 7, when the side etching of the lower metal film 5 is larger than the side etching of the upper transparent conductive material film 4, the transparent conductive material film 4 moves to the outside of the pattern. An overhanging "eave portion" is formed.

As described above, when the "eave portion" is formed on the end face of the pattern of the obtained multilayer film, the "eave portion" is peeled off in the step of peeling off the resist pattern or the cleaning step after completion of the etching. Generates dust (dust) and causes defects such as short circuits.

Further, when the end face of the multilayer film pattern is covered with the coating film, a problem occurs in that the coating film cracks at the place where the eaves are formed, that is, a so-called “step break”. When the covering film is a protective insulating film, insulation failure occurs at the stepped portion, and when the covering film is a conductive film, electrical connection fails at the stepped portion.

In patterning the multilayer film in a lump, it is necessary to select a limited specific material for the material and etching method of the thin film in order to prevent the formation of the eaves portion. For this reason, the degree of freedom regarding the structure and the material of the active matrix type display device is significantly reduced.

It is conceivable to extend the over-etching time of the upper transparent conductive material film 4 extremely to perform the same side etching as that of the lower metal film 5. However, in general, the transparent conductive material film 4
Side etching speed is low, and even if over-etching is performed for a considerably long time, the size of side etching is often not sufficient. In particular, since the thickness of the transparent conductive material film 4 is relatively small, sufficient side etching may not proceed even after an extremely long time due to the problem of penetration of the etching solution.

On the other hand, if each of the thin films forming the multilayer film is subjected to film formation → preparation of a resist pattern by photolithography → patterning by etching, no eaves are formed, but productivity is greatly increased. This leads to a decrease and an increase in production costs.

SUMMARY OF THE INVENTION The present invention has been made in view of the above-mentioned problems, and has a method of manufacturing a multilayer film pattern including a step of collectively patterning a multilayer film using one photomask. Provided is one that can sufficiently prevent generation of an eave portion (overhang portion) at an edge portion and occurrence of a defect due to the generation.

[0016]

According to a first aspect of the present invention, there is provided a method of manufacturing a multilayer thin film pattern, comprising: depositing a first thin film and a second thin film directly covered by the first thin film on an insulating substrate to form a multilayer film. A step of forming one resist pattern on the multilayer film, and a step of sequentially etching the first and second thin films under the one resist pattern. A first etching step of patterning the first thin film;
A second etching step of patterning the thin film, and after the second etching step, by selectively etching the pattern of the first thin film, the contour of the pattern of the first thin film is adjusted in the resist pattern. A third etching step of inwardly receding.

According to the above configuration, generation of an overhang portion (overhang portion) at the edge of the multilayer film pattern and occurrence of a defect due to this can be sufficiently prevented.

According to a first aspect of the present invention, there is provided a method of manufacturing a multilayer thin film pattern, comprising: depositing a first thin film and a second thin film directly covered by the first thin film on an insulating substrate to form a multilayer film; A step of forming one resist pattern thereon,
Under this one resist pattern, the first and second resist patterns are used.
A step of sequentially etching the thin films of the above, wherein before the post-bake is performed on the one resist pattern, a pre-bake etching step of patterning the first thin film by etching, and a heat treatment are performed. By applying, while expanding the outline of the one resist pattern to the outside,
It is characterized by comprising a post-baking step of completing the thermal curing of the resist material, and a post-baking etching step of patterning the second thin film after the post-baking step.

According to the above configuration, it is also possible to sufficiently prevent the formation of the eaves at the edge of the multilayer film pattern and the occurrence of defects due to the formation.

[0020]

DESCRIPTION OF THE PREFERRED EMBODIMENTS <First Embodiment> First, a thin film transistor (TFT) obtained by the manufacturing method of the present embodiment.
And an array substrate for a liquid crystal display device including the same,
The outline will be described with reference to FIGS.

FIG. 1 is a cross-sectional perspective view schematically showing the structure of a TFT forming portion and its vicinity. FIG. 2 is a plan view schematically showing a configuration of each pixel on an array substrate including a TFT.

On the array substrate 10, a plurality of signal lines 21 arranged substantially in parallel at equal intervals and a plurality of scanning lines 11 arranged in substantially parallel and at equal intervals are arranged so as to be orthogonal to each other. The pixel electrodes are arranged in a matrix in each of the grid-shaped sections formed by the above. In each of the sections, a TFT 7 as a switching element is arranged near an intersection between the signal line 21 and the scanning line 11.

The TFT 7 is of an inverted staggered back channel type in the specific example shown. That is, the glass substrate 18
Above the upper gate electrode 11a, the gate insulating films 15, 2
A trough-shaped back channel portion 45 is located with the back channel portion 45 interposed therebetween with the semiconductor film 26 interposed therebetween.
A source electrode 23 and a drain electrode 22 are arranged.

As shown in the figure, the extension of the scanning line 11 forms the gate electrode 11a of the TFT 7, and the first and second gate insulating films 15 are formed on the scanning line 11 including the gate electrode 11a. , 25, a semiconductor film 26 made of amorphous silicon (a-Si: H) is arranged. A low-resistance semiconductor film 27 made of phosphorus-doped amorphous silicon (n ⁺ a-Si: H) is stacked on the semiconductor film 26 except for a portion corresponding to the bottom surface of the back channel portion 45. Further thereon, a source electrode 23 and a drain electrode 22 made of the metal film 5 are arranged. In the specific example shown, the metal film 5 is a three-layer metal film in which a metal aluminum (Al) layer is sandwiched between upper and lower metal molybdenum (Mo) layers.

The second gate insulating film 25 in the TFT 7,
The contours of the semiconductor film 26, the low-resistance semiconductor film 27, and the source electrode 23 and the drain electrode 22 made of the metal film 5 are substantially the same except for the back channel portion 45. The signal line 21 connected to the drain electrode 22 is also connected to the source electrode 2
Like the third electrode 3 and the drain electrode 22, it is made of the metal film 5, and is superimposed on the three-layer non-metal film whose contour substantially coincides with the signal line 21. The signal line 21, the drain electrode 22, and the source electrode 23 are formed by collectively patterning the metal film 5 and the three-layer nonmetal film 6 under one resist pattern (etching mask). is there.

On the other hand, the back channel portion 45 of the TFT 7
Is an IT for forming the pixel electrode 42, the source covering ITO film (pixel electrode extending portion) 42a, and the protective ITO film 41.
The O film 4, the metal film 5 before being separated into the source electrode 23 and the drain electrode 22, and the amorphous silicon film 61 forming the low-resistance semiconductor film 27 are collectively formed under another resist pattern. It is provided by patterning.

The patterning for providing the pixel electrode 42 and the back channel portion 45 is performed as described below.
(a) Etching of ITO film 4 with oxalic acid aqueous solution → (b)
Etching of the metal film 5 with a water-containing mixed acid consisting of phosphoric acid, nitric acid, acetic acid and water → (c) I with an aqueous oxalic acid solution again
This is performed by selective etching of the TO film 4 (FIG. 3).
~ 5).

(A) First Etching (Etching to Pattern ITO Film 4, FIG. 3) After depositing an amorphous ITO film, a photoresist material is coated, and a predetermined resist pattern is formed by photolithography using a mask pattern. Form. Thereafter, it is completely cured by a heat treatment called post-baking, and the adhesion to the substrate is strengthened.

Thereafter, the ITO film 4 is patterned by wet etching using an oxalic acid aqueous solution containing a surfactant and an antifoaming agent at a liquid temperature of 45 ° C.

At the time of this etching, about 100% over-etching is performed using an end point monitor. That is, the etching time is extended by about 100% based on the time of the just etching for etching to the contour of the resist pattern. The end point monitor captures the change in the amount of reflected light or transmitted light and reads the change in the amount of reflected light or transmitted light.
Is to detect the point at which is exposed.

In a specific example, etching with an oxalic acid aqueous solution was performed for 50 seconds. As a result, side etching of about 0.2 μm was performed.

Even if 200% over-etching is performed under the same conditions as in the specific example, the pattern of the ITO film 4 is reduced only by about 0.3 μm from the edge of the resist pattern. There was no big difference from the case where it was performed.

(B) Second Etching (Etching for Patterning Metal Film 5, FIG. 4) Next, the array substrate being manufactured is moved to another etching chamber.
Then, the metal film 5 is patterned by wet etching using an aqueous mixed acid composed of phosphoric acid, acetic acid and nitric acid.

In this etching step, sufficient over-etching must be performed in order to prevent the leakage current of the TFT 7 due to the metal film remaining without being etched.

When the metal film 5 is a three-layer metal film (Mo / Al / Mo) as shown in the figure, the etching rate is reduced to reduce side etching (undercut) of the bottom Mo layer. It is preferable to perform wet etching by a shower method.

A preferred composition of the mixed acid is, for example, if the following acid aqueous solution is mixed in the following range, or
It can be obtained if an appropriate amount of water is added.

85% phosphoric acid aqueous solution 71 ± 20% by volume (v / v%) 70% nitric acid aqueous solution 1 to 20% by volume 90% acetic acid aqueous solution 5 to 30% by volume In the specific example, the above mixed acid solution was used and 140% Was over-etched. At this time, the time from the start of the second etching to the end of the overetching was 120 seconds. At the end of the overetching, the pattern of the three-layer metal film 5 (Mo / Al / Mo) is changed to the resist pattern 9.
Was smaller by about 0.9 μm from the edge of.

Therefore, at the end of the second etching, the pattern of the ITO film 4 is changed to the three-layer metal film 5 (Mo / Al / M
An eaves portion (overhang portion) is formed to protrude from the upper end of the end face of the pattern of FIG.

In the case of this embodiment, the thickness of the lower metal film 5 is much larger than the thickness of the ITO film 4 and the lower metal film 5 is isotropically etched by wet etching. Because of this, the dimension in which the upper end of the end face of the metal film 5 pattern is drawn into the inside of the resist pattern 9, that is, the side etching dimension of the metal film 5 pattern is large, is a major cause of the formation of the eaves. Another cause is that the side etching of the ITO film 4 is difficult to progress even when the ITO film 4 has a small thickness and a considerable over-etching time is taken due to a problem such as penetration of an etching solution. Further, the metal film 5
Any residue will adversely affect product performance,
The need to perform sufficient over-etching on the metal film 5 is also a cause of the formation of the eaves.

(C) Third etching (again ITO film 4)
Etching, FIG. 5) Using the same etching solution as in the first etching,
The etching of the pattern of the O film 4 is performed again.
Thus, even if the edge of the pattern of the metal film 5 extends outward after the second etching to form an “eave portion”, such an eave portion is surely removed by the third wet etching. Can be.

In the third etching, the "eave portion" made of the ITO film 4 is subjected to wet etching from the lower surface side, and is called etching using the lower metal film 5 having a large side etching dimension as a mask. You can also.

In the specific example, the etching was performed for 20 seconds corresponding to 80% of the just etching time in the first etching.

Hereinafter, a method of manufacturing a thin film transistor and an array substrate according to the embodiment will be described in more detail.

(1) First Patterning Transparent insulating substrate 18 made of glass of 360 × 465 mm
On this, a molybdenum-tungsten alloy film (MoW film) is deposited to a thickness of 230 nm by a sputtering method. And the first
600 using a mask pattern of
Scanning lines 11 and gate electrodes 11 formed by extending the scanning lines 11
a, and approximately the same number of auxiliary capacitance lines 12 as the scanning lines 11 are formed (see FIG. 2). At the same time, the scanning line connection pads 11b are formed on the connection peripheral portion 10a of the array substrate 10 (see the right part of FIGS. 2 and 6).

(2) Second patterning 350 n forming the first gate insulating film 15 by the CVD method
a 50 nm thick silicon nitride film 63 and TF which form a second gate insulating film 25;
An amorphous silicon (a-Si: H) layer 62 having a thickness of 250 nm for forming the semiconductor film 26 of T7 and a phosphorus-doped amorphous silicon (n ⁺ a-Si) having a thickness of 50 nm for forming the low-resistance semiconductor film 27. : H) Layer 61
Films are formed continuously without exposure to the atmosphere.

Thereafter, a Mo layer 51 having a thickness of 25 nm, an Al layer 52 having a thickness of 350 nm, and 50 n
A metal film 5 composed of a Mo layer 53 having a thickness of m is deposited.

Then, using the second mask pattern,
After exposing and developing the resist, the silicon nitride film 6
3. The a-Si: H layer 62, the n ⁺ a-Si: H layer 61, and the metal film 5 are collectively patterned. By this second patterning, 800 × 3 signal lines 21, a drain electrode 22 extending from each signal line 21, and a source electrode 23 still connected to the drain electrode 22 are formed (FIG. 2 and FIG. 2). See FIG. 6). Although not shown in the figure, signal line pads (including lead lines from the signal lines 21) drawn from the signal lines 21 are simultaneously formed in the peripheral connection region of the array substrate 10.

First, the three-layer metal film 5 was etched with a mixed hydrous acid composed of nitric acid, phosphoric acid, and acetic acid.

Next, the silicon nitride film 63, a-Si: H
For layer 62, n ⁺ a-Si: H layer 61, sulfur hexafluoride (SF ₆ ), hydrogen chloride (HCl), and helium (H
e) plasma etching using a mixed gas
tching, PE) or reactive ion etching (reacti
(Veion etching, RIE).

(3) Third Patterning Using the third mask pattern, the scanning line pad portion 11b
A through-hole 31 is formed to expose the upper surface of FIG.
(See right). At this time, the first gate insulating film 15 on the scanning line pad portion 11b is removed by wet etching using a hydrofluoric acid aqueous solution containing ammonium fluoride.

(4) Fourth patterning (4-1) Deposition of amorphous ITO film 4 and formation of resist pattern An amorphous ITO layer having a thickness of 40 nm is deposited on the entire surface of the substrate by sputtering. Next, a predetermined resist pattern 9 is formed using the fourth mask pattern.
Thereafter, post baking is performed.

(4-2a) Patterning of the Amorphous ITO Film 4 The protective ITO film 41 is formed under the resist pattern 9 by wet etching at 45 ° C. using an aqueous oxalic acid solution containing a surfactant and an antifoaming agent. And the pixel electrode 42
And a source-covered ITO film 42a extending therefrom. The protective ITO film 41 reliably covers the upper surface and the end surface of the signal line 2 (the center part in FIG. 6) and covers the upper surface of the drain electrode 22 (the upper left part in FIG. 6). The source-covered ITO film 42a extends from the pixel electrode 42 to cover the source electrode 23 and the end face on the pixel electrode side, thereby performing conduction between the source electrode 23 and the pixel electrode 42.

At the time of this patterning, in the peripheral connection region of the array substrate 10, a pad portion ITO film 43 (right portion in FIG. 6) covering each scanning line pad 11b and a pad portion ITO film covering each signal line pad are provided. Each is formed.

(4-2b) Patterning of Metal Film 5 At the place where the back channel portion 45 of the TFT is formed, the metal film 5 (groove) is formed in a groove shape by wet etching using a mixed acid containing water containing phosphoric acid, acetic acid and nitric acid. Mo / Al / Mo).

(4-2c) Re-Etching of the Amorphous ITO Film 4 Re-etching is performed using the same etching solution as used for the above-described patterning of the amorphous ITO layer.

(4-2d) Etching of n ⁺ a-Si: H layer 61 At a portion corresponding to the groove bottom of the back channel portion 45, n ⁺ a-
By removing the Si: H layer 61, the drain electrode 2
2 and the source electrode 23 are completely separated to complete the TFT 7. For this removal, sulfur hexafluoride (S
Plasma etching using a mixed gas of F ₆ ), hydrogen chloride (HCl), and helium (He) is performed.

(4-3) Stripping of resist pattern 9 and annealing treatment After stripping and removing the resist pattern 9, annealing is performed by heating to convert the ITO film 4 from an amorphous state to a microcrystalline state. By this annealing, at the same time, T
The FT characteristics are stabilized.

<Second Embodiment> The second embodiment differs from the first embodiment only in the patterning step for providing the back channel portion 45, and is completely the same in other points. Therefore, only the patterning process will be described.

As described in detail below, the patterning for providing the pixel electrode 42 and the back channel portion 45 is performed by (a) etching the ITO film 4 with an oxalic acid aqueous solution under the resist pattern before post-baking → (b) Enlargement of resist pattern by post-bake → (c) Phosphoric acid, nitric acid,
The etching is performed by etching the metal film 5 with an aqueous mixed acid solution composed of acetic acid and water.

(A) Etching of ITO film 4 (FIG. 7) After depositing the amorphous ITO film, a photoresist material is coated, and a predetermined resist pattern 91 is formed by photolithography using a mask pattern.

Thereafter, the ITO film 4 is patterned by wet etching using an aqueous oxalic acid solution containing a surfactant and an antifoaming agent at a liquid temperature of 45 ° C. without performing a heat treatment called post-baking.

At the time of this etching, about 200% over-etching is performed using an end point monitor. That is, the etching time is increased by about 200% based on the time of the just etching for etching to the contour of the resist pattern.

In the specific example, etching with an oxalic acid aqueous solution was performed for 75 seconds. As a result, side etching of about 0.3 μm was performed.

(B) Post-bake (FIG. 8) A heat treatment is performed on the array substrate in the process of manufacturing, with the resist pattern 91 still attached. This heat treatment can be performed under the same conditions as in the case of ordinary post baking as in the first embodiment. For example, an oven for post bake treatment included in a normal resist pattern developing device can be used.

The heat treatment completes the curing of the material of the resist pattern 91 and increases the adhesion to the lower surface in the same manner as in the ordinary post-baking, and the heat treatment is performed so that the resist pattern 91 extends outside the pattern. It is to be deformed. The resist pattern 91 includes the above IT
When the O film 4 is etched, the etchant penetrates and swells, and the hem portion is further deformed and pushed outward by the heat treatment.

In a specific example, the array substrate was placed on a hot plate and heated at 130 ° C. for 200 seconds. In the resist pattern 92 after the heat treatment, each contour line extends to the outside of the pattern by about 0.6 μm as compared to before the etching of the ITO film 4. Therefore, the outline of the resist pattern 92 is different from the outline of the pattern of the ITO
It protrudes outward by about 0.9 μm.

(C) Etching of Metal Film 5 (FIG. 9) Next, under the resist pattern 92 after post-baking,
The metal film 5 is patterned by wet etching using an aqueous mixed acid composed of phosphoric acid, acetic acid and nitric acid.

In this etching step, sufficient over-etching must be performed in order to prevent a leakage current of the TFT 7 due to the metal film remaining without being etched. When the metal film 5 is a three-layer metal film (Mo / Al / Mo) as shown in the drawing, a shower method is used to reduce side etching (undercut) of the bottom Mo layer by reducing the etching rate. It is preferable to perform wet etching by The preferred composition of the mixed acid is the same as that described in the first embodiment.

In a specific example, the above mixed acid solution was used,
% Over-etching was performed. At this time, the etching time by the mixed acid containing water was 120 seconds. Also,
At the end of over-etching, the three-layer metal film 5 (Mo / Al / M
The upper end of the end face of the pattern (o) was located inside the pattern by about 0.8 to 0.9 μm from the edge of the resist pattern 92.

At the end of the second etching, the upper end of the end face of the pattern of the three-layer metal film 5 (Mo / Al / Mo) substantially matches the contour of the pattern of the ITO film 4 or slightly inside the pattern. Located in.

<Effects of First and Second Embodiments> According to the manufacturing methods of the first and second embodiments described above, an array substrate for a display device can be manufactured by patterning only four times. And the metal film 5 and the ITO film 4
Thus, it is possible to sufficiently prevent the eaves portion 8 (overhang) from being generated or remaining on the end face of the pattern obtained by patterning all at once. For this reason, it is prevented that this portion is peeled off after the etching to generate a conductive foreign matter which causes a failure such as a short circuit or an interlayer insulation failure. In addition, since the eaves portion 8 is removed and the end surface of the metal film 5 can be formed into a gentle taper, when a protective insulating film covering the TFT 7 and the pixel electrode 42 is provided, the protective insulating film is formed by the back channel portion 45 and other parts. Ensure that the end face is covered.

In particular, according to the manufacturing method of the embodiment, the TFT
Thus, the degree of freedom in selecting the material, the laminated structure, and the etching conditions of the multilayer film constituting the layer 7 and the like can be remarkably increased.

In the above embodiment, the case where the end face of the obtained pattern is covered with the insulating protective film has been described, but the case where the end face is covered with the conductive film is exactly the same.

Further, in the above embodiment, the metal film
Although the patterning of the multilayer film composed of the amorphous ITO film directly covering this is described, the same applies to the patterning of the multilayer film composed of the metal film and the insulating film and other films. Further, in the above embodiment, each thin film of the multilayer film is etched by wet etching. However, etching by dry etching may be included in the process.

Further, in the above embodiment, the end surface of the obtained multilayer film pattern is tapered. However, when it is not necessary to cover the end surface reliably, the end surface of the multilayer film pattern may be attached to the substrate. It may be almost vertical.

In the above description, the case of an array substrate for a liquid crystal display device has been described as an example. However, a thin film transistor used for other purposes such as an organic EL array substrate can be manufactured by the same method. . In some cases, the manufacturing method of the present invention can be applied to semiconductor devices other than thin film transistors.

[0077]

According to the present invention, in a method of manufacturing a multilayer film pattern including a step of collectively patterning a multilayer film using one photomask, generation of an eave portion (overhang portion) at an end face of the multilayer film pattern, and The occurrence of defects due to this can be sufficiently prevented.

[Brief description of the drawings]

FIG. 1 is a cross-sectional perspective view schematically illustrating a configuration of a TFT forming portion and its vicinity.

FIG. 2 is a plan view schematically showing a configuration of each pixel on an array substrate including a TFT.

FIG. 3 is a schematic longitudinal sectional view showing a state after the first etching in the first embodiment, that is, a state after patterning the ITO film 4 with an oxalic acid aqueous solution.

FIG. 4 shows a state after the second etching in the first embodiment, that is, a state after patterning the non-metal film 5 with a mixed hydrate containing phosphoric acid, nitric acid, acetic acid and water. FIG. 3 is a schematic longitudinal sectional view corresponding to FIG.

FIG. 5 is a schematic longitudinal sectional view corresponding to FIG. 3 and showing a state after a third etching in the first embodiment. That is, it is a schematic diagram showing a state after the selective etching of the ITO film with the oxalic acid aqueous solution again.

FIG. 6 is a schematic longitudinal sectional view corresponding to FIG. 3, showing a state when the array substrate is completed.

FIG. 7 is a schematic longitudinal sectional view showing a state after patterning an ITO film 4 under a resist pattern before post-baking in a second embodiment.

FIG. 8 is a schematic longitudinal sectional view showing a state after enlargement of a resist pattern by post baking according to a second embodiment.

FIG. 9 is a schematic longitudinal sectional view showing a state after a metal film is patterned under a resist pattern after post-baking in the second embodiment.

FIG. 10 is a vertical cross-sectional view of a thin film transistor on an array substrate, for explaining an “eave portion” generated by a conventional technique.

[Explanation of symbols]

10 Array substrate 11 Scanning line 21 Signal line 22 Drain electrode 23 extended from signal line 23 Source electrode 15 First gate insulating film 25 Second gate insulating film 26 Semiconductor film of TFT 27 Low resistance semiconductor film 41 Protection covering signal line ITO film 42 Pixel electrode 42a Source covering ITO film extending from the pixel electrode and covering the pattern of the source electrode 43 ITO film for pad 45 Back channel part of TFT 5 Metal film (Mo / Al / Mo) 6 Three-layer nonmetal film (N ⁺ a-Si: H layer, a-Si: H layer and silicon nitride film) 7 TFT 8 Eave portion (overhang portion) 9 Resist pattern 91 Resist pattern before post-baking 92 Resist pattern after post-baking

 ──────────────────────────────────────────────────続 き Continuing on the front page (72) Inventor Yasuyuki Imamura 7-1, Nisshincho, Kawasaki-ku, Kawasaki-shi, Kanagawa Prefecture Inside Toshiba Electronics Engineering Co., Ltd. F-term in the Toshiba Himeji Plant (reference) QQ10

Claims (7)

[Claims] 1. A step of depositing a first thin film and a second thin film directly covered thereon on an insulating substrate to form a multilayer film, and forming one resist pattern on the multilayer film. And a step of sequentially etching the first and second thin films under the one resist pattern, a first etching step of patterning the first thin film, A second etching step of patterning a second thin film; and after the second etching step, by selectively etching the pattern of the first thin film, the contour of the pattern of the first thin film is formed by the resist. A third etching step of receding inward in the pattern. 2. The method according to claim 1, wherein after the second etching step, the first thin film pattern is moved from the upper end of the end face to the first thin film pattern.
An eaves portion is formed in which the pattern of the thin film extends outward, and the eaves portion is removed in the third etching step by using the same etchant used in the first etching step. The method for producing a multilayer thin film pattern according to claim 1. 3. A step of depositing a first thin film and a second thin film directly covered thereon on an insulating substrate to form a multilayer film, and a step of forming one resist pattern on the multilayer film. And a step of sequentially etching the first and second thin films under the one resist pattern, wherein the post-baking is performed on the one resist pattern by etching. A pre-bake etching step of patterning the first thin film, and a heat treatment to push out the outline of the one resist pattern to the outside and a post-bake step of completing thermosetting of the resist material; A post-baking etching step of patterning the second thin film after the post-baking step. Manufacturing method of a multilayer thin film pattern. 4. The side etching dimension of the pattern of the first thin film and the side etching dimension of the pattern of the second thin film, wherein the dimension in which the outline of the one resist pattern is expanded by the post-baking step is set. 4. The method according to claim 3, wherein the total is substantially equal to the sum of 5. After the third etching step or the post-bake etching step, an outer edge of an end face in the pattern of the first thin film is inside an inner edge of an end face in the pattern of the first thin film. The method for manufacturing an array substrate according to claim 1, wherein: 6. The method according to claim 1, wherein the second thin film is patterned by wet etching. 7. The thin film transistor according to claim 1, wherein the first thin film is an ITO film, and the second thin film is a metal film forming a source electrode and a drain electrode of the thin film transistor.
Or the method for producing a multilayer thin film pattern according to 3.