JP2012018970A - Thin film transistor array substrate, manufacturing method of the same and liquid crystal display device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a thin film transistor array substrate, a manufacturing method of the same and a fringe field switching (FFS) mode liquid crystal display device, which can reduce the number of photolithography processes without using a semi-transparent mask and prevent disconnection.SOLUTION: The thin film transistor array substrate of the present invention comprises: source wiring 44 formed on a gate insulation film 11 covering gate wiring 43; a semiconductor layer 2 formed on the gate insulation film 11 and disposed on almost whole area below a drain electrode 5, on almost whole area below a source electrode 4, on almost whole area below the source wiring 44 and on a counter face of a gate electrode; a pixel electrode 6 formed directly on the drain electrode 5 partially overlaid; a transparent conductive pattern 6a formed directly on the source electrode 4 and the source wiring 44 by the same layer with the pixel electrode 6 overlaid; and a counter electrode 8 formed on an interlayer insulation film 12 covering the pixel electrode 6 and the transparent conductive pattern 6a for generating a fringe electric field between the counter electrode 8 and the pixel electrode 6.

Description

The present invention relates to a thin film transistor array substrate, a manufacturing method thereof, and a liquid crystal display device, and more particularly to a thin film transistor array substrate used in a fringe field switching mode liquid crystal display device, a manufacturing method thereof, and a liquid crystal display device.

A fringe field switching (FFS) mode liquid crystal display device is a display system that performs display by applying a fringe electric field to liquid crystal sandwiched between opposing substrates. In the FFS mode liquid crystal display device, since the pixel electrode and the counter electrode are formed of a transparent conductive film, higher aperture ratio and transmittance can be obtained than in the in-plane switching (IPS) mode. (See Patent Document 1)

In a conventional FFS mode liquid crystal display device, a thin film transistor (TFT) array substrate is manufactured by (1) counter electrode, (2) gate electrode, (3) semiconductor layer, (4) source / drain. At least six photolithography processes are required for the electrode, (5) contact hole, and (6) pixel electrode. Therefore, there is a problem that the manufacturing cost is higher than that of a TN (Twisted Nematic) mode in which a TFT array substrate can be generally manufactured by five photolithography processes.

For such a problem, for example, Patent Document 2 proposes to reduce the number of photolithography processes by using a transflective mask. Further, in the array substrate of the conventional FFS mode liquid crystal display device, similar to the array substrate of a general liquid crystal display device, disconnection of the wiring occurs. For such a problem, for example, Patent Document 3 proposes that the wiring is covered with another film, for example, a transparent conductive film.

JP 2009-157368 A JP 2001-235863 A JP 2009-251070 A

However, the photolithography process using a transflective mask is complicated in process management as compared with a normal photolithography process, and there is a problem for stable mass production. In addition, the transflective mask is more expensive than a general mask and has a problem in terms of cost. Furthermore, in order to reduce the disconnection of the wiring, even if the wiring is covered with another different layer, a mask is additionally required for that purpose.

The present invention has been made to solve the above problems, and in the FFS mode liquid crystal display device, the number of photolithography processes can be reduced without using a transflective mask, and the wiring can be reduced. An object of the present invention is to provide a thin film transistor array substrate that can reduce disconnection, a manufacturing method thereof, and a liquid crystal display device.

A thin film transistor array substrate according to the present invention is a thin film transistor array substrate having a thin film transistor, and is formed on the substrate and connected to a gate electrode of the thin film transistor, and a gate insulating film covering the gate electrode and the gate wiring And a source wiring formed on the gate insulating film and connected to a source electrode of the thin film transistor, formed on the gate insulating film, substantially under the drain electrode of the thin film transistor, and below the source electrode A semiconductor layer disposed on substantially the entire surface, substantially the entire surface under the source wiring, and the opposite surface of the gate electrode, and a part thereof are directly formed on the drain electrode, and are electrically connected to the drain electrode. On the same layer as the pixel electrode on the pixel electrode to be connected, the source electrode and the source wiring Therefore, a transparent conductive pattern directly overlapped, an interlayer insulating film covering the pixel electrode and the transparent conductive pattern, a counter electrode formed on the interlayer insulating film and generating a fringe electric field between the pixel electrode, , Are provided.

The thin film transistor array substrate manufacturing method according to the present invention is a method of manufacturing a thin film transistor array substrate having a thin film transistor, wherein a gate electrode of the thin film transistor and a gate wiring connected to the gate electrode are formed on the substrate. Forming a gate insulating film covering the gate electrode and the gate wiring; forming a semiconductor layer, an ohmic contact film, and a metal film in this order on the gate insulating film; Patterning a metal film to form a source electrode and a drain electrode of the thin film transistor connected on the semiconductor layer to be a channel region of the thin film transistor, and a source wiring connected to the source electrode; And using the metal film as a mask, the semiconductor layer and the ohmic layer Etching the cross-contact film; forming a transparent conductive film directly overlying the metal film; patterning the transparent conductive film; and a pixel electrode partly directly overlying the drain electrode; Forming a transparent conductive pattern directly overlaid on the source electrode and the source wiring; and etching the metal film and the ohmic contact film using the pixel electrode and the transparent conductive pattern as a mask. A step of exposing the semiconductor layer serving as a channel region of the thin film transistor, a step of forming an interlayer insulating film covering the pixel electrode and the transparent conductive pattern, and the pixel electrode on the interlayer insulating film. Forming a counter electrode for generating a fringe electric field.

According to the present invention, in an FFS mode liquid crystal display device, the number of photolithography processes can be reduced without using a transflective mask, and a thin film transistor array substrate capable of reducing disconnection, a manufacturing method thereof, and A liquid crystal display device can be provided.

2 is a front view showing a configuration of a TFT array substrate used in the liquid crystal display device according to Embodiment 1. FIG. 3 is a plan view showing a pixel configuration of a TFT array substrate according to Embodiment 1. FIG. 2 is a cross-sectional view showing a pixel configuration of a TFT array substrate according to Embodiment 1. FIG. FIG. 5 is a plan view showing one manufacturing process of the TFT array substrate according to the first embodiment. FIG. 5 is a plan view showing one manufacturing process of the TFT array substrate according to the first embodiment. FIG. 5 is a plan view showing one manufacturing process of the TFT array substrate according to the first embodiment. FIG. 5 is a plan view showing one manufacturing process of the TFT array substrate according to the first embodiment. FIG. 5 is a plan view showing one manufacturing process of the TFT array substrate according to the first embodiment. 5 is a cross-sectional view showing one manufacturing process of the TFT array substrate according to Embodiment 1. FIG. 5 is a cross-sectional view showing one manufacturing process of the TFT array substrate according to Embodiment 1. FIG. 5 is a cross-sectional view showing one manufacturing process of the TFT array substrate according to Embodiment 1. FIG. 5 is a cross-sectional view showing one manufacturing process of the TFT array substrate according to Embodiment 1. FIG. 5 is a cross-sectional view showing one manufacturing process of the TFT array substrate according to Embodiment 1. FIG. 5 is a plan view showing a pixel configuration of a TFT array substrate according to Embodiment 2. FIG. 6 is a cross-sectional view showing a pixel configuration of a TFT array substrate according to Embodiment 2. FIG. FIG. 6 is a cross-sectional view showing a connection converter between a gate layer and a source / drain layer according to a third embodiment. FIG. 6 is a cross-sectional view showing a connection converter between a gate layer and a source / drain layer according to a third embodiment. It is the top view and sectional drawing which showed the connection conversion part of the gate layer which concerns on Embodiment 3, and a source / drain layer. It is the top view and sectional drawing which showed the connection conversion part of the gate layer which concerns on Embodiment 3, and a source / drain layer. 6 is a cross-sectional view showing a pixel configuration of a TFT array substrate according to Embodiment 4. FIG.

The preferred embodiments of the present invention will be described below. The following description explains the embodiment of the present invention, and the present invention is not limited to the following embodiment. For clarity of explanation, the following description and drawings are omitted and simplified as appropriate. For the sake of clarification, duplicate explanation is omitted as necessary. In addition, what attached | subjected the same code | symbol in each figure has shown the same element, and description is abbreviate | omitted suitably.

Embodiment 1 FIG.
First, the liquid crystal display device according to the first embodiment will be described with reference to FIG. FIG. 1 is a front view showing a configuration of a TFT array substrate used in the liquid crystal display device according to the first embodiment. The liquid crystal display device according to the first embodiment is an FFS mode liquid crystal display device in which a pixel electrode and a counter electrode are formed on a TFT array substrate. The overall configuration of this liquid crystal display device is common to the first to sixth embodiments described below.

The liquid crystal display device according to the first embodiment has a substrate 1. The substrate 1 is, for example, an array substrate such as a TFT array substrate. The substrate 1 is provided with a display area 41 and a frame area 42 provided so as to surround the display area 41. In the display area 41, a plurality of gate lines (scanning signal lines) 43 and a plurality of source lines (display signal lines) 44 are formed. The plurality of gate wirings 43 are provided in parallel. Similarly, the plurality of source lines 44 are provided in parallel. The gate wiring 43 and the source wiring 44 are formed so as to cross each other. A region surrounded by the adjacent gate wiring 43 and source wiring 44 is a pixel 47. Accordingly, in the display area 41, the pixels 47 are arranged in a matrix.

A scanning signal driving circuit 45 and a display signal driving circuit 46 are provided in the frame region 42 of the substrate 1. The gate line 43 extends from the display area 41 to the frame area 42 and is connected to the scanning signal drive circuit 45 at the end of the substrate 1. Similarly, the source line 44 extends from the display area 41 to the frame area 42 and is connected to the display signal drive circuit 46 at the end of the substrate 1. An external wiring 48 is connected in the vicinity of the scanning signal driving circuit 45. In addition, an external wiring 49 is connected in the vicinity of the display signal driving circuit 46. The external wirings 48 and 49 are wiring boards such as FPC (Flexible Printed Circuit).

Various external signals are supplied to the scanning signal driving circuit 45 and the display signal driving circuit 46 via the external wirings 48 and 49. The scanning signal driving circuit 45 supplies a gate signal (scanning signal) to the gate wiring 43 based on an external control signal. The gate wiring 43 is sequentially selected by this gate signal. The display signal driving circuit 46 supplies a display signal to the source wiring 44 based on an external control signal or display data. As a result, a display voltage corresponding to the display data can be supplied to each pixel 47.

In the pixel 47, at least one TFT 50 is formed. The TFT 50 is disposed near the intersection of the source wiring 44 and the gate wiring 43. For example, the TFT 50 supplies a display voltage to the pixel electrode. That is, the TFT 50 which is a switching element is turned on by a gate signal from the gate wiring 43. Thereby, a display voltage is applied from the source line 44 to the pixel electrode connected to the drain electrode of the TFT 50. Further, the pixel electrode is disposed to face a common electrode (a counter electrode) having a slit through an insulating film. A fringe electric field corresponding to the display voltage is generated between the pixel electrode and the counter electrode. An alignment film (not shown) is formed on the surface of the substrate 1. A detailed configuration of the pixel 47 will be described later.

Furthermore, a counter substrate is disposed opposite to the substrate 1. The counter substrate is, for example, a color filter substrate, and is disposed on the viewing side. A color filter, a black matrix (BM), an alignment film, and the like are formed on the counter substrate. A liquid crystal layer is sandwiched between the substrate 1 and the counter substrate. That is, liquid crystal is introduced between the substrate 1 and the counter substrate. Furthermore, a polarizing plate, a phase difference plate, and the like are provided on the outer surfaces of the substrate 1 and the counter substrate. A backlight unit or the like is disposed on the non-viewing side of the liquid crystal display panel.

The liquid crystal is driven by a fringe electric field between the pixel electrode and the counter electrode. That is, the alignment direction of the liquid crystal between the substrates changes. As a result, the polarization state of the light passing through the liquid crystal layer changes. That is, the polarization state of light that has been linearly polarized after passing through the polarizing plate is changed by the liquid crystal layer. Specifically, light from the backlight unit becomes linearly polarized light by the polarizing plate on the array substrate side. As the linearly polarized light passes through the liquid crystal layer, the polarization state changes.

The amount of light passing through the polarizing plate on the counter substrate side varies depending on the polarization state. That is, the amount of light that passes through the polarizing plate on the viewing side among the transmitted light that passes through the liquid crystal display panel from the backlight unit changes. The alignment direction of the liquid crystal changes depending on the applied display voltage. Therefore, the amount of light passing through the viewing-side polarizing plate can be changed by controlling the display voltage. That is, a desired image can be displayed by changing the display voltage for each pixel.

Subsequently, a pixel configuration of the liquid crystal display device according to Embodiment 1 will be described with reference to FIGS. FIG. 2 is a plan view showing a pixel configuration of the TFT array substrate according to the first embodiment. FIG. 3 is a cross-sectional view showing a pixel configuration of the TFT array substrate according to the first embodiment. FIG. 2 shows one of the pixels 47 of the TFT array substrate. 3A is a sectional view taken along line IIIA-IIIA in FIG. 2, FIG. 3B is a sectional view taken along line IIIB-IIIB in FIG. 2, and FIG. 3C is a sectional view taken along line IIIC-IIIC in FIG.

2 and 3, a gate wiring 43 connected to the gate electrode of the TFT 50 is formed on a transparent insulating substrate 1 such as glass. Here, the gate wiring 43 is formed so that a part thereof constitutes a gate electrode. The gate wiring 43 is arranged on the substrate 1 so as to extend linearly in one direction. On the substrate 1, a plurality of common wirings 43 a are formed from the same layer as the gate wirings 43. The common wiring 43 a is disposed between the adjacent gate wirings 43. The plurality of common wires 43a are provided in parallel. The common wiring 43a and the gate wiring 43 are disposed so as to be substantially parallel to each other. The gate wiring 43 and the common wiring 43a are, for example, Cr, Al, Ta, Ti, Mo, W, Ni, Cu, Au, Ag, an alloy film containing these as a main component, or a first metal made of a laminated film thereof. It is formed by a film.

A gate insulating film 11 as a first insulating film is provided so as to cover the gate wiring 43 and the common wiring 43a. The gate insulating film 11 is formed of an insulating film such as silicon nitride or silicon oxide.

A semiconductor layer 2 is formed on the gate insulating film 11. In the first embodiment, the semiconductor layer 2 is formed in a straight line so as to intersect the gate wiring 43 and the common wiring 43a. Here, for example, it is orthogonal to the gate wiring 43 and the common wiring 43a. The semiconductor layer 2 is disposed on the substrate 1 so as to extend linearly in a direction intersecting with the gate wiring 43. A plurality of semiconductor layers 2 are arranged at intervals.

The semiconductor layer 2 branches off at the intersection with the gate wiring 43. The branched semiconductor layer 2 extends along the gate wiring 43 and further extends into the pixel 47. In the region where the TFT 50 is formed, the semiconductor layer 2 is provided on the opposite side of the gate electrode via the gate insulating film 11. That is, in the semiconductor layer 2 branched from the intersection with the gate wiring 43, a portion overlapping with the gate electrode functions as an active region constituting the TFT 50. The active region of the semiconductor layer 2 is
Here, the gate wiring 43 is formed on the gate insulating film 11 so as to overlap with the gate wiring 43, and the gate wiring 43 in a region overlapping with the active region of the semiconductor layer 2 serves as a gate electrode. The semiconductor layer 2 is made of, for example, amorphous silicon, polycrystalline polysilicon, or the like.

The linear semiconductor layer 2 extending in the direction intersecting with the gate wiring 43 can be used as a redundant wiring of the source wiring 44 described later. That is, the linear semiconductor layer 2 is formed in accordance with the formation region of the source wiring 44, and it is possible to prevent electrical signals from being interrupted even when the source wiring 44 is disconnected.

On the semiconductor layer 2, an ohmic contact film 3 doped with conductive impurities is formed. The ohmic contact film 3 is disposed on substantially the entire surface of the semiconductor layer 2 excluding the channel region of the TFT 50. Of the semiconductor layer 2 overlapping the gate electrode, the region of the semiconductor layer 2 corresponding to the ohmic contact film 3 becomes a source / drain region. Specifically, the region of the semiconductor layer 2 corresponding to the left ohmic contact film 3 overlapping with the gate electrode in FIG. The region of the semiconductor layer 2 corresponding to the right ohmic contact film 3 overlapping with the gate electrode in FIG. 3A becomes the drain region. Thus, source / drain regions are formed at both ends of the active region of the semiconductor layer 2 constituting the TFT 50. A region sandwiched between the source / drain regions of the semiconductor layer 2 becomes a channel region. The ohmic contact film 3 is not formed on the channel region of the semiconductor layer 2. The ohmic contact film 3 is made of, for example, n-type amorphous silicon or n-type polycrystalline silicon doped with an impurity such as phosphorus (P) at a high concentration.

On the ohmic contact film 3, a source electrode 4, a drain electrode 5, and a source wiring 44 are formed. Specifically, the source electrode 4 is formed on the ohmic contact film 3 on the source region side of the semiconductor layer 2. A drain electrode 5 is formed on the ohmic contact film 3 on the drain region side. In this way, the channel etch type TFT 50 is configured. The source electrode 4 and the drain electrode 5 are formed so as to extend outside the channel region of the semiconductor layer 2. That is, the source electrode 4 and the drain electrode 5 are not formed on the channel region of the semiconductor layer 2 like the ohmic contact film 3.

The source electrode 4 extends outside the channel region of the semiconductor layer 2 and is connected to the source wiring 44. That is, the source wiring 44 is connected to the source electrode 4. The source wiring 44 is formed on the semiconductor layer 2 via the ohmic contact film 3 and is disposed on the substrate 1 so as to extend linearly in a direction intersecting with the gate wiring 43. Therefore, the source line 44 branches at the intersection with the gate line 43 and then extends along the gate line 43 to become the source electrode 4. The source electrode 4, the drain electrode 5, and the source wiring 44 are made of, for example, Cr, Al, Ta, Ti, Mo, W, Ni, Cu, Au, Ag, an alloy film containing these as a main component, or a laminated film thereof. The second metal film is formed.

As described above, in the first embodiment, the semiconductor layer 2 includes the substantially entire surface under the source wiring 44, the substantially entire surface under the source electrode 4, the almost entire surface under the drain electrode 5, and the gate electrode. It is the structure arrange | positioned. Here, ohmic contact films 3 are further formed between the source wiring 44, the source electrode 4, the drain electrode 5, and the semiconductor layer 2.

The drain electrode 5 extends outside the channel region of the semiconductor layer 2 and is electrically connected to the pixel electrode 6. In the first embodiment, the pixel electrode 6 is formed directly on the drain electrode 5. That is, the lower surface (lower surface) of the pixel electrode 6 is formed so as to be in direct contact with the upper surface (upper surface) of the drain electrode 5. The pixel electrode 6 is formed on substantially the entire surface of the drain electrode 5. The pixel electrode 6 extends from the drain electrode 5 into the pixel 47, and as shown in FIGS. 2 and 3, the pixel electrode 6 is in a region surrounded by the source wiring 44 and the gate wiring 43 constituting the pixel 47. It is formed on substantially the entire surface. That is, the pixel electrode 6 is disposed so that a part thereof overlaps the drain electrode 5. At this time, the pattern end of the pixel electrode 6 on the channel region side is overlapped with the pattern end of the drain electrode 5 on the channel region side. Therefore, the pattern end of the drain electrode 5 on the channel region side is not covered with the pixel electrode 6. The pixel electrode 6 is formed so as to cover, for example, the pattern end of the drain electrode 5 other than the channel region side. The pixel electrode 6 is formed of a first transparent conductive film such as ITO.

Thus, the pixel electrode 6 is formed directly on the upper layer of the source electrode 4, the drain electrode 5, and the source wiring 44 without using an insulating film. With such a configuration, a contact hole for electrically connecting the pixel electrode 6 to the drain electrode 5 becomes unnecessary. This is because by arranging a part of the pixel electrode 6 so as to directly overlap the drain electrode 5, an electrical connection between them can be obtained. Therefore, the pixel 47 can be configured without providing an area for arranging the contact hole for the connection between the drain electrode 5 and the pixel electrode 6, and the aperture ratio can be increased.

In the first embodiment, the transparent conductive pattern 6 a is formed of the same first transparent conductive film as the pixel electrode 6. The transparent conductive pattern 6 a is formed so as to directly overlap the substantially entire surface on the source electrode 4 and the source wiring 44. The transparent conductive pattern 6a is formed so as to cover the source electrode 4 and the source wiring 44, for example. However, the pattern end on the channel region side of the source electrode 4 is not covered with the transparent conductive pattern 6a. Therefore, the pattern end on the channel region side of the transparent conductive pattern 6a is substantially at the same position as the pattern end of the source electrode 4 on the channel region side. The transparent conductive pattern 6a and the pixel electrode 6 are disposed so as to be separated from each other. Further, the transparent conductive pattern 6 a and the pixel electrode 6 are not provided on the channel region of the semiconductor layer 2.

As described above, in the first embodiment, the pixel electrode 6 or the transparent conductive pattern made of the first transparent conductive film is formed on the source electrode 4, the drain electrode 5, and the source wiring 44 made of the second metal film. 6a is laminated. Here, the pattern formed by the first transparent conductive film is formed so as to completely cover all regions except the channel region of the TFT 50 among the patterns formed by the second metal film. As a result, the source wiring 44 for supplying the display signal to each pixel 47 can have a two-layer laminated structure of the second metal film and the first transparent conductive film. Therefore, there is an effect of suppressing occurrence of disconnection of the source wiring 44. That is, the transparent conductive pattern 6 a laminated on the source wiring 44 can be used as a redundant wiring of the source wiring 44 as in the semiconductor layer 2 below the source wiring 44. Therefore, even if the source wiring 44 is disconnected, it is possible to prevent the display signal from being interrupted.

An interlayer insulating film 12 as a second insulating film is provided so as to cover the pixel electrode 6 and the transparent conductive pattern 6a. The interlayer insulating film 12 covers the TFT 50. The interlayer insulating film 12 is formed of an insulating film such as silicon nitride or silicon oxide.

In the first embodiment, the counter electrode 8 is formed on the interlayer insulating film 12. The counter electrode 8 is disposed on the opposite side of the pixel electrode 6 with the interlayer insulating film 12 interposed therebetween, and a slit for generating a fringe electric field is provided between the counter electrode 8 and the pixel electrode 6. As shown in FIG. 2, a plurality of slits are provided substantially in parallel with the source wiring 44. The slit is provided in a straight line in a direction intersecting with the gate wiring 43, for example.

The counter electrode 8 is electrically connected to the common wiring 43 a through a contact hole 13 that penetrates the interlayer insulating film 12 and the gate insulating film 11. The counter electrode 8 is formed so as to be connected to the counter electrode 8 of the adjacent pixel 47 with the gate wiring 43 interposed therebetween. That is, the counter electrode 8 is integrally formed so as to be connected to the counter electrode 8 of the adjacent pixel 47 with the gate wiring 43 interposed therebetween. Specifically, the counter electrodes 8 of the pixels 47 adjacent to each other with the gate wiring 43 interposed therebetween are connected by a connecting portion 8a. The connecting portion 8 a is formed so as to get over the gate wiring 43, and connects the opposing electrodes 8 of the adjacent pixels 47 with the gate wiring 43 interposed therebetween. Here, the connecting portion 8 a of the counter electrode 8 is formed so as to straddle the gate wiring 43 in a region not overlapping with the source wiring 44 or the TFT 50. That is, the counter electrode 8 is formed so as to overlap at least a part of the gate wiring 43. The counter electrode 8 is formed of a second transparent conductive film such as ITO.

Next, a method for manufacturing the liquid crystal display device according to the first embodiment will be described with reference to FIGS. 4 to 8 are plan views showing one manufacturing process of the TFT array substrate according to the first embodiment. 9 to 13 are cross-sectional views showing one manufacturing process of the TFT array substrate according to the first embodiment. 9A to 13B, (a) is a cross-sectional view at a location corresponding to the IIIB-IIIB cross section of FIG. 2, (b) is a cross-sectional view at a location corresponding to the IIIB-IIIB cross section of FIG. ) Shows cross-sectional views at locations corresponding to the IIIC-IIIC cross-section of FIG. That is, these drawings are cross-sectional views for each manufacturing process at locations corresponding to the respective drawings in FIG.

First, Cr, Al, Ta, Ti, Mo, W, Ni, Cu, Au, Ag, an alloy film containing these as a main component, or these films are formed on the entire surface of the transparent insulating substrate 1 such as glass. A first metal film made of a laminated film is formed. When an alloy obtained by adding Ni to the base material Al is used as the material of the first metal film, electrical connection with the counter electrode 8 shown in FIG.
For example, a film is formed on the entire surface of the substrate 1 by using a sputtering method or a vapor deposition method. Thereafter, a resist is applied, the applied resist is exposed from above the photomask, and the resist is exposed. Next, the exposed resist is developed to pattern the resist. Hereinafter, the series of steps is referred to as a photolithography step. Thereafter, etching is performed using this resist pattern as a mask, and the photoresist pattern is removed. Hereinafter, such a process is referred to as a fine processing technique. As a result, as shown in FIGS. 4 and 9, the gate electrode, the gate wiring 43, and the common wiring 43a are patterned. In this manner, the gate electrode, the gate wiring 43, and the common wiring 43a are formed by the first photolithography process and the fine processing technique.

Next, the first insulating film, the semiconductor layer 2, and the ohmic contact film 3 to be the gate insulating film 11 are formed in this order so as to cover the gate electrode, the gate wiring 43, and the common wiring 43a. For example, these are formed on the entire surface of the substrate 1 using plasma CVD, atmospheric pressure CVD, reduced pressure CVD, or the like. As the gate insulating film 11, silicon nitride, silicon oxide, or the like can be used. Note that the gate insulating film 11 is preferably formed in a plurality of times in order to prevent a short circuit due to the occurrence of film defects such as pinholes. Amorphous silicon, polycrystalline polysilicon, or the like can be used for the semiconductor layer 2, but light is absorbed when a transparent semiconductor film such as ZnO, ITO, or IGZO (In—Ga—Zn—O) is used. Accordingly, it is possible to suppress the deterioration of the off characteristics of the thin film transistor derived from the photocarrier generated. The semiconductor layer 2 may be an organic semiconductor film such as tetracene or pentacene. The ohmic contact film 3 can be made of n-type amorphous silicon or n-type polycrystalline silicon to which an impurity such as phosphorus (P) is added at a high concentration. When a transparent semiconductor film is used as the semiconductor layer 2, a metal film such as an aluminum film can be used as the ohmic contact film 3.

Next, in the first embodiment, Cr, Al, Ta, Ti, Mo, W, Ni, Cu, Au, Ag or an alloy film containing these as a main component is formed on the ohmic contact film 3 formed. Alternatively, a second metal film made of these laminated films is further formed. For example, the film is formed by using a sputtering method or a vapor deposition method. Thereafter, the second metal film is patterned by a second photolithography process and a fine processing technique. As a result, the source wiring 44 and a portion branched from the source wiring 44 and extending onto the formation region of the TFT 50 are formed by the second metal film. The portion branched from the source wiring 44 is formed so as to branch from the intersection of the source wiring 44 with the gate wiring 43 and extend into the pixel 47, and to be separated in a later step, and the source electrode 4 and drain The shape includes the electrode 5. That is, at this time, the second metal film remains on the channel region, and the source electrode 4 and the drain electrode 5 are connected. That is, when the second metal film is patterned, the source electrode 4 and the drain electrode 5 connected on the semiconductor layer 2 to be the channel region of the TFT 50 and the source wiring 44 connected to the source electrode 4 are formed. .

Subsequently, the pattern of the patterned second metal film, or the resist pattern used when patterning the second metal film (or the state where the resist pattern used when patterning the second metal film is left. And the ohmic contact film 3 and the semiconductor layer 2 are etched. As a result, as shown in FIGS. 5 and 10, the ohmic contact film 3 and the semiconductor layer 2 that are not covered with the second metal film are removed. Thus, by patterning the ohmic contact film 3 and the semiconductor layer 2, the patterning of the ohmic contact film 3 and the semiconductor layer 2 can be integrated with the patterning of the source wiring 44. That is, the ohmic contact film 3 and the semiconductor layer 2 can be patterned and the source wiring 44 can be patterned in one photolithography process.

Next, a first transparent conductive film such as ITO is formed on the entire surface of the substrate 1 by sputtering or the like. Then, the first transparent conductive film is patterned by a third photolithography process and a fine processing technique. In the first embodiment, patterning is performed so that the first transparent conductive film remains on the formation region of the pixel electrode 6 and on the second metal film pattern excluding the channel region of the TFT 50. As a result, the transparent conductive pattern 6 a is formed on the source wiring 44 and on the region that becomes the source electrode 4 in the portion branched from the source wiring 44. Further, the pixel electrode 6 is formed so that a part of the portion branched from the source wiring 44 overlaps with a region to be the drain electrode 5. The transparent conductive pattern 6a and the pixel electrode 6 formed by the first transparent conductive film function as an etching barrier pattern in a channel etch process described later.

Note that the first transparent conductive film may be ITO, IZO, or ITZO. In addition, when the first transparent conductive film is formed in an amorphous state, a weak acid such as oxalic acid can be used as an etching solution. For example, when a refractory metal is used as the second metal film, it is relatively easy to select an etchant that does not etch the second metal film pattern when the first transparent conductive film is etched. Therefore, the disconnection of the source wiring 44 made of the second metal film pattern can be further reduced.

Subsequently, the second metal film and the ohmic contact film 3 on the channel region are etched using the pixel electrode 6 and the transparent conductive pattern 6a as a mask. Specifically, the portion of the second metal film exposed without being covered with the pixel electrode 6 or the transparent conductive pattern 6a is removed by etching. Thereby, the second metal film on the channel region is removed, and the source electrode 4 and the drain electrode 5 are separated. Further, the ohmic contact film 3 on the channel region exposed on the surface by removing the second metal film is removed by etching. As a result, as shown in FIGS. 6 and 11, the semiconductor layer 2 that becomes the channel region of the TFT 50 is exposed. As described above, in the first embodiment, the second metal film and the ohmic contact film on the channel region are formed by using the transparent conductive pattern 6a formed by the first transparent conductive film and the pixel electrode 6 as an etching barrier pattern. 3 can be removed.

 In the above description, etching is performed using the pixel electrode 6 and the transparent conductive pattern 6a as a mask. However, the second metal film is formed using the resist pattern used for patterning the pixel electrode 6 and the transparent conductive pattern 6a as a mask. The ohmic contact film 3 may be etched.

Subsequently, a second insulating film to be the interlayer insulating film 12 is formed from above. For example, an inorganic insulating film such as silicon nitride or silicon oxide is formed as an interlayer insulating film 12 over the entire surface of the substrate 1 using a CVD method or the like. Thereby, the pixel electrode 6 and the transparent conductive pattern 6 a are covered with the interlayer insulating film 12. Further, the channel region of the semiconductor layer 2 is covered with the interlayer insulating film 12. Here, the inorganic insulating film constituting the interlayer insulating film 12 may be formed twice. For example, after film formation once, brush cleaning may be performed and film formation may be performed again. Thereby, the short circuit by a foreign material reduces and insulation performance increases.

Thereafter, contact holes are formed in the interlayer insulating film 12 and the gate insulating film 11 by a fourth photolithography process and a fine processing technique. Thereby, as shown in FIGS. 7 and 12, a contact hole 13 reaching the common wiring 43a is formed, and the common wiring 43a is partially exposed. In the frame region 42, a terminal (not shown) for connecting to the scanning signal driving circuit 45 or the display signal driving circuit 46 is formed of the same layer as the gate wiring 43 or the source wiring 44. Therefore, in the fourth photolithography process and the fine processing technique, the contact holes 13 reaching the common wiring 43 a and the contact holes reaching these terminals are formed in the interlayer insulating film 12 and the gate insulating film 11.

Next, a second transparent conductive film such as ITO is formed on the entire surface of the substrate 1 on the interlayer insulating film 12 by sputtering or the like. Then, the second transparent conductive film is patterned by a fifth photolithography process and a fine processing technique. Thus, the counter electrode 8 having a slit is formed on the opposite side of the pixel electrode 6 through the interlayer insulating film 12 so as to be connected to the common wiring 43 a through the contact hole 13. In the frame region 42, the gate terminal pad connected to the gate terminal through the contact hole is formed by the same second transparent conductive film as the counter electrode 8. Similarly, a source terminal pad connected to the source terminal via the contact hole is formed by the same second transparent conductive film as the counter electrode 8.

Through the above steps, the TFT array substrate of the first embodiment is completed. As described above, in the first embodiment, at least (1) the gate electrode (first metal film), (2) the source / drain electrode (without using a transflective mask which is a general process reduction technique) The TFT array substrate can be formed by five photolithography steps of (second metal film), (3) pixel electrode and transparent conductive pattern, (4) contact hole, and (5) counter electrode. This makes it possible to make the number of photolithography processes equal to the number of photolithography processes required for manufacturing a TN mode TFT array substrate of a general liquid crystal display device.

In particular, in the first embodiment, in a conventional FFS mode liquid crystal display device, (1) a counter electrode, (2) a gate electrode (first metal film), (at least necessary for manufacturing a TFT array substrate) 3) Among the six photolithography steps of (4) source / drain electrode (second metal film), (5) contact hole, and (6) pixel electrode, (3) semiconductor layer, (4) In the first embodiment, the source / drain electrode (second metal film) and (6) the pixel electrode are subjected to three photolithography steps. In the first embodiment, (2) the second metal film, (3) the pixel electrode, and the transparent conductive pattern Can be integrated into two ordinary photolithography processes. Therefore, it is possible to reduce the number of photolithography processes necessary for manufacturing the TFT array substrate of the FFS mode liquid crystal display device without using a transflective mask, and to reduce the manufacturing cost.

On the TFT array substrate thus manufactured, an alignment film is formed in the subsequent cell process. In addition, an alignment film is similarly formed on a counter substrate manufactured separately. Then, the alignment film is subjected to an alignment process using a technique such as rubbing to make a micro scratch in one direction on the contact surface with the liquid crystal. Next, a sealing material is applied to the periphery of the substrate, and the TFT array substrate and the counter substrate are bonded at a predetermined interval so that the alignment films face each other. After the TFT array substrate and the counter substrate are bonded together, liquid crystal is injected from the liquid crystal injection port using a vacuum injection method or the like. Then, the liquid crystal injection port is sealed. After attaching polarizing plates on both sides of the liquid crystal cell thus formed and connecting the drive circuit, the backlight unit is attached. In this way, the liquid crystal display device of the first embodiment is completed.

In the first embodiment, it has been described that the counter electrode 8 between the adjacent pixels 47 is connected with the gate wiring 43 interposed therebetween, but the shape of the counter electrode 8 is limited to this. It is not a thing. The counter electrode 8 corresponding to each pixel 47 is electrically connected to the common wiring 43 a through the contact hole 13. Therefore, when the same signal is applied to these common wirings 43a, the counter electrodes 8 between the adjacent pixels 47 with the gate wiring 43 interposed therebetween may be formed so as to be separated from each other.

As described above, in the first embodiment, in the second photolithography process, the second metal film is patterned to form the source / drain electrodes connected to the channel region and the source wiring 44. . Then, the ohmic contact film 3 and the semiconductor layer 2 are etched using the patterned second metal film pattern as a mask. Thereafter, a first transparent conductive film is deposited directly on the first transparent conductive film, and an ohmic contact with the second metal film on the channel region is formed using the patterned first transparent conductive film as a mask in the third photolithography step. The contact film 3 is further removed by etching. Thereby, the number of photolithography processes required for manufacturing the TFT array substrate can be reduced without using a transflective mask. Accordingly, mass production can be further stabilized without complicating process management, and mask costs can be suppressed.

The TFT array substrate formed in this way is formed on the entire area (entire surface) under the second metal film constituting the source wiring 44, the source electrode 4, the drain electrode 5 and the like via the ohmic contact film 3. Layer 2 is present. Further, the pixel electrode 6, the transparent conductive pattern 6 a, and the like are directly superimposed on almost the entire region (entire surface) on the second metal film that forms the source wiring 44, the source electrode 4, the drain electrode 5, and the like. The transparent conductive film exists. As a result, the transparent conductive pattern 6 a is laminated on the source wiring 44 and becomes a redundant wiring of the source wiring 44. Therefore, even if the source wiring 44 is disconnected, it is possible to prevent the display signal from being interrupted.

Embodiment 2. FIG.
In the first embodiment, after the third photolithography process, the etching of the second conductive film is performed subsequent to the etching of the first transparent conductive film, thereby reducing the number of photolithography processes and the source wiring. The effect that the disconnection can be reduced was achieved. That is, in the source electrode and the drain electrode, at the locations facing the channel regions, the second metal film, which is the lower layer, is etched using the first transparent conductive film as an etching mask. In general, when a laminated structure is processed, if each layer is selectively etched with an etchant sequentially, side etching occurs in the etched layer, while the upper layer of the etched layer is not etched and becomes wrinkled. The cross-sectional shape will pop out. FIG. 14 shows this situation in a cross-sectional view.

FIG. 14 shows the situation after etching the second metal film, which is the layer to be etched, using the pixel electrode 6 and the transparent conductive pattern 6a as an etching mask. It can be seen that the edge starts out from the edges of the source electrode 4 and the drain electrode 5 which are the second metal film, and a shape like a ridge is generated. When such a wrinkle is formed, the covering property of the interlayer insulating film 12 to be formed later is deteriorated, and the etching solution at the time of patterning the counter electrode 8 on the upper layer soaks into the first transparent conductive film. There arises a problem that the pixel electrode 6 and the transparent conductive pattern 6a which are films are damaged. Alternatively, before the interlayer insulating film 12 is formed, there may be a problem that the portion of the ridge is broken and becomes a foreign substance, causing a display defect.

A pixel configuration of the liquid crystal display device according to Embodiment 2 will be described with reference to FIG. FIG. 15 is a cross-sectional view showing a pixel configuration of the TFT array substrate according to the second embodiment. FIG. 15 shows one of the pixels 47 of the TFT array substrate. 15 is a cross-sectional view taken along the line IIIA-IIIA in FIG. In this embodiment, only the cross-sectional shapes of the transparent conductive pattern 6a and the source wiring 44 in the TFT channel portion are different from those in the first embodiment, and the other configurations are the same as those in the first embodiment. The description about is omitted.

As is clear from FIG. 15, the pattern edges of the transparent conductive pattern 6 a and the pixel electrode 6 are different from those of the source electrode 4 and the drain electrode 5 in the cross-sectional shape where the source electrode 4 and the drain electrode 5 face each other across the channel region. It is more backward than the pattern edge. In other words, the pattern edges of the transparent conductive pattern 6 a and the pixel electrode 6 are included in the pattern edges of the source electrode 4 and the drain electrode 5 at the locations facing each other across the channel region. The TFT array substrate having such a structure is formed again after the etching of the second conductive film performed after the etching of the first transparent conductive film is completed in the microfabrication process after the third photolithography process in the first embodiment. The first transparent conductive film is formed by etching.

In the second etching of the first transparent conductive film performed after the etching of the second conductive film, if the second conductive film is likely to be etched, the second conductive is more than the pattern edge of the first transparent conductive film recedes. The edge of the film pattern will recede and the wrinkle shape will not be eliminated. Therefore, in such etching, etching conditions having selectivity that the second conductive film is hardly etched to such an extent that the ridge shape is eliminated are preferable. Furthermore, it is desirable that the etching rate of the first transparent conductive film is higher than the etching rate of the second conductive film. If the second etching condition of the first transparent conductive film is selective to the second conductive film, the first etching condition of the first transparent conductive film performed before the etching of the second conductive film is performed. May be the same.

Further, when the first transparent conductive film is an amorphous film, the timing for crystallizing the film by means of annealing or the like is determined by the etching of the first transparent conductive film performed after the etching of the second conductive film. It is better to be after completion. This is because the generation of etching residues can be reduced by etching before crystallization rather than after crystallization of the transparent conductive film.

In the second embodiment, in addition to the effect that the number of photolithography steps can be reduced and the disconnection of the source wiring can be reduced, there is an effect that the wrinkles of the first transparent conductive film can be removed.

Embodiment 3 FIG.
The pixel configuration of the liquid crystal display device according to the first embodiment will be described with reference to FIGS. 16 and 17 for a third embodiment which is a different mode. In FIG. 16, the electrode line 43b of the gate layer and the electrode line 44b of the same layer as the source / drain electrode are electrically connected by the conductive pattern 8b of the same layer as the counter electrode 8 through the contact holes 13a and 13b. The cross section of the connection conversion part connected is shown. The contact hole 13b is opened in the interlayer insulating film 12, and an opening edge 51 that is a boundary where the interlayer insulating film 12 and the transparent conductive film 6b are in contact with each other is formed on the bottom surface of the contact hole 13b.

Usually, the conductive pattern 8b is electrically connected by covering the surface of the transparent conductive film 6b exposed from the side surface of the contact hole 13b through the opening edge 51 from the side surface of the contact hole 13b which can be said to be the side surface of the interlayer insulating film 12. It has gained. The same applies to the contact hole 13a. In this way, the conductive patterns 8b can electrically connect the conductive films in different layers through the contact holes.

As described above, as a request for electrically connecting conductive films in different layers through contact holes, for example, when forming the terminal portion of the source wiring, the source wiring is formed by extending as it is. Since the wiring easily peels off when chamfering, this structure is essential when it is necessary to convert the source layer to the gate layer that is the lowest layer.

Here, the contact hole 13b is opened on the transparent conductive film 6b. However, when the interlayer insulating film 12 is opened by dry etching, a defect called a notch may occur depending on conditions. FIG. 17 is a cross-sectional view when a notch is generated in the structure shown in FIG.

In FIG. 17, when the contact hole 13b is opened by etching the interlayer insulating film 12, a wedge-shaped cut called a notch 52 is formed in the cross-sectional shape of the interlayer insulating film 12 along the opening edge 51 of the contact hole 13b. Therefore, the situation where the coverage of the conductive pattern 8b is deteriorated is shown. For example, as disclosed in Japanese Patent Application Laid-Open No. 2000-294895, when the notch 52 is generated, the conductive pattern 8b is interrupted at the opening edge 51 which is the edge of the bottom surface of the contact hole 13b. Cannot be covered with the electrode wire 44b, and the electrical connection with the electrode wire 44b cannot be obtained.

The third embodiment is for solving this problem, and FIG. 18 shows the structure thereof. 18A is a plan view of the connection conversion portion between the gate layer and the source / drain layer, and FIG. 18B is a diagram showing a cross section taken along the line AA in FIG. It is. 18A and 18B, as in FIG. 16, the electrode line 43b of the gate layer and the electrode line 44b of the same layer as the source / drain electrodes are electrically connected by the conductive pattern 8b through the contact holes. It is the same that the structure is intended to be connected electrically. In FIG. 18A, the conductive pattern 8b covers almost the entire surface.

Hereinafter, FIGS. 18A and 18B will be described. The contact hole 13 shown in this embodiment is opened by removing not only the interlayer insulating film 12 but also the gate insulating film 11. Therefore, in the region where the gate insulating film 11 is removed by etching, the main surface of the insulating substrate 1 is exposed in the region where the electrode line 43b of the gate layer is not formed, so that the opening edge 51 of the contact hole 13 is also insulative. It occurs on the substrate 1. This corresponds to the opening edge 51 which is the boundary between the gate insulating layer 11 and the insulating substrate 1, which is the lower layer of the electrode line 44 b in the same layer as the source / drain electrodes, on the right side of the contact hole 13 in FIG. To do. On the other hand, in the region where the electrode line 43b of the gate layer is formed, the opening edge 51 is generated on the electrode line 43b. This corresponds to the opening edge 51 on the electrode line 43b of the gate layer on the left side of the contact hole 13 in FIG.

Here, the notch 52 occurs when the opening edge 51 of the contact hole 13 is on the transparent conductive film, but the opening edge 51 is on the insulating substrate 1 such as glass or quartz or on the electrode line 43b. Is known not to occur. Therefore, the conductive pattern 8b can be satisfactorily covered including the portion where the electrode line 43b of the gate layer is exposed.

Further, as described in the third embodiment, if the pattern edge of the transparent conductive film 6b is retracted by additional etching as shown in FIG. 15, the conductive pattern 8b has good coverage and the electrode lines 44b and the bright conductive film. It extends to the surface of the film 6b. In this case, the conductive pattern 8b can be covered across the electrode line 43b of the gate layer and the electrode line 44b of the same layer as the source / drain electrode, regardless of the notch 52 generated on the transparent conductive film 6b. Electrical connection can be made.

Further, in FIG. 18B, there is a region where the conductive pattern 8b is in contact with the main surface of the insulating substrate 1, but this is not an essential structure. In this embodiment, unlike FIG. 17, the region where the notch 52 is not generated in the opening edge 51 of the contact hole 13 having the region where the electrode covered with the transparent conductive film 6b is exposed, that is, the transparent conductive film 6b is formed. This is because it includes a region that is not formed. Further, this is because the conductive pattern 8b covers the opening edge 51 in the region where the transparent conductive film 6b is not formed, so that a good coating can be performed.

Therefore, the structure and arrangement of the film on the bottom surface of the contact hole 13 excluding the opening edge 51 may be determined as appropriate. For example, it is possible to open the contact hole 13 that does not expose the main surface of the insulating substrate 1 by expanding the formation region of the electrode line 43b of the gate layer. In this case, since the notch 52 does not occur in the opening edge 51 on the electrode line 43b, the conductive pattern 8b can be satisfactorily covered, and the same effect as in FIG. 18 can be obtained.

Looking at the electrical connection between the covered region of the conductive pattern 8b and the electrode wire 44b in FIG. 18B, the conductive pattern 8b covers the opening edge 51 in the region other than the electrode wire 44b, and the electrode wire 43b and the substrate. One electrode is connected to the electrode wire 44b through the surface. On the other hand, in the region connected to the electrode line 44b from the outside of the contact hole 13 immediately above the electrode line 44b, there is a notch 52 due to the presence of the transparent conductive film 6b covering the electrode line 44b. Is incomplete. For this reason, in FIG. 18, in order to electrically connect the electrode line 44b and the conductive pattern 8b through the contact hole, a region where the transparent conductive film is not formed on the opening edge 51 of the contact hole 13 is required. Explained what to do.

However, when the pattern end of the transparent conductive film 6b covering the electrode line 44b is recessed inward from the pattern end of the second metal film, the transparent conductive film 6b is not formed on the second metal film exposed there. It will not be formed.

FIG. 19 is the same as FIG. 18 in a plan view, but is different from FIG. In FIG. 19 (a), a cross-sectional view taken along the line BB is shown in FIG. 19 (b). The difference from FIG. 18 is that in FIG. 19, the pattern end of the transparent conductive film 6b recedes inward from the pattern end of the second metal film of the electrode line 44b, and the second metal when viewed from above. It is in the point which sees the cross section about the location where the film | membrane is exposed.

As can be seen from FIG. 19B, the opening edge 51 of the contact hole 13 is located on the electrode line 44b, and the conductive pattern 8b can be well connected to the electrode line 44b through the contact hole 13. Recognize. Therefore, when the electrode line 44b itself has a region where the transparent conductive film is not formed at the opening edge 51 of the contact hole 13, the electrode line 44b of the same layer as the source / drain layer is provided if the contact hole is opened. And the conductive pattern 8b can be electrically connected.

Embodiment 4 FIG.
In the first embodiment, after the third photolithography process, the etching of the second conductive film is performed subsequent to the etching of the first transparent conductive film, so that the number of photolithography processes can be reduced. Yes. In this manufacturing method, since it is premised that the first transparent conductive film is formed on the gate insulating film 11, only the interlayer insulating film 12 is provided between the first transparent conductive film and the second transparent conductive film. It will be separated by. Therefore, the foreign matter mixed in the interlayer insulating film 12 or the pinhole of the interlayer insulating film 12 generated by the pinhole generated in the resist in the fourth photolithography process when patterning the interlayer insulating film 12 causes the first There is a problem that a short circuit or a dielectric breakdown occurs between the transparent conductive film and the second transparent conductive film.

The present embodiment is characterized in that the interlayer insulating film 12 has a laminated structure including an inorganic insulating film 12a such as a SiN film and an organic insulating film 12b formed thereon. A pixel configuration of the liquid crystal display device according to this embodiment will be described with reference to FIG. 20 is a cross-sectional view showing a pixel configuration of the TFT array substrate according to the fourth embodiment, and is a cross-sectional view corresponding to the IIIA-IIIA cross-sectional view of FIG.

Generally, an organic resin film such as acrylic or polyimide is used for the organic insulating film 12b. Further, after forming the inorganic insulating film 12a by plasma CVD or sputtering, an organic resin film 12b such as acrylic or polyimide is applied by a spin coater or the like, and a baking process is performed if necessary. When applied using a spin coater, the organic resin film 12b has a surface that smoothens the unevenness of the thin film transistor serving as a base, and the film thickness is preferably 1 μm or more and 2 μm or less. This is because if the thickness is too large, the capacitance between the pixel electrode 6 and the counter electrode 8 decreases.

The organic resin film 12b may have photosensitivity. When there is photosensitivity, the contact hole 13 can be opened by exposing and developing the organic insulating film 12b without applying a new photosensitive resist. After that, the inorganic insulating film 12a as a base may be etched using the organic resin film 12b as a mask.

The inorganic insulating film 12a may be SiN, but may be SiO2 or SiON. Moreover, SOG may be sufficient. The organic resin film may have photosensitivity, in which case the organic resin film itself can be patterned without forming a separate resist or etching in the fourth photolithography process. Therefore, the production process can be reduced, and the production efficiency can be improved.

Embodiment 5 FIG.
In Embodiment 4, a contact hole is opened in the interlayer insulating film 12 after the fourth photolithography process. At the time of opening, the organic insulating film 12b is removed by etching or development, and then the inorganic insulating film 12a such as SiN is removed by dry etching. As described above, in this case, in the vicinity of the interface with the first transparent conductive film. A wedge-shaped cut called a notch may be formed in the cross section of the inorganic insulating film 12a.

The present embodiment is characterized in that the film thickness of the inorganic insulating film 12a such as a SiN film is the same as or thinner than the film thickness of the second transparent conductive film. Usually, since the film thickness of the second transparent conductive film is about 0.05 to 0.2 μm, if the insulating film 12 is a single layer and the film thickness is less than that, the pixel electrode 6 And the counter electrode 8 is not sufficient to maintain insulation. However, according to this embodiment, since the laminated structure of the inorganic insulating film 12a and the organic insulating film 12b is formed between the pixel electrode 6 and the counter electrode 8, the thickness of the inorganic insulating film 12a is small. In addition, since the organic insulating film 12b is sufficiently thick, sufficient insulation can be maintained. And since the film thickness of the inorganic insulating film 12a is thinner than the film thickness of the 2nd transparent conductive film, even if a notch arises in the inorganic insulating film 12a, it can be coat | covered with a 2nd transparent conductive film. Play.

Embodiment 6 FIG.
In the fourth embodiment, the interlayer insulating film 12 has a laminated structure including an inorganic insulating film 12a such as a SiN film and an organic resin film 12b formed on the upper layer. A plurality of films may be formed. Different organic resin films may be stacked, or organic resin films of the same material may be stacked. In either case, similar to the fourth embodiment, an effect of reducing a short circuit between the conductive films due to pinholes or the like can be achieved.

Further, when only the organic resin film was laminated and the inorganic insulating film was not used, no notch was generated even when the opening edge of the contact hole was located on the transparent conductive film. Therefore, even in the structure as shown in FIG. 16 shown in the third embodiment, electrical connection can be established without generating a notch as shown in FIG. It can contribute to the conversion.

1 substrate, 2 semiconductor layers, 3 ohmic contact film,
4 source electrode, 5 drain electrode,
6 pixel electrode, 6a, 6b transparent conductive pattern,
8 Counter electrode, 8a, 8b Connection pattern of conversion part,
11 Gate insulating film,
12 interlayer insulation film, 12a inorganic insulation film, 12b organic insulation film,
13 Contact hole, 13b Contact hole of conversion part,
41 display area, 42 frame area,
43 Gate wiring, 43a Common wiring, 43b Conversion layer gate layer wiring,
44 source wiring, 44b wiring of the source layer of the conversion unit,
45 scanning signal drive circuit, 46 display signal drive circuit,
47 pixels, 48, 49 External wiring, 50 TFT
51 opening edge, 52 notch

Claims (10)

A thin film transistor array substrate having thin film transistors,
A gate wiring formed on the substrate and connected to the gate electrode of the thin film transistor;
A gate insulating film covering the gate electrode and the gate wiring;
A semiconductor layer formed on the gate insulating film and formed at least in a region facing the gate electrode;
A source wiring connected to the source electrode of the thin film transistor and formed on the semiconductor layer;
A drain electrode formed on the semiconductor layer so as to face the source electrode across a channel region;
A pixel electrode partly formed directly on the drain electrode and electrically connected to the drain electrode;
On the source electrode and the source wiring, a transparent conductive pattern directly overlapped and formed by the same layer as the pixel electrode,
An interlayer insulating film covering the pixel electrode and the transparent conductive pattern;
A thin film transistor array substrate comprising: a counter electrode formed on the interlayer insulating film and generating a fringe electric field with the pixel electrode;
A thin film transistor array substrate, wherein an edge of the transparent conductive pattern recedes from the source electrode at a portion of the source electrode facing the channel region. Having at least a contact hole opened in the interlayer insulating film;
2. The thin film transistor array substrate according to claim 1, wherein the opening edge of the contact hole includes a region not on the conductive pattern which is the same layer as the pixel electrode. A thin film transistor array substrate having thin film transistors,
A gate wiring formed on the substrate and connected to the gate electrode of the thin film transistor;
A gate insulating film covering the gate electrode and the gate wiring;
A semiconductor layer formed on the gate insulating film and formed at least in a region facing the gate electrode;
A source wiring connected to the source electrode of the thin film transistor and formed on the semiconductor layer;
A drain electrode formed on the semiconductor layer so as to face the source electrode across a channel region;
A pixel electrode partly formed directly on the drain electrode and electrically connected to the drain electrode;
On the source electrode and the source wiring, a transparent conductive pattern directly overlapped and formed by the same layer as the pixel electrode,
An interlayer insulating film covering the pixel electrode and the transparent conductive pattern;
A thin film transistor array substrate comprising: a counter electrode formed on the interlayer insulating film and generating a fringe electric field with the pixel electrode;
The thin film transistor array substrate, wherein the interlayer insulating film includes an organic insulating film. 4. The thin film transistor array substrate according to claim 3, wherein the interlayer insulating film is formed of a laminate of an organic insulating film and an inorganic insulating film. 5. The thin film transistor array substrate according to claim 4, wherein the inorganic insulating film includes at least one layer of SiN, SiO2, and SOG. A liquid crystal display device comprising the thin film transistor array substrate according to claim 1. A method of manufacturing a thin film transistor array substrate having thin film transistors,
Forming a first metal film on the substrate and then patterning to form a gate electrode of the thin film transistor and a gate wiring connected to the gate electrode;
Forming a gate insulating film covering the gate electrode and the gate wiring;
Forming a semiconductor layer, an ohmic contact film, and a second metal film in this order on the gate insulating film;
Patterning the second metal film to form a source electrode and a drain electrode of the thin film transistor connected on the semiconductor layer to be a channel region of the thin film transistor, and a source wiring connected to the source electrode When,
Etching the semiconductor layer and the ohmic contact film using the patterned second metal film as a mask;
Forming a first transparent conductive film directly overlying the second metal film, patterning the first transparent conductive film, and a pixel electrode partially overlapping directly over the drain electrode; Forming a source electrode and a transparent conductive pattern disposed directly over the source wiring; and
Etching the second metal film and the ohmic contact film using the pixel electrode and the transparent conductive pattern as a mask to expose the semiconductor layer serving as a channel region of the thin film transistor;
Forming an interlayer insulating film covering the pixel electrode and the transparent conductive pattern;
Opening a contact hole in the interlayer insulating film and the gate insulating film;
Forming a second transparent conductive film on the interlayer insulating film, and patterning to form a counter electrode that generates a fringe electric field between the pixel electrode and a conductive pattern; A method of manufacturing a thin film transistor array substrate. In the step of etching the second metal film and the ohmic contact film using the pixel electrode and the transparent conductive pattern as a mask to expose the semiconductor layer serving as a channel region of the thin film transistor, the second metal film 8. The method of manufacturing a thin film transistor array substrate according to claim 7, further comprising a step of etching the transparent conductive film again after the etching. In the step of etching the transparent conductive film again after the etching of the second metal film, the etching rate of the transparent conductive film uses an etching condition higher than that of the second metal film. A method for manufacturing a thin film transistor array substrate according to claim 8. The opening edge of the contact hole includes a region where the first transparent conductive film is not formed, and the second transparent conductive film covers the opening edge in the region. 10. A method for producing a thin film transistor array substrate according to 9.

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