JPH06132535A - Film transistor and its manufacture - Google Patents

Abstract

PURPOSE:To provide a film transistor and its manufacturing method which has a structure where pattern conversion difference can be utilized and shower doping can also be used for manufacture. CONSTITUTION:An island-shaped electrode formation semiconductor layer 2 that includes an offset areas 2e and 2f present between a source electrode part 2s and drain electrode part 2d, and a channel area 2c that connects them, and a gate electrode 4 formed on the island-shaped electrode formation semiconductor layer 2 with a gate insulation film 3 in between are provided, to constitute a film transistor. The gate electrode 4 contains a lower side gate electrode 4a, formed of a semiconductor layer doped with impurities, and an upper side gate electrode 4b, formed of the material which is not etched when etching is performed for forming the lower side electrode 4a. This type of film transistor can be manufactured using the etching pattern whose etching characteristic does not degrade even when temperature rises in shower-doping.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a thin film transistor formed on an insulating substrate having a large area such as an inexpensive glass substrate and a method for manufacturing the thin film transistor. Such a technique is applied to a large area active matrix liquid crystal display or the like.

[0002]

2. Description of the Related Art In recent years, an active matrix type liquid crystal display has been urgently required to have high image quality and a large screen while incorporating peripheral circuits. In this type of liquid crystal display, TFTs are formed in a matrix on a transparent insulating substrate such as a glass substrate so that one thin film transistor (hereinafter referred to as TFT) corresponds to one pixel.

FIG. 18 is an explanatory view of a conventional thin film transistor. In FIG. 18, an island-shaped electrode forming semiconductor layer 02 is formed on an insulating substrate 01. poly-Si
The island-shaped electrode forming semiconductor layer 02 formed by using is composed of a source electrode portion 02s, a drain electrode portion 02d, and a channel region 02c connecting them. A gate insulating film 03 is formed on the island-shaped electrode forming semiconductor layer 02, and a gate electrode 04 is formed on the gate insulating film 03. An interlayer insulating film 05 is formed on the gate electrode 04, and contact holes 05s and 05d are formed on the interlayer insulating film 05. The Al wirings 06 and 07 formed on the interlayer insulating film 05 are connected to the source electrode portion 02s and the drain electrode portion 02d of the island-shaped electrode forming semiconductor layer 02 through the contact holes 05s and 05d. ing. The upper surface of the wirings 06 and 07 is a device protection film 0.
It is covered by 8. As a conventional manufacturing method of the thin film transistor, a gate insulating film 03 is deposited on a silicon island for forming an island-shaped electrode forming semiconductor layer, and ions are implanted into the silicon island using the gate electrode 04 formed thereon as a mask. A method of forming the island-shaped electrode forming semiconductor layer 02 is used.

The island-shaped electrode-forming semiconductor layer 02 is composed of a source electrode portion 02s, a drain electrode portion 02d and a channel region 02c connecting them, but according to the method of manufacturing a thin film transistor as described above, The electrode-forming semiconductor layer 02 has a channel region 02c formed in a portion overlapping the gate electrode 04, and a source electrode portion 02s and a drain electrode portion 02d formed outside the portion overlapping the gate electrode 04. In such a method of manufacturing a thin film transistor, since the channel region 02c of the island-shaped electrode forming semiconductor layer 02 can be formed in a size that does not waste in accordance with the size of the gate electrode 04, the device size can be reduced. There was an advantage in increasing the device density.

For application to an active matrix liquid crystal display or the like, the current driving capability of the TFT is required in order to incorporate the peripheral circuit together with the TFT. Therefore, the poly-Si having a high carrier mobility is used as the channel layer.
It is necessary to use Si-TFT. By the way, in order to hold the drive voltage of the liquid crystal, it is necessary to keep the off current of the poly-Si-TFT arranged in each pixel low, but the electric field near the drain junction of the channel region 02c is large. Therefore, it is known that the leakage current due to field-enhanced emission is large and the off current of the poly-Si-TFT is high. It is said that the high off current of the poly-Si-TFT is because carriers trapped in the trap level near the drain are generated by the electric field of the gate electrode / drain region and are measured as a leak current. (S. Madan et al, IEEE Tran
s. ElectronDevices, Vol. ED-33, No. 10, pp. 1518-1
527, Oct. 1986).

Po which can keep the off current low
A ly-Si-TFT having a structure shown in FIG. 19 is considered. 19, elements corresponding to those shown in FIG. 18 are designated by the same reference numerals. In FIG. 19, an impurity is added to a portion distant from the gate electrode 04 outside the portion of the electrode forming semiconductor layer 02 which overlaps with the gate electrode 04 when viewed from above and below (in a plan view). Electrode part 02s and drain electrode part 02d
Are formed, and offset regions 02e and 02f having a low impurity concentration are formed in a portion close to the gate electrode 04. When impurities are not introduced into the offset regions 02e and 02f, the offset regions 02e and 02f are sometimes referred to as offset gate regions, and the TFT in this case is referred to as an offset gate structure. Also,
When the impurity concentration is low, the offset region 02f is sometimes called a drain region having a low impurity concentration, and the TFT in that case is called an LDD (Lightly Doped Drain) structure TFT.

Regarding the LDD structure TFT, (K.
Tanaka et al, IEEE Electron Device Lett., Vol.
9, NO. 1, Jan. 1988). In the LDD structure TFT, the drain region having a low impurity concentration necessary for suppressing the off current is at least 1.
A dimension of 0 μm or more is required. As a method of forming a drain region with a low impurity concentration and a relatively large size, it is proposed to use the pattern conversion difference from the resist pattern formed by photolithography when processing a gate electrode formed of poly-Si. (JP-A-5
8-204570 gazette). That is, Japanese Patent Laid-Open No. 58-204570 discloses the following technology (A21).
Method for forming an electrode-forming semiconductor layer having a source electrode portion, a drain electrode portion, an offset region in which impurities are injected at a low concentration, and a channel region according to (A26) (LDD
A method of manufacturing a TFT having a structure) is described. (A21) A silicon island for forming an electrode-forming semiconductor layer is formed on an insulating substrate, and a gate insulating film is formed on this silicon island. (A22) A doping gate electrode pattern as a primary doping mask is formed on the gate insulating film. (A23) With the resist pattern left on the dope pink gate electrode pattern, impurities are implanted into the silicon island by a first doping process using the resist pattern as a mask. (A24) With the resist pattern left, the doping gate electrode pattern is side-etched to form a gate electrode. (A25) The resist pattern on the gate electrode is removed. (A26) The electrode forming semiconductor layer is formed by a second doping step of injecting impurities into the silicon island using the gate electrode as a mask.

Further, with the increase in screen size, it is difficult to adapt the ion implantation apparatus used in the LSI process as a method of implanting impurities into the drain region for a glass substrate having a side of 30 cm or more, and it is difficult to apply a dopant. After ionization,
A shower doping method (S. Inoue, Proc. Of IEDM 91, pp. 555-558) in which implantation is performed without mass separation has been used.

However, since the ionization efficiency at the time of performing the above shower doping is poor, the time of the shower doping step (time at the time of ion implantation)
Becomes longer, and the substrate temperature rises when ions are implanted. For this reason, in the method disclosed in Japanese Patent Laid-Open No. 58-204570, the resist mask is carbonized in the shower doping step and cannot be removed.
Therefore, it has been found that shower doping cannot be used in the method utilizing the pattern conversion difference described in the above publication.

In view of the above circumstances, the present invention provides the following (A11)
The content described in is the subject. (A31) To provide a thin film transistor having a structure that can be manufactured by utilizing shower patterning and utilizing a pattern conversion difference, and a manufacturing method thereof.

[0010]

The present invention devised to solve the above problems will now be described. The elements of the present invention are to facilitate correspondence with the elements of the embodiments described later. , The reference numerals of the elements in the embodiments are enclosed in parentheses. The reason why the present invention is described in association with the reference numerals of the embodiments described later is to facilitate the understanding of the present invention.
It is not intended to limit the scope of the invention to the examples. In order to solve the above-mentioned problems, a thin film transistor according to a first invention of the present application has a source electrode portion (2s) and a drain electrode portion (2d).
And an island-shaped electrode-forming semiconductor layer (2) composed of a channel region (2c) connecting them, and formed on the island-shaped electrode-forming semiconductor layer (2) via a gate insulating film (3) A thin film transistor having a gate electrode (4) provided with the following requirements (A1) and (A2): (A1) The gate electrode (4) is a semiconductor to which an impurity is added. A lower gate electrode (4a) formed of a layer and an upper gate electrode (4b) formed of a material that is not etched by the etching for forming the lower gate electrode (4a), (A2)
The gate electrode (4) of the electrode forming semiconductor layer (2)
The source electrode portion (2s) and the drain electrode portion (2d), to which impurities are added, are formed in a portion distant from the gate electrode (4) outside the portion overlapping with the gate electrode (4). Offset regions (2e, 2f) having a low impurity concentration were formed in the adjacent portions.

Further, in the method of manufacturing a thin film transistor according to the second invention of the present application, an island-shaped electrode formed of a source electrode portion (2s), a drain electrode portion (2d) and a channel region (2c) connecting them is formed. The semiconductor layer (2) and the gate insulating film (3) on the island-shaped electrode-forming semiconductor layer (2)
A gate electrode (4) formed through the drain electrode part (2) in which an impurity is added to an outer portion of a portion overlapping with the gate electrode in the electrode forming semiconductor layer.
d) is formed, and a thin film transistor in which an offset region (2e, 2f) having a lower impurity concentration than other regions is formed in a region of the drain electrode portion (2d) near the gate electrode (4), In the method of manufacturing a thin film transistor, which is manufactured using the following steps (A3) to (A8),
(A3) A silicon island (2 ') for forming an island-shaped electrode-forming semiconductor layer (2) is formed on an insulating substrate (1), characterized by having the following requirements (A9) to (A11): Step, that is, a silicon island forming step (A
4) A step of forming a gate insulating film (3) on the silicon island (2 '), that is, a step of forming a gate insulating film, (A5) A mask for primary shower doping on the gate insulating film (3) Step of forming a doping gate electrode pattern (4p), that is, step of forming a doping gate electrode pattern, (A6) Impurity is injected into the silicon island (2 ') using the dope pink gate electrode pattern (4p) as a mask. First
Next shower doping step, (A7) Gate electrode forming step of etching the doping gate electrode pattern (4p) to form a gate electrode (4), (A8)
A step of forming the electrode forming semiconductor layer (2) by a second shower doping step of injecting impurities into the silicon island (2 ′) using the gate electrode (4) as a mask, that is, an electrode forming semiconductor layer forming step, (A9)
In the step (A5), on the gate insulating film (3),
In the etching of the lower gate electrode forming layer (4a ′) formed of the impurity-added semiconductor layer and the lower gate electrode forming layer (4a ′) for forming the lower gate electrode (4a), An upper gate electrode forming layer (4b ') formed of a material that is not etched and a gate electrode pattern layer (9') whose etching characteristics are not deteriorated by the temperature rise during the first shower doping are sequentially formed. A resist pattern in which the resist layer (10 ') is patterned by a photolithography etching after forming a resist layer (10') on the gate electrode pattern layer (9 ') by a laminating step. (10), the pattern (9) of the pattern layer in which the gate electrode pattern layer (9 ') is patterned, and the electrode forming layers (4a') (4b ') Having a step of forming a turning has been doped electrode pattern (4p), a, (A10) the primary shower doping process (A
6) is performed in a state where the resist pattern (10) formed in the step (A5) is removed and the pattern layer pattern (9) is left, (A11) The gate electrode forming step (A7) ) Side etches the lower gate electrode forming layer (4a ') of the doping gate electrode pattern (4p) while leaving the pattern layer pattern (9) formed in the step (A5). Thereby forming the lower gate electrode (4a), and thereafter,
Forming an upper gate electrode (4b) by etching the upper gate electrode forming layer (4b ′) of the doping gate electrode pattern (4p) using the pattern (9) of the patterning layer as a mask. To have.

[0012]

In the thin film transistor according to the first invention of the present application having the above-mentioned structure, the gate electrode (4) has a lower gate electrode (4a) formed of an impurity-added semiconductor layer and the lower gate electrode (4a). It has an upper gate electrode (4b) formed of a material that is not etched by the etching for forming (4a). When the gate electrode (4) has such a structure, the source electrode portion (2s),
An island-shaped electrode forming semiconductor layer (2) composed of a drain electrode portion (2d) and a channel region (2c) connecting them, and a gate insulating film (on the island-shaped electrode forming semiconductor layer (2) When manufacturing a thin film transistor having the gate electrode (4) formed via 3), a manufacturing method (manufacturing method of the second invention) using a pattern doping difference and shower doping is used. Can be adopted. Then, by adopting the manufacturing method, the source in which impurities are added to a portion apart from the gate electrode (4) in an outer portion of a portion of the electrode forming semiconductor layer overlapping the gate electrode (4). Electrode part (2
s) and the drain electrode portion (2d) are formed, and a thin film transistor in which an offset region having a low impurity concentration and a uniform dimension is formed in a portion close to the gate electrode (4) can be obtained. In a thin film transistor having an evenly sized offset region, the electric field in the vicinity of the drain junction of the channel region (2c) is small, and therefore the leak current is small.

According to the method of manufacturing a thin film transistor of the second invention of the present application having the above-mentioned constitution, in the silicon island forming step, the silicon island for forming the island-shaped electrode forming semiconductor layer (2) is formed on the insulating substrate (1). (2 ') is formed. Next, in a gate insulating film forming step, a gate insulating film (3) is formed on the silicon island (2 '). Next, in a step of forming a gate electrode pattern for doping, a lower gate electrode forming layer (4a ') formed of a semiconductor layer to which impurities are added and a lower gate electrode are formed on the gate insulating film (3). An upper gate electrode forming layer (4b ') made of a material that is not etched by etching the lower gate electrode forming layer (4a') to form (4a), and the temperature during the first shower doping. A gate electrode pattern layer (9 ') whose etching characteristics do not deteriorate due to the rise is sequentially formed. After that, a resist layer (10 ') is formed on the gate electrode pattern layer (9') and then the resist layer (10 ') is patterned by photolithography etching. A pattern layer pattern (9) in which the gate electrode pattern layer (9 ') is patterned, and a doping electrode pattern (4p) in which the electrode forming layers (4a') and (4b ') are patterned. )
To form.

The pattern (9) of the pattern layer and the gate electrode pattern (4p) for doping have the following first structure.
It is used as a mask for the next shower doping. Next, in the first shower doping step, with the resist pattern (10) removed and the pattern layer pattern (9) left, the dope gate electrode pattern (4p) is used as a mask. Impurities are implanted into the silicon islands (2 '). At this time, impurities are implanted into the source electrode portion (2s) and the drain electrode portion (2d) of the silicon island (2 ').

Next, in the gate electrode forming step, the lower gate electrode forming layer (4a ') of the doping gate electrode pattern (4p) is side-etched while leaving the pattern (9) of the patterning layer. By doing so, the lower gate electrode (4a) is formed. Then, the upper gate electrode forming layer (4b ') of the doping gate electrode pattern (4p) is etched by using the pattern (9) of the patterning layer as a mask to form the upper gate electrode (4b). Thus, the doping gate electrode pattern (4p) is etched to form the gate electrode (4). Next, in the electrode forming semiconductor layer forming step, the electrode forming semiconductor layer (2) is formed by a second shower doping step of injecting impurities into the silicon island (2 ′) using the gate electrode (4) as a mask. . At this time, the offset region (2c) and the source electrode portion (2
s) and impurities are injected into the drain electrode part (2d).

[0016]

1 is a structural explanatory view of an embodiment of a thin film transistor of the present invention. In FIG. 1, an island-shaped electrode-forming semiconductor layer 2 made of a poly-Si material is formed on an insulating substrate 1. The island-shaped electrode-forming semiconductor layer 2 includes a source electrode portion 2s formed on the left and right outer portions, a drain electrode portion 2d, a channel region 2c formed between them, and a channel region 2c and the source electrode portion 2s. And the offset regions 2e and 2f formed between the drain electrode 2d and the drain electrode 2d. Impurities (for example, phosphorus P) are implanted (added) into the source electrode portion 2s, the drain electrode portion 2d, and the offset regions 2e and 2f. The concentration of the impurities injected into the offset regions 2e and 2f is set to be lower than that of the source electrode 2s and the drain electrode portion 2d.

A gate insulating film (SiO 2 film) 3 is formed on the island-shaped electrode-forming semiconductor layer 2, and a gate electrode 4 is formed on the gate insulating film 3.

The gate electrode 4 is composed of upper and lower two layers of electrodes. That is, the gate electrode 4 is the lower gate electrode 4a.
And the upper gate electrode 4b. The lower gate electrode 4a is made of poly-containing impurities such as phosphorus and boron.
It is made of a Si semiconductor layer and has a thickness of 3000 angstroms. The upper gate electrode 4b is made of a material that is not etched by the etching material for patterning the lower gate electrode 4a, for example, platinum, and has a film thickness of 300 angstroms.

The channel region 2c is located substantially directly below the gate electrode 4 as a reference. The offset regions 2e and 2f formed between the channel region 2c and the drain electrode portion 2d and between the channel region 2c and the source electrode portion 2s are the gate electrodes of the electrode forming semiconductor layer 2. Is formed on the outer side of the overlapping portion when seen in a plan view.

An interlayer insulating film 5 (SiO2) is formed on the upper surface of the upper gate electrode 4b. Contact holes 5s and 5d communicating with the source electrode portion 2s and the drain electrode portion 2d are formed in the interlayer insulating film 5.
Al (aluminum) electric wires 6 and 7 are provided on the interlayer insulating film 5. The electric wires 6 and 7 are connected to the source electrode portion 2s and the drain via the contact holes 5s and 5d. The electrode portion 2d is connected to an electric circuit (not shown).

Next, the operation of the above-described thin film transistor embodiment will be described. As described above, the gate electrode 4 is composed of the lower gate electrode 4a and the upper gate electrode 4 made of a material that is not etched by the etching for forming the lower gate electrode.
If it is composed of b and b, the manufacturing method described later can be adopted. Then, it is possible to obtain a thin film transistor in which the offset regions 2e and 2f are uniform. In this case, the electric field in the vicinity of the drain junction of the channel region 2c becomes small and the leak current becomes small.

(Manufacturing method of the TFT of the embodiment shown in FIG. 1) Next, a manufacturing method of the embodiment of the thin film transistor having the above-mentioned structure will be described with reference to FIGS. In FIG. 2, amorphous silicon (hereinafter, also referred to as a-Si) C (decompressed) C is formed on a transparent insulating substrate (quartz substrate) 1.
It is deposited by the VD method. The thickness of the a-Si film is 1000 angstrom. The film forming temperature at this time is 550 ° C. The entire surface of this a-Si film is irradiated with a KrF excimer laser. The irradiation intensity is 450 mJ / (1 square cm)
And By this irradiation, the a-Si layer is crystallized into polycrystalline silicon (hereinafter referred to as poly-Si). Next, the poly-Si layer is patterned by a photolithography method to form a silicon island 2'as shown in FIG.

Next, as shown in FIG. 4, SiO2 is deposited on the insulating substrate 1 so as to cover the silicon island 2 ', and a gate insulating film 3 is formed. The gate insulating film 3 has a thickness of 1000 Å.

Next, as shown in FIGS. 5 and 6, upper and lower two layers of lower gate electrode forming layer 4a 'and upper gate electrode forming layer 4b' are formed. That is, first, on the upper surface of the gate insulating film 3, a doped-type doped with impurities such as phosphorus and boron is added.
LPCVD of lower gate electrode forming layer 4a 'with poly-Si
And the thickness is set to 3000 angstrom (see FIG. 5). At this time, the film forming temperature is 580 ° C., the gas pressure is 300 mTorr, and the gas flow rate is SiH4: P.
H3 = 100: 20 sccm. Next, as shown in FIG. 6, an upper gate electrode forming layer 4b 'is deposited on the lower gate electrode forming layer 4a'. This upper gate
The gate electrode forming layer 4b 'is a lower gate electrode forming layer 4a'.
A material that is not etched with an etching material for patterning, such as platinum, is used to form a film by sputtering. The film deposition conditions at this time are
Gas pressure is 10mTorr, plasma power is 2.0K
At W, the film thickness is 300 Å.

Next, as shown in FIG. 7, a gate electrode pattern is formed on the upper gate electrode forming layer 4b 'by the same LPCVD method as that for forming the silicon island 2'. Layer 9'is formed to a thickness of 5000 angstroms. For the gate electrode pattern layer 9 ', poly-Si containing no impurities such as phosphorus and boron is used. This poly-Si is a material whose etching characteristics do not deteriorate due to a temperature rise during shower doping described later.

Next, as shown in FIG. 8, a resist layer is formed on the gate electrode pattern layer 9 ', and then a resist pattern 10 is formed by photolithographic etching.

Next, etching is performed in order from the upper layer. That is, first, the chemical dry etching method (CDE method)
Thus, as shown in FIG. 9, the gate electrode pattern layer 9'is etched to form the pattern 9 of the pattern layer. The condition at this time is that the gas flow rate is CF4: O2 =
300: 90 sccm, gas pressure 200 mTorr,
The plasma power is 400W.

Next, as shown in FIG. 10, the upper gate electrode forming layer 4b 'is etched with aqua regia to form a doping upper electrode pattern 4bp.

Next, as shown in FIG. 11, the same method as when the gate electrode pattern layer 9'is etched,
Under the same conditions, the lower gate electrode forming layer 4a 'is etched to form the doping lower electrode pattern 4ap.
A doping electrode pattern 4p is formed from the doping lower electrode pattern 4ap and the doping upper electrode pattern 4bp. Resist pattern 1 at this stage
0 is removed (see FIG. 12).

Then, in the state shown in FIG. 12, that is, with the resist pattern 10 removed, phosphorus is implanted into the silicon island 2'through the gate insulating film 3 through the gate insulating film 3. That is, the first shower doping is performed. This first shower doping is 100 KeV per
By injecting phosphorus ions of energy of 5 × (10 15 to the power of 15) per 1 cm 2 into the silicon island 2 ′ by using the pattern 9 of the patterning layer and the doping electrode pattern 4 p as a mask, To do. As a result of this shower doping, the silicon island 2 ′ has impurities outside the region directly below the pattern 9 of the pattern layer and the doping electrode pattern 4 p (the region overlapping with the doping electrode pattern 4 p in plan view). Injected. A region of the silicon island 2'that overlaps the doping electrode pattern 4p is the channel electrode portion 2c and the offset region 2
e and 2f are portions, and both outer portions thereof are the source electrode portion 2s and the drain electrode portion 2d.

Next, the pattern 9 of the pattern layer and the lower electrode pattern 4 for doping are formed by the CDE method.
Etch ap at the same time. At this time, etching is performed until the pattern 9 of the pattern layer has a thickness of 500 Å. At this time, the lower electrode pattern 4ap for doping is underside-etched as compared with the upper gate electrode pattern 4bp for doping to form a lower gate electrode 4a, as shown in FIG. At this time, the pattern 9 of the patterning layer and the doping lower electrode pattern 4ap are side-etched by the same material at the same time by substantially the same amount, and thus have substantially the same shape (size) in a plan view.

Next, as shown in FIG. 14, etching is performed again using aqua regia so that the doping upper gate electrode pattern 4bp has the same size as the lower gate electrode 4a, and the upper gate is etched. Forming an electrode 4b. A gate electrode 4 is formed from the lower gate electrode 4a and the upper gate electrode 4b.

Next, as shown in FIG. 15, the pattern 9 of the patterning layer having a thickness of 500 angstrom, which was left a little, is removed.

The electrode forming semiconductor layer 2 is further processed to form L
In order to obtain the DD structure, phosphorus ions are implanted into the electrode-forming semiconductor layer 2 using the gate electrode 4 as a mask by secondary shower doping as shown in FIG. This implantation is the same as the above-mentioned formation of the source electrode portion 2s and the drain electrode portion 2d in that phosphorus ions having an energy of 100 KeV are used, but one square c
The difference is that 5 × (10 to the 12th power) are input per m, which is three orders of magnitude smaller. By this secondary shower doping, a channel region 2c is formed in a region of the silicon island 2'that overlaps with the gate electrode 4,
Offset regions 2e and 2f are formed on the outer side portions thereof, and a source electrode portion 2s and a drain electrode portion 2d are further formed on the outer side portions thereof. Impurities (phosphorus) are injected into the source electrode portion 2s and the drain electrode portion 2d by the first and second shower doping, and the impurity concentration is high. However, the impurity concentration is low in the offset regions 2e and 2f because the impurities are implanted only by the secondary shower doping.

In order to activate the dopants (impurities) implanted as described above, heat treatment is performed for 60 hours in a nitrogen atmosphere at 550 ° C., or a KrF excimer laser is irradiated at an intensity of 300 mJ / square cm. To do.

Next, a thickness of 7,000 angstroms is formed on the entire surface.
The silicon oxide film of the aluminum is deposited, and as shown in FIG.
The interlayer insulating film 5 is formed. Next, the interlayer insulating film 5 and the gate insulating film 3 are penetrated from the upper surface of the interlayer insulating film 5.
Contact holes 5d and 5s reaching the drain electrode portion 2d and the source electrode portion 2s are opened.

Next, aluminum is deposited on the entire surface by a sputtering method, and patterning is performed to connect the drain electrode portion 2d and the source electrode portion 2s to an electric circuit (not shown) 7, 8 (see FIG. 1),
The TFT of the embodiment shown in FIG. 1 is manufactured.

The operation of the first embodiment of the method of manufacturing a thin film transistor described above will be described below. The process shown in FIG. 12, that is,
In the first shower doping step of first implanting phosphorus ions into the silicon island 2 ′, if the resist doping temperature is 200 ° C. or higher during shower doping, carbonization occurs at 200 ° C. and the resist layer 10 that cannot be removed in the subsequent etching step is a mask material. The pattern material 9 which is not used as the mask material at this time is the pattern layer pattern 9 whose etching characteristics do not deteriorate due to the temperature increase during shower doping. Can be easily removed in a later etching process.

In the step shown in FIG. 13, that is, in the step of etching the doping lower electrode pattern 4ap,
The upper gate electrode pattern for doping 4bp above the lower electrode pattern for doping 4ap is formed of a material which is not etched by the etching material for patterning the lower electrode pattern for doping 4ap.
The amount of underside etching of the doping lower electrode pattern 4ap can be arbitrarily determined. Under this time
The side etching amount corresponds to the remaining amount of the remaining portion of the pattern 9 on the patterning layer. Therefore, the regions shown in FIG. 16, that is, the regions where the impurity concentration is low, that is, the offset regions 2e and 2f formed in the secondary shower doping process, are formed.
The width of can be controlled and set to an arbitrary value. Therefore, this width can be uniformly set to a value necessary for suppressing the off current (leak current), for example, an arbitrary value of 1.0 micron or more.

(Modification) The embodiment of the thin film transistor according to the present invention has been described in detail above. However, the present invention is not limited to the above embodiment, and deviates from the invention described in the claims. It is possible to make various design changes without the need. For example, instead of implanting impurities into the offset regions 2e and 2f to form a thin film transistor having an LDD structure, it is possible to form a thin film transistor having an offset gate structure without implanting impurities. Although platinum is used as the material of the upper gate electrode 4b in the first embodiment, various materials that are not etched by the etching for forming the lower gate electrode 4a, for example,
It is also possible to use chromium and palladium.

[0041]

The thin film transistor of the present invention having the above-described structure has the following effects (A41). (A41) It can be manufactured by utilizing the pattern conversion difference and using shower doping. Further, the method of manufacturing a thin film transistor according to the present invention described above has the following effect (A42). (A42) When the first shower doping is performed, a mask material whose etching characteristics are not deteriorated by this shower doping is used, so that the etching can be performed in the subsequent step of the mask material. Therefore, the shower
Doping methods can be used in the manufacturing process.
Further, since the lower electrode pattern for doping is underside-etched using the upper electrode pattern for doping, which is not subjected to etching when performing etching for forming the lower gate electrode, as a reference mask, this underlayer etching is performed. By controlling the amount of side etching, this amount can be made uniform in each TFT. Impurity ions are implanted again into the electrode forming semiconductor layer using the lower gate electrode pattern formed by underside etching the lower electrode pattern for doping and the upper gate electrode pattern thereabove as a mask. As a result, a uniform offset region can be provided between the channel region and the drain electrode part and between the channel region and the source electrode part. In that case, the electric field in the vicinity of the drain junction of the channel region is reduced, and the leak current can be reduced.

[Brief description of drawings]

FIG. 1 is a first embodiment of a thin film transistor of the invention.
FIG.

FIG. 2 is an explanatory view showing a method of manufacturing the thin film transistor of Embodiment 1 in the order of steps, and is a cross-sectional view.

FIG. 3 is an explanatory view showing a method of manufacturing the thin film transistor according to the first embodiment in the order of steps, and is a cross-sectional view.

FIG. 4 is an explanatory view showing a method of manufacturing the thin film transistor according to the first embodiment in the order of steps, and is a cross-sectional view.

FIG. 5 is an explanatory view showing a method of manufacturing the thin film transistor according to the first embodiment in the order of steps, and is a cross-sectional view.

6A and 6B are explanatory views showing a method of manufacturing the thin film transistor according to the first embodiment in the order of steps, and are cross-sectional views.

FIG. 7 is an explanatory view showing the method of manufacturing the thin film transistor of the first embodiment in the order of steps, and is a cross-sectional view.

FIG. 8 is an explanatory diagram showing the method of manufacturing the thin film transistor of the first embodiment in the order of steps, and is a cross-sectional view.

FIG. 9 is an explanatory view showing the method of manufacturing the thin film transistor of the first embodiment in the order of steps, and is a cross-sectional view.

FIG. 10 is an explanatory view showing a method of manufacturing the thin film transistor of Embodiment 1 in the order of steps, and is a cross-sectional view.

FIG. 11 is an explanatory diagram showing the method of manufacturing the thin film transistor of the first embodiment in the order of steps, and is a cross-sectional view.

FIG. 12 is an explanatory view showing the method of manufacturing the thin film transistor of the first embodiment in the order of steps, and is a cross-sectional view.

FIG. 13 is an explanatory view showing the method of manufacturing the thin film transistor of Embodiment 1 in the order of steps, and is a cross-sectional view.

FIG. 14 is an explanatory diagram showing the method of manufacturing the thin film transistor of the first embodiment in the order of steps, and is a cross-sectional view.

FIG. 15 is an explanatory view showing the method of manufacturing the thin film transistor of Embodiment 1 in the order of steps, and is a cross-sectional view.

FIG. 16 is an explanatory diagram showing the method of manufacturing the thin film transistor of Embodiment 1 in the order of steps, and is a cross-sectional view.

FIG. 17 is an explanatory diagram showing the method of manufacturing the thin film transistor of Embodiment 1 in the order of steps, and is a cross-sectional view.

FIG. 18 shows a conventional thin film transistor,
FIG.

FIG. 19 is a cross-sectional view showing a conventional thin film transistor having an offset region.

[Explanation of symbols]

2 ... Electrode forming semiconductor layer, 2 '... Silicon island (po
ly-Si island), 2c ... Channel region, 2d ... Drain electrode part, 2s ... Source electrode part, 2e, 2f ... Offset region, 3 ... Gate insulating film, 4 ... Gate electrode, 4a ... Lower gate electrode, 4a ' ... Lower gate electrode forming layer, 4ap ...
Lower gate electrode pattern for doping, 4b ... Upper gate electrode, 4b '... Upper gate electrode forming layer, 4bp ... Upper gate electrode pattern for doping, 9 ... Pattern layer pattern, 9' ... Gate electrode Pattern layer,

Claims (2)

[Claims] 1. An island-shaped electrode forming semiconductor layer composed of a source electrode portion, a drain electrode portion and a channel region connecting them, and a gate insulating film formed on the island-shaped electrode forming semiconductor layer. A thin film transistor having a gate electrode formed by: a thin film transistor having the following requirements (A1) and (A2): (A1) The gate electrode is formed of an impurity-doped semiconductor layer. Having a lower gate electrode and an upper gate electrode formed of a material that is not etched by etching for forming the lower gate electrode, (A2) An outer portion of a portion of the electrode-forming semiconductor layer that overlaps the gate electrode. The source electrode part and the drain electrode part, to which impurities are added, are formed in a portion distant from the gate electrode. The low offset region impurity concentration is formed on the proximate portion. 2. An island-shaped electrode forming semiconductor layer composed of a source electrode portion, a drain electrode portion and a channel region connecting them, and a gate insulating film formed on the island-shaped electrode forming semiconductor layer. And a drain electrode portion to which an impurity is added is formed in an outer portion of a portion overlapping with the gate electrode in the electrode forming semiconductor layer, and the gate electrode of the drain electrode portion is formed. In a method of manufacturing a thin film transistor in which a thin film transistor in which an offset region having a lower impurity concentration than other regions is formed in an adjacent region using the following steps (A3) to (A8), the following requirements (A9) to (A11) A method for manufacturing a thin film transistor, characterized by comprising: (A3) An island-shaped electrode-forming silicon island for forming a semiconductor layer is formed on an insulating substrate. (A4) forming a gate insulating film on the silicon island, (A5) forming a doping gate electrode pattern as a first shower doping mask on the gate insulating film, (A6) A first shower doping step of implanting impurities into the silicon island using the dope pink gate electrode pattern as a mask; (A7) a gate electrode forming step of etching the doping gate electrode pattern to form a gate electrode; ) A step of forming the electrode forming semiconductor layer by a second shower doping step of injecting an impurity into the silicon island by using the gate electrode as a mask, (A9) the step (A5) is performed on the gate insulating film,
Lower gate electrode forming layer formed by a semiconductor layer to which impurities are added, and upper gate electrode forming by a material that is not etched by etching of the lower gate electrode forming layer for forming the lower gate electrode Layers,
A stacking step of sequentially forming a gate electrode pattern layer in which etching characteristics are not deteriorated by a temperature rise during the first shower doping, and then, the gate electrode pattern is formed.
Forming a resist layer on the pattern layer, each electrode forming layer is patterned by photolithoetching, a doping electrode pattern, the gate electrode pattern layer is a patterned layer pattern pattern, And a step of forming a patterned resist pattern of the resist layer, (A10) the first shower doping step (A6)
Is performed in a state where the resist pattern formed in the step (A5) is removed and the pattern layer pattern is left, (A11) The gate electrode forming step (A7) is performed in the step (A5) A step of forming a lower gate electrode by side-etching the lower gate electrode forming layer of the doping gate electrode pattern with the pattern of the pattern layer formed in 1. left, and thereafter, the pattern layer Forming the upper gate electrode by etching the upper gate electrode forming layer of the doping gate electrode pattern using the pattern as a mask.