JPH05152326A - Manufacturing method of thin film transistor - Google Patents
Manufacturing method of thin film transistorInfo
- Publication number
- JPH05152326A JPH05152326A JP31784991A JP31784991A JPH05152326A JP H05152326 A JPH05152326 A JP H05152326A JP 31784991 A JP31784991 A JP 31784991A JP 31784991 A JP31784991 A JP 31784991A JP H05152326 A JPH05152326 A JP H05152326A
- Authority
- JP
- Japan
- Prior art keywords
- thin film
- resist
- manufacturing
- pattern
- forming
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
- 239000010409 thin film Substances 0.000 title claims abstract description 48
- 238000004519 manufacturing process Methods 0.000 title claims description 22
- 238000005530 etching Methods 0.000 claims abstract description 23
- 238000000034 method Methods 0.000 claims abstract description 15
- 239000000758 substrate Substances 0.000 claims abstract description 12
- 239000012212 insulator Substances 0.000 claims abstract description 8
- 239000004065 semiconductor Substances 0.000 claims abstract description 6
- 239000002019 doping agent Substances 0.000 claims abstract description 4
- 230000015572 biosynthetic process Effects 0.000 claims abstract 3
- 229910021420 polycrystalline silicon Inorganic materials 0.000 claims description 15
- 238000005468 ion implantation Methods 0.000 claims description 2
- 239000010408 film Substances 0.000 abstract description 12
- 239000004020 conductor Substances 0.000 abstract 1
- 229920005591 polysilicon Polymers 0.000 description 14
- 239000010410 layer Substances 0.000 description 9
- 239000004973 liquid crystal related substance Substances 0.000 description 8
- 229910004298 SiO 2 Inorganic materials 0.000 description 7
- 229910021417 amorphous silicon Inorganic materials 0.000 description 6
- 238000007796 conventional method Methods 0.000 description 3
- 239000002184 metal Substances 0.000 description 3
- 229920002120 photoresistant polymer Polymers 0.000 description 3
- UFHFLCQGNIYNRP-UHFFFAOYSA-N Hydrogen Chemical compound [H][H] UFHFLCQGNIYNRP-UHFFFAOYSA-N 0.000 description 2
- 229910052739 hydrogen Inorganic materials 0.000 description 2
- 239000001257 hydrogen Substances 0.000 description 2
- 238000002161 passivation Methods 0.000 description 2
- 238000000137 annealing Methods 0.000 description 1
- 238000005229 chemical vapour deposition Methods 0.000 description 1
- 238000002425 crystallisation Methods 0.000 description 1
- 230000008025 crystallization Effects 0.000 description 1
- 238000001312 dry etching Methods 0.000 description 1
- 238000001035 drying Methods 0.000 description 1
- 239000012535 impurity Substances 0.000 description 1
- 238000009413 insulation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 230000001678 irradiating effect Effects 0.000 description 1
- 239000000463 material Substances 0.000 description 1
- 238000000206 photolithography Methods 0.000 description 1
- 238000005268 plasma chemical vapour deposition Methods 0.000 description 1
- 230000007261 regionalization Effects 0.000 description 1
- 239000007787 solid Substances 0.000 description 1
- 238000004544 sputter deposition Methods 0.000 description 1
- 238000005406 washing Methods 0.000 description 1
- XLYOFNOQVPJJNP-UHFFFAOYSA-N water Substances O XLYOFNOQVPJJNP-UHFFFAOYSA-N 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
- H01L29/76—Unipolar devices, e.g. field effect transistors
- H01L29/772—Field effect transistors
- H01L29/78—Field effect transistors with field effect produced by an insulated gate
- H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
- H01L29/78606—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device
- H01L29/78618—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure
- H01L29/78621—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with supplementary region or layer in the thin film or in the insulated bulk substrate supporting it for controlling or increasing the safety of the device characterised by the drain or the source properties, e.g. the doping structure, the composition, the sectional shape or the contact structure with LDD structure or an extension or an offset region or characterised by the doping profile
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
- H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
- H01L29/66007—Multistep manufacturing processes
- H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
- H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
- H01L29/66409—Unipolar field-effect transistors
- H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
- H01L29/66742—Thin film unipolar transistors
- H01L29/6675—Amorphous silicon or polysilicon transistors
- H01L29/66757—Lateral single gate single channel transistors with non-inverted structure, i.e. the channel layer is formed before the gate
Landscapes
- Engineering & Computer Science (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Ceramic Engineering (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Manufacturing & Machinery (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は、液晶を駆動する液晶表
示装置や画像読み取り用センサ等に用いられている薄膜
トランジスタの製造方法、とりわけ比較的低温（６００
℃以下）で形成されたポリシリコン薄膜を用いたポリシ
リコン薄膜トランジスタの製造方法に関するものであ
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a thin film transistor used in a liquid crystal display device for driving a liquid crystal, an image reading sensor, etc.
The present invention relates to a method for manufacturing a polysilicon thin film transistor using a polysilicon thin film formed at a temperature of not higher than ° C.
【０００２】[0002]
【従来の技術】以下、液晶表示装置用に応用検討が進め
られているポリシリコン薄膜トランジスタ（以下ＴＦＴ
と呼ぶ）とその製法の一例を説明する。2. Description of the Related Art Polysilicon thin film transistors (hereinafter referred to as TFTs) are being studied for application to liquid crystal display devices.
Will be described) and an example of the manufacturing method will be described.
【０００３】近年ＴＦＴを用いた液晶表示の分野では、
比較的低温（６００℃以下）で形成されたポリシリコン
ＴＦＴが注目を集めている（例えば雑誌「フラットパネ
ル・ディスプレイ１９９１」，pp.117［日経ＢＰ社発
行］を参照）。ところで、ポリシリコンＴＦＴの重大な
欠点の一つにリ−ク電流が大きいことがあげられ、特に
画素電極用のＴＦＴの場合大きな問題となる。このため
オフセット構造やＬＤＤ（ライトリィ−・ド−プト・ド
レイン）構造のトランジスタの検討がなされている。図
３は従来のＬＤＤ構造のポリシリコンＴＦＴの製造方法
を説明するためのトランジスタ部の工程断面図である。
以下に、この従来の製法について簡単に説明する（ポリ
シリコンＴＦＴの製造方法については、世良他、１９８
９年秋期、第５０回応用物理学会学術講演会講演予稿集
２７ａ−Ａ−２，pp.539を参照）。In recent years, in the field of liquid crystal display using TFT,
Polysilicon TFTs formed at a relatively low temperature (600 ° C. or lower) have been attracting attention (see, for example, magazine “Flat Panel Display 1991”, pp.117 [published by Nikkei BP]). By the way, one of the serious drawbacks of the polysilicon TFT is that the leak current is large, which is a serious problem particularly in the case of the pixel electrode TFT. Therefore, a transistor having an offset structure or an LDD (lightly doped drain) structure has been studied. 3A to 3D are process cross-sectional views of a transistor portion for explaining a conventional method of manufacturing a polysilicon TFT having an LDD structure.
The conventional manufacturing method will be briefly described below (for the method of manufacturing a polysilicon TFT, see Sera et al., 198).
See the proceedings of the 50th Annual Meeting of the Japan Society of Applied Physics 27th A-A-2, pp.539, Autumn 9th year).
【０００４】まず基板１上にソ−スドレインとなるべき
部位に高濃度の不純物を含んだポリシリコン層２を形成
し、その上にアモルファスシリコン層３を形成する（図
３（ａ））。次にエキシマレ−ザ−を照射することによ
りアモルファスシリコン層３を多結晶化しポリシリコン
層３’を形成する（図３（ｂ））。次にゲ−ト絶縁膜４
とゲ−ト電極５を形成し、ゲ−ト電極５をド−ピングマ
スクにイオン注入を行い低濃度のソ−スドレイン領域
（ＬＤＤ領域）Ｌ１とＬ２を形成する。つづいてパッシ
ベイション膜６を形成し、メタル電極７を形成すること
によりＬＤＤ構造のＴＦＴを作製している。なおポリシ
リコン層２とゲ−ト電極５は露光機を用いたフォトリソ
グラフィ−工程でパタ−ン形成されている。First, a polysilicon layer 2 containing a high concentration of impurities is formed on a substrate 1 at a portion to be a source drain, and an amorphous silicon layer 3 is formed thereon (FIG. 3 (a)). Next, the amorphous silicon layer 3 is polycrystallized by irradiation with an excimer laser to form a polysilicon layer 3 '(FIG. 3 (b)). Next, the gate insulating film 4
A gate electrode 5 is formed, and ion implantation is performed using the gate electrode 5 as a doping mask to form low-concentration source drain regions (LDD regions) L1 and L2. Subsequently, a passivation film 6 is formed, and a metal electrode 7 is formed to manufacture a TFT having an LDD structure. The polysilicon layer 2 and the gate electrode 5 are patterned by a photolithography process using an exposure device.
【０００５】[0005]
【発明が解決しようとする課題】しかしながら、図３の
ような製法でＬＤＤ構造のポリシリコンＴＦＴを作製す
る場合、以下の課題が問題となる。However, when the polysilicon TFT having the LDD structure is manufactured by the manufacturing method as shown in FIG. 3, the following problems occur.
【０００６】すなわち、露光機を使ったフォトマスクの
位置合わせにはばらつきがあるため、低濃度のソ−スド
レイン領域（ＬＤＤ領域）Ｌ１とＬ２の幅が場所により
変化してしまい、このためトランジスタ特性にばらつき
が生じるという点である。液晶表示装置の場合非常に多
数（数万〜数百万個）のトランジスタをばらつきなく作
る必要があり、特に大型基板を用いる場合、複数の露光
領域を繋ぎ合わせて分割露光する場合が多く、繋目の部
分でＬ１とＬ２の比が急激に変化する場合があり事態は
深刻である。That is, since there are variations in the alignment of the photomask using the exposure machine, the widths of the low-concentration source drain regions (LDD regions) L1 and L2 change depending on the location, which results in transistor characteristics. That is, there are variations. In the case of a liquid crystal display device, it is necessary to make a very large number (tens of thousands to millions) of transistors without variation. Especially, when a large substrate is used, it is often the case that a plurality of exposure regions are connected to perform divided exposure. The situation is serious because the ratio of L1 and L2 may change rapidly in the eye area.
【０００７】次に、ＬＤＤ領域はソ−スドレイン領域２
とゲ−ト電極５との２つのパタ−ン間に確実に作る必要
があり、これに伴い、ＬＤＤ領域Ｌ１とＬ２の幅は位置
合わせマ−ジンの倍以上の幅（液晶表示装置の製造に用
いる大型基板対応の露光機では数μｍの幅）で設計する
ことが必要となる。このためＬＤＤ構造を取らない場合
に比べて素子サイズが大きくなるという問題が２つめの
課題である。液晶表示装置の画素電極用ＴＦＴが目的の
場合、できるだけ画素の開口率（有効領域）を大きく取
る必要があるので、素子サイズがしばしば設計上の問題
点となる。とりわけ高密度のタイプでは素子サイズをい
かに小さくするかが大きな課題となっている。Next, the LDD region is the source drain region 2
It is necessary to surely form between the two patterns of the gate electrode 5 and the gate electrode 5, and accordingly, the widths of the LDD regions L1 and L2 are more than double the width of the alignment margin (manufacturing of liquid crystal display device). It is necessary to design the exposure machine for a large substrate used for the above with a width of several μm). Therefore, the second problem is that the device size becomes larger than that in the case where the LDD structure is not adopted. When the purpose is a pixel electrode TFT of a liquid crystal display device, it is necessary to make the aperture ratio (effective area) of the pixel as large as possible, so that the element size often becomes a design problem. Particularly in the high-density type, how to reduce the element size is a big issue.
【０００８】本発明は、このような従来のＴＦＴの製造
方法の課題を考慮し、ＬＤＤ領域がほぼ同一の幅にで
き、素子サイズを小さくできるＴＦＴの製造方法を提供
することを目的とするものである。The present invention has been made in view of the above problems of the conventional method of manufacturing a TFT, and an object of the present invention is to provide a method of manufacturing a TFT in which the LDD regions can have substantially the same width and the element size can be reduced. Is.
【０００９】[0009]
【課題を解決するための手段】本発明は、基板上に半導
体薄膜と絶縁体薄膜と導電性薄膜を形成する工程と、導
電性薄膜上にレジストのパタ−ンを作成する工程と、こ
のレジストのパタ−ンと比べてサイドエッチングを有す
る形状に導電性薄膜をエッチングすることにより電極を
形成する工程と、レジストのパタ−ンを用いて電極形成
時のサイドエッチングより小さなサイドエッチング量で
絶縁体薄膜をエッチングする工程と、半導体層へ高濃度
のド−ピング（第１のド−パント導入工程）を行う工程
を使って薄膜トランジスタを製造する。SUMMARY OF THE INVENTION The present invention comprises a step of forming a semiconductor thin film, an insulator thin film and a conductive thin film on a substrate, a step of forming a resist pattern on the conductive thin film, and the resist. The step of forming an electrode by etching the conductive thin film into a shape having side etching as compared with the pattern of 1., and the insulator pattern with a smaller side etching amount than the side etching at the time of forming the electrode by using the resist pattern. A thin film transistor is manufactured using a step of etching a thin film and a step of performing high-concentration doping (first doping step) on a semiconductor layer.
【００１０】[0010]
【作用】本発明では、電極の周りに露光機等の位置合わ
せ機構を持った装置を使うことなく、しかもセルフアラ
インにＬＤＤ領域が形成され、かつゲ−ト電極の両サイ
ドに作り込まれるＬＤＤ領域はほぼ同一の幅でできあが
る。しかも条件によっては露光機の位置合わせマ−ジン
よりはるかに小さい幅でＬＤＤ領域が形成されることに
なる。According to the present invention, the LDD region is formed in self-alignment without using a device having a positioning mechanism such as an exposure device around the electrodes, and the LDD is formed on both sides of the gate electrode. The areas are made up of almost the same width. Moreover, depending on the conditions, the LDD region is formed with a width much smaller than the alignment margin of the exposure machine.
【００１１】[0011]
【実施例】以下、本発明の実施例について図面を参照し
て説明する。Embodiments of the present invention will be described below with reference to the drawings.
【００１２】図１は本発明の一実施例の薄膜トランジス
タの製造方法を説明するための工程断面図である。FIG. 1 is a process sectional view for explaining a method of manufacturing a thin film transistor according to an embodiment of the present invention.
【００１３】SiO2膜をアンダ−コ−トとして被着した基
板１上にプラズマＣＶＤ法でアモルファスシリコン（膜
厚約１００ｎｍ）を形成する。この後アモルファスシリ
コン中の水素の一部を取り去るために４５０℃で１時間
真空中でアニ−ルを行い、さらにトランジスタ素子サイ
ズにアモルファスシリコンを分離（エッチングによるパ
タ−ン形成）した後、エキシマレ−ザ−光（波長３０８
ｎｍ）を照射し結晶化を行い、ポリシリコン層１０を形
成する（図１（ａ））。次にゲ−ト絶縁膜として用いる
SiO2薄膜１１をＥＣＲ−ＣＶＤ法で被着し、さらにCr薄
膜１２（膜厚５０〜１００ｎｍ）をスパッタ法で被着す
る。そしてゲ−ト電極を形成する部位にフォトレジスト
（この場合長瀬ネガレジスト７４７を用いた）のパタ−
ン１３を形成する（図１（ｂ））。次に、Cr薄膜をウェ
ットエッチングでエッチングしオ−バ−エッチングをか
けることによりレジストのパタ−ン端から約１μｍ内側
までサイドエッチングを行いゲ−ト電極１２’を形成す
る（図１（ｃ））。そして十分に水洗そして乾燥させた
後、基板１に対して１６０℃の温度で３０分間ベ−キン
グを行いサイドエッチング部をレジスト１３でカバ−す
る（ネガレジストの多くがこの製法に適している）。Amorphous silicon (having a thickness of about 100 nm) is formed by plasma CVD on the substrate 1 with the SiO 2 film as an undercoat. Then, in order to remove a part of hydrogen in the amorphous silicon, annealing is performed in vacuum at 450 ° C. for 1 hour, and the amorphous silicon is further separated into a transistor element size (pattern formation by etching). The light (wavelength 308
(nm) for crystallization to form a polysilicon layer 10 (FIG. 1A). Next, use as a gate insulating film
The SiO 2 thin film 11 is deposited by the ECR-CVD method, and further the Cr thin film 12 (film thickness 50 to 100 nm) is deposited by the sputtering method. Then, a pattern of photoresist (in this case, Nagase negative resist 747 is used) is formed on the portion where the gate electrode is formed.
To form the film 13 (FIG. 1B). Next, the Cr thin film is etched by wet etching and over-etched to perform side etching from the pattern end of the resist to about 1 .mu.m inside to form a gate electrode 12 '(FIG. 1 (c)). ). Then, after sufficiently washing with water and drying, the substrate 1 is baked at a temperature of 160 ° C. for 30 minutes to cover the side-etched portion with the resist 13 (most negative resists are suitable for this manufacturing method). .
【００１４】この状態のレジストを使ってゲ−ト絶縁膜
として用いるSiO2薄膜１１を異方性の高いドライエッチ
ング法でエッチングしSiO2薄膜パタ−ン１１’を形成す
る（図２（ｄ））。このときSiO2薄膜１１のサイドエッ
チング量ＳＥ１はゲ−ト電極のサイドエッチング量ＳＥ
２より小さくなるように設定している。この後レジスト
１３を除去し、イオンシャワ−ド−ピング法（あるいは
バケットタイプイオンド−プ法；たとえば、イクステンテ゛ット゛
アフ゛ストラクト オフ゛ 22(1990インターナショナル)コンフェレンス オンソリット゛ ステー
ト テ゛ハ゛イセス アント゛ マテーリアルス゛(Extended Abstracts of the
22nd (1990 international) Conference on SOLID STAT
E DEVICES AND MATERIALS),PP.971 またはPP.1197 に記
述されている方法である）を用いてド−ピング（第１の
ド−パント導入工程）を行った（図２（ｅ））。そして
この後、エキシマレ−ザ−光を再度照射することにより
導入されたド−パントの活性化をはかり、層間絶縁用の
絶縁膜SiO2膜１４を形成し、コンタクトホ−ルを形成
し、メタル配線１５を形成することによりポリシリコン
薄膜トランジスタが完成する（図２（ｆ））。なお図面
には記入していないが、このトランジスタを作り込んだ
基板１を水素プラズマにさらす事によりトランジスタ特
性の改善を行っている。そしてこの製造方法の場合（図
２（ｆ））のＬ３部がＬＤＤ領域となる。Using the resist in this state, the SiO 2 thin film 11 used as a gate insulating film is etched by a highly anisotropic dry etching method to form a SiO 2 thin film pattern 11 '(FIG. 2 (d)). ). At this time, the side etching amount SE1 of the SiO 2 thin film 11 is equal to the side etching amount SE of the gate electrode.
It is set to be smaller than 2. After that, the resist 13 is removed and an ion shower doping (or bucket type ion doping);
22nd (1990 international) Conference on SOLID STAT
E DEVICES AND MATERIALS), which is the method described in PP.971 or PP.1197) was used to perform doping (first doping step) (FIG. 2 (e)). Then, after this, by irradiating the excimer laser light again, the introduced dopant is activated to form an insulating film SiO 2 film 14 for interlayer insulation, a contact hole is formed, and a metal is formed. A polysilicon thin film transistor is completed by forming the wiring 15 (FIG. 2F). Although not shown in the drawing, the transistor characteristics are improved by exposing the substrate 1 having the transistor formed therein to hydrogen plasma. In the case of this manufacturing method (FIG. 2 (f)), the L3 portion becomes the LDD region.
【００１５】[0015]
【発明の効果】以上説明したように、本発明を実施する
ことにより、ゲ−ト電極の周りにセルフアラインにＬＤ
Ｄ領域が形成され、かつゲ−ト電極の両サイドに作り込
まれるＬＤＤ領域はほぼ同一の幅でできあがる。As described above, by carrying out the present invention, the LD is self-aligned around the gate electrode.
The LDD regions in which the D regions are formed and are formed on both sides of the gate electrode have almost the same width.
【００１６】このため両サイドのＬＤＤ領域の幅とバラ
ンスが従来例のように場所によりばらつくことはなくな
り、これに伴うトランジスタ特性のばらつきがたいへん
小さくなる。For this reason, the width and balance of the LDD regions on both sides do not vary from place to place as in the conventional example, and the variation in transistor characteristics accompanying this is very small.
【００１７】また、ＬＤＤ領域はゲ−ト電極エッチン時
のサイドエッチング部を活用して作成しており、フォト
マスク工程の位置合わせマ−ジンよりはるかに小さな幅
（サブミクロンも可能）で作成でき、従来のＬＤＤ構造
を取らない場合とほぼ同一サイズでありながらリ−ク電
流の小さいＬＤＤ構造をもった薄膜トランジスタを作成
できるという長所を有する。従って、たとえばより高性
能な液晶表示が可能となる。Further, the LDD region is formed by utilizing the side etching portion at the time of etching the gate electrode, and can be formed with a width (submicron is possible) much smaller than the alignment margin in the photomask process. Another advantage is that it is possible to fabricate a thin film transistor having an LDD structure with a small leak current even though it has almost the same size as the conventional LDD structure. Therefore, for example, higher performance liquid crystal display is possible.
【図１】本発明にかかる一実施例の薄膜トランジルタの
製造方法を説明するための一部の工程断面図である。FIG. 1 is a partial process cross-sectional view for explaining a method of manufacturing a thin film transistor according to an embodiment of the present invention.
【図２】本発明にかかる一実施例の薄膜トランジルタの
製造方法を説明するための残りの工程断面図である。FIG. 2 is a cross sectional view of the remaining steps for explaining the method for manufacturing a thin film transistor according to one embodiment of the present invention.
【図３】従来の薄膜トランジルタの製造方法を説明する
ための工程断面図である。FIG. 3 is a process sectional view for explaining a conventional method for manufacturing a thin film transistor.
１ 基板 ２，３’，１０ ポリシリコン層 ３ アモルファスシリコン層 ４，１２’ ゲ−ト絶縁膜 ５ ゲ−ト電極 ６ パッシベイション膜 ７ メタル電極 １１ SiO2薄膜 １２ Ｃｒ薄膜 １３ レジストのパタ−ン Ｌ１〜Ｌ３ ＬＤＤ領域 ＳＥ１，ＳＥ２ サイドエッチング量1 Substrate 2, 3 ', 10 Polysilicon Layer 3 Amorphous Silicon Layer 4, 12' Gate Insulating Film 5 Gate Electrode 6 Passivation Film 7 Metal Electrode 11 SiO 2 Thin Film 12 Cr Thin Film 13 Resist Pattern L1 to L3 LDD area SE1, SE2 Side etching amount
───────────────────────────────────────────────────── フロントページの続き (72)発明者 筒 博司 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 (72)発明者 宮田 豊 大阪府門真市大字門真1006番地 松下電器 産業株式会社内 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Hiroshi Tsutsuba 1006 Kadoma, Kadoma City, Osaka Prefecture Matsushita Electric Industrial Co., Ltd. (72) Yutaka Miyata, 1006 Kadoma, Kadoma City, Osaka Matsushita Electric Industrial Co., Ltd.
Claims (5)
絶縁体薄膜を形成する工程と、導電性薄膜を形成する工
程と、前記導電性薄膜上にレジストのパタ−ンを作成す
る工程と、前記レジストのパタ−ンと比べてサイドエッ
チングを有する形状に前記導電性薄膜をエッチングする
ことにより電極を形成する工程と、前記レジストのパタ
−ンを用いて前記電極形成時のサイドエッチングより小
さなサイドエッチング量で前記絶縁体薄膜をエッチング
する工程と、前記半導体薄膜へのド−パント導入工程と
を備えたことを特徴とする薄膜トランジスタの製造方
法。1. A step of forming a semiconductor thin film on a substrate,
A step of forming an insulator thin film, a step of forming a conductive thin film, a step of forming a resist pattern on the conductive thin film, and a shape having side etching as compared with the resist pattern. A step of forming an electrode by etching the conductive thin film; a step of etching the insulator thin film with a side etching amount smaller than a side etching at the time of forming the electrode using a pattern of the resist; And a step of introducing a dopant into a thin film.
前記レジストにべ−キングを行い電極形成時の前記サイ
ドエッチングの少なくとも一部分を前記レジストでカバ
−することを特徴とする請求項１記載の薄膜トランジス
タの製造方法。2. The thin film transistor according to claim 1, wherein the resist is baked prior to the step of etching the insulator thin film to cover at least a part of the side etching during electrode formation. Production method.
用いることを特徴とする請求項２記載の薄膜トランジス
タの製造方法。3. The method of manufacturing a thin film transistor according to claim 2, wherein a negative type resist is used as the resist.
照射により結晶化を行った多結晶シリコン薄膜を前記半
導体薄膜に用いることを特徴とする請求項１記載の薄膜
トランジスタの製造方法。4. An insulating substrate is used as the substrate, and a laser is used.
2. The method for manufacturing a thin film transistor according to claim 1, wherein a polycrystalline silicon thin film crystallized by irradiation is used as the semiconductor thin film.
オンシャワ−ド−ピング法またはプラズマド−ピング法
を用いることを特徴とする請求項１記載の薄膜トランジ
スタの製造方法。5. The method of manufacturing a thin film transistor according to claim 1, wherein an ion implantation method, an ion shower doping method, or a plasma doping method is used in the dopant introduction step.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31784991A JPH05152326A (en) | 1991-12-02 | 1991-12-02 | Manufacturing method of thin film transistor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP31784991A JPH05152326A (en) | 1991-12-02 | 1991-12-02 | Manufacturing method of thin film transistor |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| JPH05152326A true JPH05152326A (en) | 1993-06-18 |
Family
ID=18092744
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP31784991A Pending JPH05152326A (en) | 1991-12-02 | 1991-12-02 | Manufacturing method of thin film transistor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPH05152326A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0645802A2 (en) * | 1993-09-20 | 1995-03-29 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| US6335290B1 (en) | 1998-07-31 | 2002-01-01 | Fujitsu Limited | Etching method, thin film transistor matrix substrate, and its manufacture |
| US7618881B2 (en) | 2006-01-23 | 2009-11-17 | Nec Corporation | Thin-film transistor and manufacturing method thereof |
-
1991
- 1991-12-02 JP JP31784991A patent/JPH05152326A/en active Pending
Cited By (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| EP0645802A2 (en) * | 1993-09-20 | 1995-03-29 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| EP0645802A3 (en) * | 1993-09-20 | 1998-03-11 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| US6049092A (en) * | 1993-09-20 | 2000-04-11 | Semiconductor Energy Laboratory Co., Ltd. | Semiconductor device and method for manufacturing the same |
| US6335290B1 (en) | 1998-07-31 | 2002-01-01 | Fujitsu Limited | Etching method, thin film transistor matrix substrate, and its manufacture |
| US6534789B2 (en) | 1998-07-31 | 2003-03-18 | Fujitsu Limited | Thin film transistor matrix having TFT with LDD regions |
| US7618881B2 (en) | 2006-01-23 | 2009-11-17 | Nec Corporation | Thin-film transistor and manufacturing method thereof |
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