KR20010055071A - Method for manufacturing thin film transistor - Google Patents
Method for manufacturing thin film transistor Download PDFInfo
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- KR20010055071A KR20010055071A KR1019990056138A KR19990056138A KR20010055071A KR 20010055071 A KR20010055071 A KR 20010055071A KR 1019990056138 A KR1019990056138 A KR 1019990056138A KR 19990056138 A KR19990056138 A KR 19990056138A KR 20010055071 A KR20010055071 A KR 20010055071A
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- thin film
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- 239000010409 thin film Substances 0.000 title claims abstract description 37
- 238000000034 method Methods 0.000 title claims abstract description 30
- 238000004519 manufacturing process Methods 0.000 title claims abstract description 11
- 229920002120 photoresistant polymer Polymers 0.000 claims abstract description 17
- 239000002184 metal Substances 0.000 claims abstract description 15
- 229910052710 silicon Inorganic materials 0.000 claims abstract description 13
- 239000010703 silicon Substances 0.000 claims abstract description 13
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims abstract description 12
- 238000000206 photolithography Methods 0.000 claims abstract description 12
- 239000004020 conductor Substances 0.000 claims abstract description 4
- 238000000059 patterning Methods 0.000 claims abstract description 4
- 238000005530 etching Methods 0.000 claims abstract description 3
- 238000000151 deposition Methods 0.000 claims description 4
- 238000010030 laminating Methods 0.000 claims description 2
- 239000000758 substrate Substances 0.000 abstract description 5
- 239000004065 semiconductor Substances 0.000 abstract description 2
- 239000010410 layer Substances 0.000 description 55
- 229910021420 polycrystalline silicon Inorganic materials 0.000 description 7
- 239000010408 film Substances 0.000 description 5
- 229910021417 amorphous silicon Inorganic materials 0.000 description 4
- 230000002950 deficient Effects 0.000 description 3
- 238000005468 ion implantation Methods 0.000 description 3
- 239000004973 liquid crystal related substance Substances 0.000 description 3
- 239000011159 matrix material Substances 0.000 description 3
- 230000015572 biosynthetic process Effects 0.000 description 2
- 238000007796 conventional method Methods 0.000 description 2
- 230000007547 defect Effects 0.000 description 2
- 229920005591 polysilicon Polymers 0.000 description 2
- 229910004298 SiO 2 Inorganic materials 0.000 description 1
- 230000004913 activation Effects 0.000 description 1
- 230000000295 complement effect Effects 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 238000011156 evaluation Methods 0.000 description 1
- 239000011229 interlayer Substances 0.000 description 1
- 238000002161 passivation Methods 0.000 description 1
- 230000002250 progressing effect Effects 0.000 description 1
- 230000027756 respiratory electron transport chain Effects 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/1288—Multistep manufacturing methods employing particular masking sequences or specially adapted masks, e.g. half-tone mask
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
- H01L27/1259—Multistep manufacturing methods
- H01L27/127—Multistep manufacturing methods with a particular formation, treatment or patterning of the active layer specially adapted to the circuit arrangement
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- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Thin Film Transistor (AREA)
Abstract
Description
본 발명은 박막트랜지스터의 제조방법에 관한 것으로, 특히 구동회로를 내장한 액티브 매트릭스형 액정 표시소자의 스위칭소자로 활용되고 있는 박막 트랜지스터에서 저누설전류를 위한 LDD 혹은 오프셋 영역을 가지는 박막 트랜지스터 및 CMOS 구동회로를 적은 수의 포토 마스크 공정으로 얻을 수 있는 박막 트랜지스터의 제조 방법에 관한 것이다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method for manufacturing a thin film transistor, and more particularly, a thin film transistor and a CMOS driving circuit having an LDD or offset region for low leakage current in a thin film transistor that is used as a switching element of an active matrix liquid crystal display device having a built-in driving circuit. The present invention relates to a method for manufacturing a thin film transistor which can be obtained by a small number of photo mask processes.
박막 트랜지스터는 액티브 매트릭스 액정 표시장치와 같은 평판 표시소자 등에서 픽셀의 온 오프 스위칭소자로 널리 활용되고 있다. 여기에 적용되는 박막 트랜지스터는 내전압성과 온 오프 전류비가 높아야 하는 조건을 충족해야 한다.The thin film transistor is widely used as an on / off switching device of a pixel in a flat panel display device such as an active matrix liquid crystal display device. The thin film transistors to be applied here must satisfy the condition that the voltage resistance and the on-off current ratio must be high.
박막 트랜지스터의 종류는 비정질 실리콘 트랜지스터와 다결정 실리콘 트랜지스터가 알려져 있으며, 비정질 실리콘에 비해 다결정 실리콘이 전자 이동율 등의 성능과 신뢰도 면에서 더 좋은 평가를 내리고 있지만 고온 분위기에서 막 형성되는 문제가 있어서 일반적으로는 비정질 실리콘 박막 트랜지스터가 실용화되고 있다.The types of thin film transistors are known as amorphous silicon transistors and polycrystalline silicon transistors, and polycrystalline silicon has a better evaluation in terms of performance and reliability such as electron transfer rate than amorphous silicon. Amorphous silicon thin film transistors have been put into practical use.
그러나 최근에 엑시머레이저 장비 등을 활용하여 막 형성을 위한 고온 분위기를 간단하고 저렴한 비용으로 조성할 수 있는 기술적 진보가 이루어짐에 따라 다결정 실리콘 박막 트랜지스터에 대한 관심이 고조되고 있는 실정이다.Recently, however, interest in polycrystalline silicon thin film transistors has been increasing due to technological advances that can easily and inexpensively form a high temperature atmosphere for film formation using excimer laser equipment.
상기 액티브 매트릭스 액정 표시장치에서는 반도체의 한쪽으로 게이트, 소스 및 드레인전극을 위치시키는 코플래너 구조(평면형 구조)를 선호하는 경향이 있다.상기 코플래너 구조는 소자의 크기를 최소화할 수 있고, PMOS와 NMOS를 함께 갖추어 상호간의 장단점을 보완하는 특성을 가진다.In the active matrix liquid crystal display device, a coplanar structure (planar structure) in which the gate, source, and drain electrodes are positioned to one side of the semiconductor tends to be preferred. The coplanar structure can minimize the size of the device, and It is equipped with NMOS to complement each other's advantages and disadvantages.
도 2는 종래의 일반적인 코플래너 구조로 된 박막 트랜지스터를 도시하고 있다.2 shows a thin film transistor having a conventional coplanar structure.
도면에서 기판(1)과 버퍼층(2)의 상면 소정 개소에는 포토 리소그라피법에 의해 패터닝되어서 적층 형성된 활성층(3)이 위치하고, 상기 활성층(3)은 절연막(4)에 의해 코팅되고, 이 절연막(4)에는 다시 게이트 메탈층이 증착된 후에 포토 리소그라피 공정을 거쳐 소정의 게이트전극(5)이 위치하게 된다.In the drawing, an active layer 3 formed by patterning and stacking the substrate 1 and the buffer layer 2 by a photolithography method is positioned, and the active layer 3 is coated with an insulating film 4, and this insulating film ( In 4), the gate metal layer is again deposited, and then a predetermined gate electrode 5 is positioned through a photolithography process.
상기와 같이 게이트전극(5)을 형성한 다음, 잔여 포토 레지스트층을 제거하고 새로운 포토 레지스트층을 도포하되, 상기 게이트전극(5) 보다 약간 큰 폭으로 도포되도록 패터닝하고 노광, 현상한 후 이온 주입하여 상기 활성층(3)의 양단부에 소스 또는 드레인 콘택층을 정의하여 놓고, 상기 활성층(3)의 양단부에 n-영역을 형성하여 n웰을 형성하고 포토 레지스트층을 제거한 후에 가볍게 이온 도핑시키면 상기 게이트전극(5)과 콘택층 사이로 LDD영역(6)이 남게 된다. 이후, p-영역을 형성하여 p도핑을 수행함으로써 p영역 활성화층을 형성한다.After forming the gate electrode 5 as described above, the remaining photoresist layer is removed and a new photoresist layer is applied, but patterned, exposed and developed so as to have a slightly larger width than the gate electrode 5, and then ion implanted. The source or drain contact layers are defined at both ends of the active layer 3, n-regions are formed at both ends of the active layer 3 to form n wells, and the photoresist layer is removed. The LDD region 6 remains between the electrode 5 and the contact layer. Subsequently, p-regions are formed to form p-region activation layers by performing p doping.
상기 게이트전극(5)의 상면에 층간절연막(7)을 적층하고 상기 콘택층과 연통되는 비아홀을 형성한 다음, 금속막을 증착하여 소스전극(8) 또는 드레인전극(9)를 형성한다.An interlayer insulating film 7 is stacked on the upper surface of the gate electrode 5, a via hole communicating with the contact layer is formed, and a metal film is deposited to form a source electrode 8 or a drain electrode 9.
마지막으로 소스전극(8)과 드레인전극(9)의 상면에 패시베이션층(10)을 형성하고 필요 개소에 비아홀을 정의한 후 ITO 등의 화소전극(11)을 형성한다.Finally, the passivation layer 10 is formed on the upper surfaces of the source electrode 8 and the drain electrode 9, and via holes are defined in the required positions, and then pixel electrodes 11 such as ITO are formed.
이와 같은 종래의 박막 트랜지스터 제조 공정에서 포토 리소그라피 공정은 적어도 9회 실시되기 때문에 공정 수의 증가에 따른 생산성의 저하 문제와 제품 불량률의 증가 문제를 피할 수 없었다. 특히 도핑을 위한 포토 마스크 공정은 기판 패턴, 게이트 패턴, n+ 이온주입, n- 이온주입, p+ 이온주입의 5회로 실시되어야 하기 때문에 공정 수를 줄이는데 큰 장애로 작용하고 있다.Since the photolithography process is performed at least nine times in the conventional thin film transistor manufacturing process, it is inevitable to reduce the productivity and increase the product defect rate according to the increase in the number of processes. In particular, the photo mask process for doping has to be performed five times: substrate pattern, gate pattern, n + ion implantation, n− ion implantation, and p + ion implantation.
따라서 본 발명의 목적은 도핑을 위한 포토 마스크의 공정 실시 회수를 줄여서 공정 단축 및 불량률의 감소, 그리고 생산성의 향상을 도모할 수 있는 박막 트랜지스터의 제조 방법을 제공함에 있다.Accordingly, an object of the present invention is to provide a method for manufacturing a thin film transistor which can reduce the number of times the photomask is processed for doping, thereby shortening the process, reducing a defective rate, and improving productivity.
상기의 목적을 달성하기 위하여 본 발명은 마스크를 이용한 포토 리소그라피법으로 패터닝하여 소정 개소에 활성층을 마련하는 공정과, 상기 활성층의 상면 전체에 게이트 절연층을 적층 형성하고 그 위로 금속층을 증착 형성하는 공정과, 상기 금속층을 포토 리소그라피법으로 식각하여 소정개소에 게이트전극이 적층 형성되게 하는 공정과, 상기 게이트전극을 마스크로 삼아 n+ 도핑을 행하여 화소부분 및 CMOS부분의 n-박막의 활성층 양측부가 n+ 실리콘층으로 도핑되게 하는 공정과, 상기 각 게이트전극의 상방으로 포토 레지스트를 도포하고 패터닝하여 화소부분의 n-박막의 게이트전극과 CMOS부분의 p-박막의 게이트전극을 소정 폭으로 축소시킴과 동시에 CMOS부분의 n-박막의 게이트전극 주변이 소정폭으로 실드되게 하는 공정과, 상기 화소부분의 상방을 마스크로 실드하고 CMOS를 p+ 도핑하여 p-박막의 활성층양측으로 p+ 실리콘층이 도핑 형성되게 하는 공정과, 상기 각 게이트전극에 도포된 포토 레지스트을 제거하고 전체 면에 절연층을 적층 형성한 다음 소정개소마다 콘택홀을 형성하는 공정과, 상기 콘택홀로 금속 또는 ITO 등의 도전물질을 증착하여 소스전극과 드레인전극이 인출되게 하는 공정으로 행해진다.In order to achieve the above object, the present invention provides a process for forming an active layer at a predetermined position by patterning by photolithography using a mask, and forming a gate insulating layer on the entire upper surface of the active layer and depositing a metal layer thereon. And etching the metal layer by a photolithography method so that gate electrodes are stacked at a predetermined position, and n + doping using the gate electrode as a mask to perform n + doping so that both sides of the active layer of the n-thin film of the pixel portion and the CMOS portion are n + silicon. And a photoresist applied and patterned above each gate electrode to reduce the gate electrode of the n-thin film of the pixel portion and the gate electrode of the p-thin film of the CMOS portion to a predetermined width and simultaneously A step of shielding a portion around the gate electrode of the n-thin film in a predetermined width and an image of the pixel portion Shielding with a mask and p + doping the CMOS to form a p + silicon layer on both sides of the active layer of the p-thin film, removing the photoresist applied to each of the gate electrodes, laminating an insulating layer on the entire surface, and then And forming a contact hole for each point, and depositing a conductive material such as metal or ITO into the contact hole to draw the source electrode and the drain electrode.
이 때, 상기 게이트전극의 상방으로 포토 레지스트층을 적층 형성한 후에 CMOS부분을 마스크로 실드하고 화소부분을 n- 도핑하여 그 하측의 활성층에 LDD 영역이 형성되게 하는 공정을 더 포함할 수도 있다.In this case, the method may further include forming a LDD region on the lower active layer by shielding the CMOS portion with a mask and n-doping the pixel portion after stacking the photoresist layer on the gate electrode.
만약, 화소부분을 n- 도핑하지 않으면 오프셋 영역이 형성된다.If the pixel portion is not n-doped, an offset region is formed.
상술한 본 발명은 공정의 전반에 걸쳐 포토 리소그라피의 반복 횟수가 대폭 줄어들기 때문에 종래의 방법에 비하여 획기적으로 공정 수를 줄일 수 있어서 얼라인에 의한 불량률을 감소시킬 수 있다.In the present invention described above, since the number of repetitions of photolithography is drastically reduced throughout the process, the number of processes can be drastically reduced as compared to the conventional method, thereby reducing the defective rate due to alignment.
도 1a 내지 도 1j는 본 발명에 따른 박막 트랜지스터의 제조 방법을 도시하는 공정순서도.1A to 1J are process flowcharts showing a method for manufacturing a thin film transistor according to the present invention.
도 2는 종래의 CMOS 폴리 실리콘 박막 트랜지스터의 구조를 도시하는 단층도.Fig. 2 is a tom diagram showing the structure of a conventional CMOS polysilicon thin film transistor.
**도면의 주요부분에 대한 부호의 설명**** Description of the symbols for the main parts of the drawings **
20 : 기판 22 : 버퍼층20: substrate 22: buffer layer
24 : 활성층 26 : 게이트절연층24: active layer 26: gate insulating layer
28 : 금속층 30 : 게이트전극28 metal layer 30 gate electrode
32 : n+ 실리콘층 36 : 마스크32: n + silicon layer 36: mask
38 : LDD 영역(n-층) 40 : p+ 실리콘층38: LDD region (n-layer) 40: p + silicon layer
42 : 절연층 44 : 콘택홀42: insulating layer 44: contact hole
46 : 소스전극 48 : 드레인전극46 source electrode 48 drain electrode
이하, 첨부된 도면을 참조하여 본 발명의 제조 방법에 관한 바람직한 실시 예를 상세히 설명한다.Hereinafter, with reference to the accompanying drawings will be described in detail a preferred embodiment of the manufacturing method of the present invention.
도 1a 내지 도 1g는 본 발명에 따른 박막 트랜지스터의 제조 방법을 도시하는 공정 단면도이다.1A to 1G are cross-sectional views illustrating a method of manufacturing a thin film transistor according to the present invention.
도 1a를 참조하면, 기판(20) 상부에 형성된 SiO2 버퍼층(22) 상부에 증착된 비정질 실리콘 상면에 엑시머레이저 등을 조사하여 다결정 실리콘으로 되게 한후, 포토 리소그라피법으로 상기 다결정 실리콘을 패터닝하여 활성층(24)을 형성한다.Referring to FIG. 1A, an excimer laser or the like is irradiated to an upper surface of an amorphous silicon deposited on an SiO 2 buffer layer 22 formed on a substrate 20 to form polycrystalline silicon, and then the polycrystalline silicon is patterned by photolithography to form an active layer ( 24).
활성층(24)의 형성을 끝낸 후에 그 상면 전체에 도 1b의 도시와 같이 게이트절연층(26)을 적층 형성하고, 이어서 상기 게이트절연층(26)을 포함한 모든 영역에 금속층(28)을 증착하여 적층한다.After the formation of the active layer 24, the gate insulating layer 26 is laminated on the entire upper surface, as shown in FIG. 1B, and then the metal layer 28 is deposited on all regions including the gate insulating layer 26. Laminated.
다음에 상기 금속층(28)을 포토 리소그라피법에 따라 식각하여 도 1c의 도시와 같이 소정개소에 게이트전극(30)이 적층되게 한다. 이 때, 화소부분의 n-박막 게이트전극과 CMOS부분의 p-박막 게이트전극을 실제로 원하는 폭보다 넓게 패터닝한다. 이렇게 하여 적층 형성된 게이트전극(30)을 마스크로 한 셀프 얼라인 방식으로 도 1d의 도시와 같이 n+ 도핑을 행하여 게이트절연층(26)을 개재한 채로 대치하고 있는 활성층(24)의 양측부가 n+ 실리콘층(32)으로 되게 한다.Next, the metal layer 28 is etched by the photolithography method so that the gate electrodes 30 are stacked at predetermined positions as shown in FIG. 1C. At this time, the n-thin gate electrode in the pixel portion and the p-thin gate electrode in the CMOS portion are actually patterned wider than the desired width. In this manner, n + doping is performed in a self-aligned manner using the gate electrodes 30 formed as a mask as shown in FIG. 1D, and both sides of the active layer 24 replaced with the gate insulating layer 26 are interposed with n + silicon. Layer 32.
그리고나서 상기 게이트전극(30)의 상방으로 포토 레지스트를 도포하고 패터닝하여 도 1e의 도시와 같이 화소부분의 n-박막의 게이트전극(30)과 CMOS부분의 p- 박막의 게이트전극(30)이 각각 소정 폭으로 축소된 채로 포토 레지스트층(34)에 의해 피복되게 함과 동시에 CMOS부분의 n- 박막의 게이트전극(30) 주변은 상기 포토 레지스트층(34)에 의해 상기 n+ 실리콘층(32)까지 실드되게 한다.Then, the photoresist is applied and patterned above the gate electrode 30 to form the n-thin gate electrode 30 of the pixel portion and the p-thin gate electrode 30 of the CMOS portion as shown in FIG. The n-silicon layer 32 is covered by the photoresist layer 34 around the gate electrode 30 of the n− thin film in the CMOS portion while being covered by the photoresist layer 34 while being reduced to a predetermined width, respectively. To be shielded.
다음에 도 1f의 도시와 같이 CMOS를 마스크(36)로 실드하고 화소부분만 n- 도핑되게 한다. 이에 따라 상기 화소부분에서는 게이트전극(30)을 마스크로 하여 n- 도핑되는 것이므로 도 1f의 도시와 같이 활성층(24)의 양측에는 n+ 실리콘층(32)과의 사이로 LDD 영역(38)이 형성되어진다. 또한 상기 LDD 영역을 단지 오프셋 영역으로 존치시키고자 할 때는 도 1f의 도핑 공정을 생략하면 된다.Next, as shown in FIG. 1F, the CMOS is shielded with a mask 36 and only the pixel portion is n-doped. Accordingly, since the pixel portion is n-doped using the gate electrode 30 as a mask, an LDD region 38 is formed between the n + silicon layer 32 on both sides of the active layer 24 as shown in FIG. 1F. Lose. In addition, the doping process of FIG. 1F may be omitted when the LDD region is to be merely an offset region.
이와 같이 화소부분에 LDD 영역(38) 또는 오프셋 영역을 마련하고 나서 도1g에 도시된 바와 같이, 마스크(36')를 상기 화소부분에 장착한 다음 CMOS부분을 p+ 도핑한다. 이 때 CMOS부분의 n-박막은 게이트전극(30)의 주변이 포토 레지스트층(34)으로 두텁게 피복되어 있기 때문에 그 하측의 n+ 실리콘층(32)은 도핑에 영향을 받지 않게 보호되고, 다만 p-박막의 활성층(24)이 그 상방의 게이트전극(30)을 마스크로 도핑되는 결과가 되어 p+ 실리콘층(40)이 상기 활성층(24)의 양측부에 형성된다.After the LDD region 38 or the offset region is formed in the pixel portion as described above, as shown in FIG. 1G, the mask 36 'is mounted on the pixel portion, and the CMOS portion is p + doped. At this time, since the n-thin film in the CMOS portion is thickly covered with the photoresist layer 34 around the gate electrode 30, the n + silicon layer 32 below is protected from doping, but p The result is that the thin active layer 24 is doped with the upper gate electrode 30 as a mask so that the p + silicon layer 40 is formed on both sides of the active layer 24.
이와 같이 화소부분의 n-박막의 게이트전극과 CMOS부분의 n-박막 및 p+박막의 게이트전극의 상측 포토 레지스트층(34)을 제거하면 도 1h의 도시와 같은 적층 구조를 가지게 된다. 다음에 도 1i의 도시와 같이 상기 게이트전극(30)의 상면으로 절연층(42)을 적층 형성하고 소정개소마다 콘택홀(44)을 형성한 다음 형성된 콘택홀(44)로 금속 또는 ITO 등의 도전물질을 증착하면 도 1j의 도시와 같이 외부로 소스전극(46)과 드레인전극(48)이 인출된 소망의 박막 트랜지스터를 얻게 된다.As such, when the upper photoresist layer 34 of the n-thin gate electrode of the pixel portion and the n-thin and p + thin gate electrode of the CMOS portion is removed, a stacked structure as shown in FIG. 1H is obtained. Next, as shown in FIG. 1I, an insulating layer 42 is formed on the upper surface of the gate electrode 30, and contact holes 44 are formed at predetermined positions. Then, the formed contact holes 44 may be formed of metal or ITO. When the conductive material is deposited, a desired thin film transistor having the source electrode 46 and the drain electrode 48 drawn out is obtained as shown in FIG. 1J.
이상 설명한 본 발명은 CMOS 회로가 내장된 폴리 실리콘 박막 트랜지스터의 제조에서 포토 리소그라피 공정이 종래 방법에 비해 2회 줄어 드는 효과가 있기 때문에 생산성의 향상과 제품 불량률을 감소시킬 수 있는 잇점이 있다.The present invention described above has the advantage that the photolithography process can be reduced twice compared to the conventional method in the production of a polysilicon thin film transistor with a CMOS circuit, thereby improving productivity and reducing product defect rate.
또 포토 마스크 공정에 있어서도 마스크는 단지 화소의 n-박막소자와 CMOS를 선택적으로 실드하여 주면 되는 것이므로 정교하게 얼라인하지 않고도 선택적인 도핑이 가능하여 공정을 신속히 진행할 수 있다. 이와 같이 정교하지 않게 진행하는실드 마스크 공정은 포토 레지스트 공정의 절감 효과를 초래하므로 더욱 생산성의 향상과 불량률의 감소를 도모할 수 있다.Also, in the photo mask process, the mask only needs to selectively shield the n-thin film element and the CMOS of the pixel, so that selective doping is possible without finely aligning, so that the process can proceed quickly. This intricately progressing shield mask process results in a reduction in the photoresist process, thereby further improving productivity and reducing the defective rate.
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Cited By (13)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| KR100542980B1 (en) * | 2001-08-07 | 2006-01-20 | 삼성에스디아이 주식회사 | Method for formming cmos thin film transistor having a lightly doped drain structure |
| US7256060B2 (en) | 2004-11-12 | 2007-08-14 | Lg.Philips Lcd Co., Ltd. | Liquid crystal display device and method of fabricating the same |
| US7414691B2 (en) | 2004-08-12 | 2008-08-19 | Lg Display Co., Ltd. | Liquid crystal display device with prevention of defective disconnection of drain/pixel electrodes by forming two conductive layers on top of entire pixel electrode and then removing a portion of both therefrom |
| US7474362B2 (en) | 2004-12-22 | 2009-01-06 | Lg Display Co., Ltd. | Liquid crystal display device and method of fabricating the same |
| US7492432B2 (en) | 2004-12-31 | 2009-02-17 | Lg Display Co., Ltd. | Liquid crystal display device and method of fabricating the same |
| US7595859B2 (en) | 2004-12-31 | 2009-09-29 | Lg Display Co., Ltd. | Liquid crystal display device and method of fabricating the same |
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| US7632722B2 (en) | 2004-12-24 | 2009-12-15 | Lg Display Co., Ltd. | Liquid crystal display device and method of fabricating the same |
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| US7642141B2 (en) * | 2007-05-31 | 2010-01-05 | Hitachi Displays, Ltd. | Manufacturing method for display device |
| US7701524B2 (en) | 2004-08-26 | 2010-04-20 | Lg Display Co., Ltd. | LCD device comprising the drain electrode connected to an upper and a side portion of the pixel electrode and fabrication method thereof |
| US7830476B2 (en) | 2004-12-31 | 2010-11-09 | Lg Display Co., Ltd. | Electroluminescence display device comprising a drain electrode being directly contacted with the upper surface of the first transparent conductive layer and the side surface of the second conductive layer and fabricating methods thereof |
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1999
- 1999-12-09 KR KR1019990056138A patent/KR100307457B1/en not_active IP Right Cessation
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| KR100542980B1 (en) * | 2001-08-07 | 2006-01-20 | 삼성에스디아이 주식회사 | Method for formming cmos thin film transistor having a lightly doped drain structure |
| US7414691B2 (en) | 2004-08-12 | 2008-08-19 | Lg Display Co., Ltd. | Liquid crystal display device with prevention of defective disconnection of drain/pixel electrodes by forming two conductive layers on top of entire pixel electrode and then removing a portion of both therefrom |
| US7927930B2 (en) | 2004-08-13 | 2011-04-19 | Lg Display Co., Ltd. | Method for fabricating a liquid crystal display device |
| US7638801B2 (en) | 2004-08-13 | 2009-12-29 | Lg Display Co., Ltd. | Liquid crystal display device and fabrication method thereof |
| US7701524B2 (en) | 2004-08-26 | 2010-04-20 | Lg Display Co., Ltd. | LCD device comprising the drain electrode connected to an upper and a side portion of the pixel electrode and fabrication method thereof |
| US8018545B2 (en) | 2004-08-26 | 2011-09-13 | Lg Display Co., Ltd. | Method of fabricating a liquid crystal display device |
| US7612836B2 (en) | 2004-09-09 | 2009-11-03 | Lg Display Co., Ltd. | Liquid crystal display device and fabrication method thereof |
| US8049830B2 (en) | 2004-09-09 | 2011-11-01 | Lg Display Co., Ltd. | Liquid crystal display device and fabrication method thereof |
| US7619286B2 (en) | 2004-11-12 | 2009-11-17 | Lg Display Co., Ltd. | Liquid crystal display device and method of fabricating the same |
| US7256060B2 (en) | 2004-11-12 | 2007-08-14 | Lg.Philips Lcd Co., Ltd. | Liquid crystal display device and method of fabricating the same |
| US7474362B2 (en) | 2004-12-22 | 2009-01-06 | Lg Display Co., Ltd. | Liquid crystal display device and method of fabricating the same |
| US7632722B2 (en) | 2004-12-24 | 2009-12-15 | Lg Display Co., Ltd. | Liquid crystal display device and method of fabricating the same |
| US7999267B2 (en) | 2004-12-24 | 2011-08-16 | Lg Display Co., Ltd. | Liquid crystal display device |
| US7492432B2 (en) | 2004-12-31 | 2009-02-17 | Lg Display Co., Ltd. | Liquid crystal display device and method of fabricating the same |
| US7830476B2 (en) | 2004-12-31 | 2010-11-09 | Lg Display Co., Ltd. | Electroluminescence display device comprising a drain electrode being directly contacted with the upper surface of the first transparent conductive layer and the side surface of the second conductive layer and fabricating methods thereof |
| US7595859B2 (en) | 2004-12-31 | 2009-09-29 | Lg Display Co., Ltd. | Liquid crystal display device and method of fabricating the same |
| US7642141B2 (en) * | 2007-05-31 | 2010-01-05 | Hitachi Displays, Ltd. | Manufacturing method for display device |
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| KR100307457B1 (en) | 2001-10-17 |
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