KR100542980B1 - Method for formming cmos thin film transistor having a lightly doped drain structure - Google Patents

Abstract

The present invention relates to a method for manufacturing a CMOS thin film transistor having an LDD region.

In the method of manufacturing a CMOS thin film transistor having an LDD region according to the present invention, forming a polysilicon pattern on the first conductive type and the second conductive type thin film transistor regions of the substrate using a first mask, respectively, the poly Sequentially forming a gate insulating film and a conductive film on a substrate including a silicon pattern; etching the conductive film of the second conductive thin film transistor region using a second mask to etch the gate electrode of the second conductive thin film transistor Forming a source / drain region by ion implanting a high concentration of impurities into the polysilicon pattern of the second conductivity type thin film transistor region using the second mask; and forming the source / drain region using a third mask The conductive film in the region of the first conductive thin film transistor is etched to obtain a crab of the first conductive thin film transistor. Forming a gate electrode, etching the conductive layer and the gate insulating layer to expose the polysilicon pattern of the second conductive thin film transistor region using the third mask; and using the third mask Implanting low concentration impurities into the polysilicon pattern of the first conductivity type thin film transistor region to form a low concentration source / drain region, and forming an interlayer insulating film on the substrate on which the low concentration source / drain region is formed; Forming a contact hole exposing a gate insulating film on both sides of the gate electrode of the second conductivity type using a mask and exposing a polysilicon pattern on both sides of the gate electrode of the first conductivity type, using the fourth mask High concentration source / Ion implantation of high concentration impurity with polysilicon pattern of first conductivity type Forming a drain region and etching the gate insulating film exposed by the second conductive contact hole to expose the second silicon polysilicon pattern.

Therefore, the process can be simplified by reducing the number of masks, thereby reducing the defective rate and improving the yield, and the N-type thin film transistor forms an LDD structure to reduce leakage current in the off state, thereby reducing the number of masks. There is an effect that can prevent the deterioration of characteristics.

Thin Film Transistors, CMOS, LDD, Mask

Description

METHODS FOR FORMMING CMOS THIN FILM TRANSISTOR HAVING A LIGHTLY DOPED DRAIN STRUCTURE

1A to 1G are cross-sectional views illustrating a method of manufacturing a CMOS thin film transistor having a conventional LDD region.

2A to 2I are cross-sectional views illustrating a method of manufacturing a CMOS thin film transistor having an LDD structure according to an exemplary embodiment of the present invention.

<Description of Symbols for Main Parts of Drawings>

0, 40: substrate 10a, 40a: N-type thin film transistor region

0b, 40b: P-type thin film transistor region

1, 41: polysilicon pattern 12, 16, 18, 46, 48: mask

13, 42: gate insulating film 14, 45, 47: gate electrode

15, 46, 49, 54: source / drain regions 20, 50: interlayer insulating film

21 and 53: contact holes 22 and 54: source / drain electrodes

44: conductive film

The present invention relates to a CMOS thin film transistor having an LDD structure, and more particularly, to a method for manufacturing a CMOS thin film transistor having an LDD structure that can simplify the process by reducing the number of masks.

In general, an active display device includes a thin film transistor functioning as a switching element, and the thin film transistor has the most fundamental problem of preventing leakage current in an off state of the polysilicon thin film transistor.

As a means for preventing the leakage current of the thin film transistor, an LDD (Lightly Doped Drain) structure or an offset (off-set) structure is used.

In the conventional method of forming a thin film transistor having an offset structure or an LDD structure, the gate electrode material, that is, the gate metal is formed by undercutting the gate electrode so that the width of the gate electrode is smaller than the pattern width of the photosensitive film when the gate electrode of the thin film transistor is formed. Alternatively, sidewalls are formed on the sidewalls of the gate, and then source / drain regions are formed to form an offset structure or an LDD structure, and an offset structure or an LDD structure is formed using an electrical oxidation of the metal gate.

1A to 1G are cross-sectional views illustrating a manufacturing process of a CMOS thin film transistor having an LDD structure using seven conventional masks.

In the conventional method for manufacturing a CMOS thin film transistor having an LDD structure, as shown in FIG. 1A, a poly-type film is formed on a substrate 10 having an N-type thin film transistor region 10a and a P-type thin film transistor region 10b. After depositing the silicon film, a polysilicon pattern is etched by placing a first mask (not shown) on the substrate 10 to etch the polysilicon film in the N-type thin film transistor region 10a and the P-type thin film transistor region 10b, respectively. (11a, 11b) are formed.

Subsequently, as shown in FIG. 1B, a photoresist is applied to the entire surface of the substrate 10 on which the polysilicon patterns 11a and 11b are formed, and then a photolithography process is performed to form the N-type thin film transistor region 10a. A second mask 12 made of a photoresist pattern exposing the polysilicon pattern 11a is formed. Next, channel doping is performed to adjust the threshold voltage using the second mask.

Next, as shown in FIG. 1C, after removing the second mask 12, a gate insulating layer 13 is formed on the substrate 10, and a gate electrode material is deposited thereon. Subsequently, the gate electrode material is etched by placing a third mask (not shown) on the substrate 10 to form the gate insulating layers 14a and 14b of the N-type and P-type thin film transistors. 13) are formed on each. Next, a low concentration source / concentration is formed on both sides of the gate electrode 14a by ion implantation of, for example, an N-type low concentration impurity having a predetermined conductivity into the polysilicon pattern 11a of the N-type thin film transistor region 10a. The drain region 15 is formed. At this time, the low concentration of impurities implanted into the P-type thin film transistor region 10b is canceled by ion implantation of the P-type impurities for the high concentration source / drain regions of the subsequent P-type thin film transistor, thus affecting the P-type thin film transistor. Does not have

Subsequently, after the photoresist is applied to the entire surface of the substrate 10 on which the low concentration source / drain regions 15 are formed, as shown in FIG. 1D, impurities to the N-type thin film transistor region 10a are performed by performing a photolithography process. A fourth mask 16 made of a photoresist pattern for forming a source / drain region of the P-type thin film transistor is prevented while the ion implantation is prevented. Subsequently, a high concentration source / drain region 17 of the P-type thin film transistor is ion-implanted by implanting a high concentration of P-type impurity into the polysilicon pattern 11b of the P-type thin film transistor region 10b using the fourth mask 16. To form.

Subsequently, as shown in FIG. 1E, the fourth mask 16 is removed, a photoresist is then applied on the substrate 10, and then a photolithography process is performed to form the gate electrode of the N-type thin film transistor. A fifth mask 18 is formed to prevent impurity ion implantation into the P-type thin film transistor region 10a. Next, an N-type high concentration impurity is implanted into the polysilicon pattern 11a of the N-type thin film transistor region 10a using the fifth mask 18 to form a high concentration source / drain region 19. .

Next, as shown in FIG. 1F, the interlayer insulating film 20 is formed on the entire surface of the substrate 10 after the fifth mask 18 is removed. Subsequently, a sixth mask (not shown) is disposed on the substrate 10 to etch the interlayer insulating layer 20 to expose the source / drain regions 17 and 19 of the N-type thin film transistor and the P-type thin film transistor. Contact holes 21a and 21b are formed in the N-type thin film transistor region 10a and the P-type thin film transistor region 10b, respectively.

Finally, as illustrated in FIG. 1G, a conductive metal material for forming a source / drain electrode is deposited on the entire surface of the substrate 10, and then the conductive metal material is etched using a seventh mask (not shown) to form N. FIG. The source / drain electrodes 22a and 22b of the type thin film transistor and the P type thin film transistor are formed, respectively.

As a result, a CMOS thin film transistor including an N-type thin film transistor having an LDD structure and a P-type thin film transistor having a conventional structure is produced.

However, in the conventional method of manufacturing a CMOS thin film transistor having an LDD structure, a total of seven masks are used to implement the LDD structure, and thus, the number of masks required to increase related equipment.

Therefore, there is a problem that causes problems such as a decrease in productivity, an increase in potential defective factors, an increase in the price of a completed transistor, and the like.

An object of the present invention is to provide a method for manufacturing a thin film transistor having an LDD structure that can simplify the process by reducing the number of masks.

Another object of the present invention is to provide a method for manufacturing a thin film transistor having an LDD structure capable of reducing a leakage current by securing an LDD region.

In order to achieve the above object of the present invention, a method for manufacturing a thin film transistor having an LDD structure according to the present invention may include polysilicon on a first conductive type and a second conductive type thin film transistor region of a substrate using a first mask, respectively. Forming a pattern; Sequentially forming a gate insulating film and a conductive film on the substrate including the polysilicon pattern; Etching the conductive film of the second conductive thin film transistor region using a second mask to form a gate electrode of the second conductive thin film transistor;

Forming a source / drain region by implanting high concentration impurities into the polysilicon pattern of the second conductive thin film transistor region using the second mask;

Etching the conductive film of the first conductive thin film transistor region using a third mask to form a gate electrode of the first conductive thin film transistor; Etching the conductive film and the gate insulating film to expose the polysilicon pattern of the first conductive thin film transistor region using the third mask; Forming a low concentration source / drain region by implanting low concentration impurities into the polysilicon pattern of the first conductivity type thin film transistor region using the third mask; Forming an interlayer insulating film on the substrate on which the low concentration source / drain regions are formed; Forming a contact hole exposing a gate insulating film on both sides of the second conductive gate electrode using a fourth mask and exposing a polysilicon pattern on both sides of the first conductive gate electrode; By using the fourth mask

Forming a high concentration source / drain region by ion implanting high concentration impurities into the polysilicon pattern of the first conductivity type; And etching the gate insulating film exposed by the second conductive type contact hole to expose the second silicon type polysilicon pattern.

Here, after the polysilicon pattern is formed, a channel doping process for adjusting the threshold voltage may be further performed, wherein the first conductive thin film transistor is formed of an LDD structure, and the second conductive thin film transistor is It may be of a conventional structure.

The first conductive thin film transistor may be an N type thin film transistor, and the second conductive thin film transistor may be a P type thin film transistor.

The gate insulating film may be formed of an oxide film having a thickness of 800 kV to 1,200 kPa.

The high concentration impurity implanted into the polysilicon pattern of the second conductive thin film transistor region may be implanted at an intensity of 40 KeV to 80 KeV, and injected into the polysilicon pattern of the first conductive thin film transistor region. Low concentration impurities may be implanted at an intensity of 5 KeV to 20 KeV, and high concentration impurities implanted into the polysilicon pattern of the first conductive thin film transistor region may be implanted at an intensity of 5 KeV to 20 KeV.

Further, after forming contact holes in the thin film transistor region of the first conductivity type and the thin film transistor region of the second conductivity type, the second conductive type exposed by the contact hole is formed.

Etching of the gate insulating film may be performed by dry etching using an etching gas having an excellent selectivity of oxide to polysilicon, and contact holes and gates of the first conductive thin film transistor region and the second conductive thin film transistor. The gap between the electrodes may be formed to 0.5㎛ 4㎛ to secure the LDD.

After exposing the polysilicon pattern of the second conductivity type, source / drain electrodes contacting the source / drain regions of the first conductivity type thin film transistor and the second conductivity type thin film transistor, respectively, are exposed on the substrate. Preferably, the forming step is further performed.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings.

2A to 2I are cross-sectional views illustrating a method of manufacturing a thin film transistor having an LDD structure using five masks according to an embodiment of the present invention.

In the method of manufacturing a thin film transistor having an LDD structure according to the present invention, as shown in FIG. 2A, polysilicon is formed on a substrate 40 having an N type thin film transistor region 40a and a P type thin film transistor region 40b. Deposit. Subsequently, by placing a first mask (not shown) on the substrate 40, the polysilicon film is etched to form polysilicon patterns 41a and 41b in the N-type and P-type thin film transistor regions 40a and 40b, respectively. do. Next, a gate insulating film 42 made of an oxide film is formed on the substrate 40 to a thickness of 800 kPa to 1,200 kPa, preferably about 1,000 kPa.

At this time, after the polysilicon patterns 41a and 41b are formed, the channel doping for the threshold voltage control is performed using the polysilicon patterns 41a and 41b formed in the N-type thin film transistor region 40a and the P-type thin film transistor region 40b. The process can be carried out further.

Next, as illustrated in FIG. 2B, a gate electrode material is deposited on the gate insulating layer 42 to a predetermined thickness to form a conductive film 44, and a photoresist is coated on the conductive film 44. Subsequently, by performing a photolithography process on the substrate, a second photoresist pattern is formed to close the region 40a on which the N-type thin film transistor is to be formed and to close a predetermined portion of the region 40b on which the P-type thin film transistor is to be formed. The mask 46 is formed. Next, the conductive film 44 is etched using the second mask 46 to form the gate electrode 45 of the P-type thin film transistor.

Here, a portion of the second mask 46 formed in the P-type thin film transistor region 40b serves as a gate electrode mask of the P-type thin film transistor, and a portion formed in the N-type thin film transistor region 40a is a P-type thin film transistor. Serves as a mask to protect the N-type thin film transistor region 40a during the formation of the gate electrode.

Subsequently, after removing the second mask 46 as shown in FIG. 2C, the polysilicon pattern 41b of the P-type thin film transistor region 40b has a predetermined conductivity type, for example, P + type. High concentration impurities are implanted at high acceleration voltages of 40 KeV to 80 Kev to form source / drain regions 46 on both sides of the gate electrode 45.

In this case, before removing the second mask 46, a high concentration of impurities having a predetermined conductivity type are ion-implanted into the polysilicon pattern 41b of the P-type thin film transistor region 40b, and then the second mask ( 46) may be removed.

Subsequently, as shown in FIG. 2D, the photoresist is applied to the entire surface of the substrate 40 on which the source / drain regions 46 are formed, and then the P-type thin film transistor region 40b is closed by performing a photolithography process. And a third mask 48 made of a photoresist pattern closing a predetermined portion of the N-type thin film transistor region 40a. Next, the gate electrode 47 of the N-type thin film transistor is formed by etching the conductive layer 44 and the gate insulating layer 42 of the N-type thin film transistor region 40a using the third mask 48.

Here, a portion of the third mask 48 formed in the N-type thin film transistor region 40a serves as a gate electrode mask of the N-type thin film transistor, and a portion formed in the P-type thin film transistor region 40a is an N-type thin film transistor. Serves as a mask to protect the P-type thin film transistor region 40a during the formation of the gate electrode.

Subsequently, as shown in FIG. 2E, the third mask 48 is removed, and then, for example, an N-type low concentration impurity having a predetermined conductivity is formed in the polysilicon pattern of the N-type thin film transistor region 40a. 5Kev to 20Kev Ion implantation at a low speed voltage of preferably 10KeV forms a low concentration source / drain region 49 on both sides of the gate electrode.

Next, as shown in FIG. 2F, an interlayer insulating film 50 made of an insulating film such as an oxide film or a nitride film is formed on the substrate 40 on which the low concentration source / drain regions 49 are formed.

Subsequently, after the photoresist is applied to the entire surface of the substrate 40 on which the interlayer insulating film 50 is formed, as shown in FIG. 2G, the source / drain regions 46 and the N-type thin film transistors of the P-type thin film transistor region 40b are then applied. A fourth mask 52 made of a photoresist pattern for forming a contact hole for opening the low concentration source / drain regions 49 of the region 40a is formed. Next, an etching process is performed using the fourth mask 52 to expose the contact hole 53a and the P-type thin film transistor exposing the polysilicon low concentration source / drain region 49 of the N-type thin film transistor region 40a. Contact holes 53b are formed to expose the gate insulating film 42 over the source / drain regions 46 of the region 40b. Next, the low concentration source / drain region 49 of the N-type thin film transistor region 40a in which the contact hole 53 is formed has a predetermined conductivity, for example, an N + type high concentration impurity of 5Kev to 20Kev is preferable. Preferably, the source / drain regions of the LDD structure are formed by ion implantation at a low-speed voltage of 10 KeV to form the high concentration source / drain regions 54 on both sides of the gate electrode 47.

At this time, the distance between the contact holes 53a and 53b formed in the N-type thin film transistor region 40a and the P-type thin film transistor region 40b and the gate electrode is 0.5 μm to 4 μm, preferably 2 μm, to secure the LDD region. To form.

In the ion implantation of high concentration impurities of N + type into the low concentration source / drain region 49 of the N type thin film transistor region 40a through the contact hole 53a, the high concentration impurities are ion implanted at a low speed voltage. Injection of impurities into the source / drain regions 46 of the P-type thin film transistor region 40b through the contact hole 53b is prevented.

Next, as shown in FIG. 2H, the fourth mask 52 is removed, followed by a dry etching process using an etching gas having an excellent etching selectivity for the oxide film with respect to polysilicon, thereby performing a P-type thin film transistor region 40b. The gate insulating film 42 made of the oxide film exposed by the contact hole 53b of the () is etched to expose the source / drain region 46.

Finally, as illustrated in FIG. 2I, a conductive metal material is deposited to form a source / drain electrode on the entire surface of the substrate 40, and then the conductive metal material is etched using a fifth mask (not shown). Source / drain electrodes 54a and 54b of the N-type thin film transistor and the P-type thin film transistor are formed, respectively.

As a result, a CMOS thin film transistor including an N-type thin film transistor having an LDD structure and a P-type thin film transistor having a conventional structure is produced.

As described above, according to the method of manufacturing the CMOS thin film transistor of the present invention, the first mask for forming the polysilicon pattern, the second mask for forming the gate electrode of the P-type thin film transistor, the gate electrode of the N-type thin film transistor Five masks are used, which are composed of a third mask for forming a semiconductor, a fourth mask for forming a contact hole, and a fifth mask for forming a source / drain electrode.

Therefore, the process can be simplified by reducing the number of masks of two sheets, compared to the conventional method of manufacturing a CMOS thin film transistor using seven masks. Thus, the defective rate is reduced and the yield is improved.

In addition, conventional thin film transistors are formed in P-type thin film transistors, whereas N-type thin film transistors have an LDD structure, thereby reducing leakage current in an off state, thereby preventing deterioration of device characteristics.

Although described above with reference to a preferred embodiment of the present invention, those skilled in the art will be variously modified and changed within the scope of the invention without departing from the spirit and scope of the invention described in the claims below I can understand that you can.

Claims (12)

Forming a polysilicon pattern on each of the first conductivity type and second conductivity type thin film transistor regions of the substrate using the first mask; Sequentially forming a gate insulating film and a conductive film on the substrate including the polysilicon pattern; Etching the conductive film of the second conductive thin film transistor region using a second mask to form a gate electrode of the second conductive thin film transistor; Forming a source / drain region by implanting high concentration impurities into the polysilicon pattern of the second conductive thin film transistor region using the second mask; Etching the conductive film of the first conductive thin film transistor region using a third mask to form a gate electrode of the first conductive thin film transistor; Etching the conductive film and the gate insulating film to expose the polysilicon pattern of the first conductive thin film transistor region using the third mask; Forming a low concentration source / drain region by implanting low concentration impurities into the polysilicon pattern of the first conductivity type thin film transistor region using the third mask; Forming an interlayer insulating film on the substrate on which the low concentration source / drain regions are formed; Forming a contact hole exposing a gate insulating film on both sides of the second conductive gate electrode using a fourth mask and exposing a polysilicon pattern on both sides of the first conductive gate electrode; Forming a high concentration source / drain region by ion implanting high concentration impurities into the first conductive polysilicon pattern using the fourth mask; And Etching the gate insulating layer exposed by the second conductivity type contact hole to expose the polysilicon pattern of the second conductivity type; A method of manufacturing a CMOS thin film transistor having an LDD structure, comprising: a. The method of claim 1, wherein after the polysilicon pattern is formed, a channel doping process for adjusting the threshold voltage is further performed. The method of manufacturing a CMOS thin film transistor having an LDD structure according to claim 1, wherein the first conductive thin film transistor has an LDD structure, and the second conductive thin film transistor has a conventional structure. 4. The CMOS thin film transistor having a LDD structure according to claim 3, wherein the first conductive thin film transistor is an N type thin film transistor and the second conductive thin film transistor is a P type thin film transistor. Way. 2. The method of claim 1, wherein the gate insulating film is formed to a thickness of 800 kW to 1,200 kW. The method of manufacturing the second high concentration impurity region of the thin film transistors of the conductivity type that is implanted into the polysilicon patterns CMOS thin film having a LDD structure, it characterized in that the injection to the intensity of 30KeV ~ 80KeV transistor according to claim 1. The method of claim 1, wherein the low concentration impurity implanted into the polysilicon pattern of the first conductive thin film transistor region is implanted at an intensity of 5KeV to 20KeV. The method of claim 1, wherein the highly doped impurities injected into the polysilicon pattern of the first conductive thin film transistor region are injected at an intensity of 5 KeV to 20 KeV. The method of manufacturing a CMOS thin film transistor having an LDD structure according to claim 1, wherein an oxide film is formed from said gate insulating film. 10. The method of claim 9, wherein after forming contact holes in the first conductivity type thin film transistor region and the second conductivity type thin film transistor region, the etching of the second conductive gate insulating film exposed by the contact hole is performed. A method of manufacturing a CMOS thin film transistor having an LDD structure, which is performed by dry etching using an etching gas having an excellent selectivity of oxide to silicon. The LDD structure of claim 1, wherein a distance between the contact hole and the gate electrode of the first conductive thin film transistor region and the second conductive thin film transistor is formed to be 0.5 μm to 4 μm. Method of manufacturing a CMOS thin film transistor. The semiconductor device of claim 1, wherein after exposing the polysilicon pattern of the second conductivity type, a source contacting the source / drain regions of the first conductivity type thin film transistor and the second conductivity type thin film transistor, respectively, on the substrate. A method for manufacturing a CMOS thin film transistor having an LDD structure, further comprising the step of forming a / drain electrode.

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