KR100223935B1 - Method of manufacturing semiconductor device - Google Patents

Method of manufacturing semiconductor device Download PDF

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KR100223935B1
KR100223935B1 KR1019970021326A KR19970021326A KR100223935B1 KR 100223935 B1 KR100223935 B1 KR 100223935B1 KR 1019970021326 A KR1019970021326 A KR 1019970021326A KR 19970021326 A KR19970021326 A KR 19970021326A KR 100223935 B1 KR100223935 B1 KR 100223935B1
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gate
region
forming
nmos
insulating film
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KR19980085268A (en
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강창용
박흥배
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구본준
엘지반도체주식회사
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823842—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different gate conductor materials or different gate conductor implants, e.g. dual gate structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/823835—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes silicided or salicided gate conductors

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  • Condensed Matter Physics & Semiconductors (AREA)
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Abstract

본 발명은 소자의 신뢰성을 향상시키고 서로 동일한 크기의 듀얼게이트를 형성하는데 적당한 반도체소자 제조방법에 관한 것으로서 필드산화막이 형성된 반도체기판상에 게이트절연막을 형성하고, 게이트절연막상에 불순물이 도핑되지 않은 폴리실리콘층을 형성하는 공정과, 상기 폴리실리콘층상에 제 1 절연막을 형성한 후 NMOS게이트가 형성될 제 1 영역과 PMOS게이트가 형성될 제 2 영역으로 정의한 다음, 각각의 영역에 해당하는 폴리실리콘층에 서로다른 불순물 이온주입을 실시하는 공정과, 상기 제 2 영역의 제 1 절연막을 제거하여 노출된 폴리실리콘층상에 PMOS게이트 형성용 패턴을 형성하고, 제 1 영역의 제 1 절연막상에 NMOS게이트 형성용 패턴을 형성하는 공정과, 상기 NMOS 및 PMOS게이트 형성용 패턴을 마스크로 상기 게이트절연막이 노출되도록 식각하여 NMOS게이트 및 PMOS게이트를 형성하는 공정과, 상기 NMOS게이트 및 PMOS게이트의 양측에 LDD영역을 갖는 소오스/드레인 불순물영역을 형성하는 공정과, 상기 NMOS게이트 및 PMOS게이트의 표면과, 소오스/드레인 불순물영역의 반도체기판상에 실리사이드를 형성하는 공정을 포함하여 이루어진다.BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a method of manufacturing a semiconductor device suitable for improving the reliability of devices and forming dual gates having the same size. A process of forming a silicon layer, a first insulating layer formed on the polysilicon layer, and a first region in which an NMOS gate is to be formed and a second region in which a PMOS gate is to be formed, and then a polysilicon layer corresponding to each region. Implanting different impurity ions into each other; forming a PMOS gate formation pattern on the exposed polysilicon layer by removing the first insulating film in the second region; and forming an NMOS gate on the first insulating film in the first region. Forming a gate pattern and exposing the gate insulating layer using the NMOS and PMOS gate formation patterns as a mask. Etching to form an NMOS gate and a PMOS gate, forming a source / drain impurity region having an LDD region at both sides of the NMOS gate and the PMOS gate, a surface of the NMOS gate and the PMOS gate, and a source / drain And forming silicide on the semiconductor substrate in the impurity region.

Description

반도체소자 제조방법Semiconductor device manufacturing method

본 발명은 반도체소자에 관한 것으로서 특히 N형 불순물이 도핑된 폴리실리콘과 p형 불순물이 도핑된 폴리실리콘의 식각비를 고려하여 신뢰성있는 듀얼(Dual)게이트를 형성하는데 적당한 반도체소자 제조방법에 관한 것이다.The present invention relates to a semiconductor device, and more particularly, to a method for manufacturing a semiconductor device suitable for forming a reliable dual gate in consideration of the etching ratio of polysilicon doped with N-type impurities and polysilicon doped with p-type impurities. .

이하, 종래기술에 따른 반도체소자의 제조방법을 첨부된 도면을 참조하여 설명하면 다음과 같다.Hereinafter, a method of manufacturing a semiconductor device according to the prior art will be described with reference to the accompanying drawings.

도 1a 내지 1i는 종래 반도체소자의 제조방법을 설명하기 위한 공정단면도이다.1A to 1I are cross-sectional views illustrating a method of manufacturing a conventional semiconductor device.

도 1a에 도시한 바와같이 반도체기판(11)의 필드영역에 필드산화막(12)을 형성하고 반도체기판(11)상에 게이트절연막(13)을 형성한다.As shown in FIG. 1A, the field oxide film 12 is formed in the field region of the semiconductor substrate 11, and the gate insulating film 13 is formed on the semiconductor substrate 11.

게이트절연막(13)상에 불순물이 도핑되지 않은 폴리실리콘층(14)을 형성한다.The polysilicon layer 14 which is not doped with impurities is formed on the gate insulating film 13.

도 1b에 도시한 바와같이 폴리실리콘층(14)상에 제 1 포토레지스트(15)를 도포한 후 노광 및 현상공정을 이용하여 NMOS게이트가 형성될 영역의 폴리실리콘층(14)을 노출시킨다.As shown in FIG. 1B, after the first photoresist 15 is applied onto the polysilicon layer 14, the polysilicon layer 14 in the region where the NMOS gate is to be formed is exposed using an exposure and development process.

상기 제 1 포토레지스트(15)를 마스크로 이용하여 노출된 폴리실리콘층(14)에 N도전형의 불순물 이온주입을 실시한다.N-conductive impurity ions are implanted into the exposed polysilicon layer 14 using the first photoresist 15 as a mask.

이어, 도 1c에 도시한 바와같이 제 1 포토레지스트(15)를 제거한 후 전면에 제 2 포토레지스트(15a)를 도포한다.Subsequently, as shown in FIG. 1C, the first photoresist 15 is removed and then the second photoresist 15 a is applied to the entire surface.

도포된 제 2 포토레지스트(15a)를 노광 및 현상공정으로 패터닝하여 이번에는 PMOS게이트가 형성될 영역의 폴리실리콘층(14)을 노출시킨다.The applied second photoresist 15a is patterned by an exposure and development process to expose the polysilicon layer 14 in the region where the PMOS gate is to be formed.

그리고 노출된 폴리실리콘층(14)에 P도전형의 불순물 이온주입을 실시한다.P-conductive impurity ions are implanted into the exposed polysilicon layer 14.

이어서, 도 1d에 도시한 바와같이 제 2 포토레지스트(15a)를 제거한 후 전면에 제 3 포토레지스트(도면에 도시하지 않음)를 도포한다.Subsequently, as shown in Fig. 1D, after removing the second photoresist 15a, a third photoresist (not shown) is applied to the entire surface.

노광 및 현상공정을 이용하여 제 3 포토레지스트를 패터닝하고 패터닝된 제 3 포토레지스트를 마스크로 이용한 식각공정으로 폴리실리콘층(14) 및 게이트절연막(13)을 선택적으로 제거하여 NMOS게이트(14a)와 PMOS게이트(14b)를 형성한다.The polysilicon layer 14 and the gate insulating layer 13 are selectively removed by patterning the third photoresist using an exposure and development process and using the patterned third photoresist as a mask to remove the NMOS gate 14a and the NMOS gate 14a. The PMOS gate 14b is formed.

그리고 도 1e에 도시한 바와같이 NMOS게이트(14a)와 PMOS게이트(14b)를 포함한 반도체기판(11)전면에 제 4 포토레지스트(15b)를 도포한다.As shown in FIG. 1E, a fourth photoresist 15b is coated on the entire surface of the semiconductor substrate 11 including the NMOS gate 14a and the PMOS gate 14b.

노광 및 현상공정으로 제 4 포토레지스트(15b)를 패터닝하여 PMOS게이트(14b)가 형성된 영역을 마스킹한 후 노출된 NMOS게이트(14a)양측의 반도체기판(11)표면내에 P도전형의 저농도 불순물 이온주입을 실시한다.After patterning the fourth photoresist 15b by the exposure and development process to mask the region where the PMOS gate 14b is formed, P-conductive low concentration impurity ions in the surface of the semiconductor substrate 11 on both sides of the exposed NMOS gate 14a. Carry out the injection.

이어, 도 1f에 도시한 바와같이 제 4 포토레지스트(15b)를 제거한 후 전면에 제 5 포토레지스트(15c)를 도포한 후 패터닝하여 NMOS게이트(14a)가 형성된 영역을 마스킹한 후 노출된 PMOS게이트(14b)양측의 반도체기판(11)표면내에 N도전형의 저농도 불순물 이온주입을 실시한다.Subsequently, as shown in FIG. 1F, after the fourth photoresist 15b is removed, the fifth photoresist 15c is applied to the entire surface, and then patterned to mask the region where the NMOS gate 14a is formed, and then the exposed PMOS gate. (14b) N-conductive low concentration impurity ions are implanted into the surfaces of the semiconductor substrates 11 on both sides.

다음, 도 1g에 도시한 바와같이 제 5 포토레지스트(15c)를 제거한 후 NMOS게이트(14a)와 PMOS게이트(14b)를 포함한 전면에 절연막을 증착한 후 에치백하여 NMOS게이트(14a)와 PMOS게이트(14b)양측면에 사이드 월(Sidewall)(16,16a)을 형성한다.Next, as shown in FIG. 1G, after the fifth photoresist 15c is removed, an insulating film is deposited on the entire surface including the NMOS gate 14a and the PMOS gate 14b, and then etched back to form the NMOS gate 14a and the PMOS gate. (14b) Sidewalls 16 and 16a are formed on both sides.

이어, 반도체기판(11)전면에 제 6 포토레지스트(15d)를 도포한 후 노광 및 현상공정으로 패터닝하여 NMOS게이트(14a)가 형성된 영역을 노출시킨 후 P도전형의 고농도 불순물 이온주입을 실시한다.Subsequently, the sixth photoresist 15d is applied to the entire surface of the semiconductor substrate 11, and then patterned by an exposure and development process to expose a region where the NMOS gate 14a is formed, and then a highly conductive impurity ion implantation of P conductivity is performed. .

그리고 도 1h에 도시한 바와같이 제 6 포토레지스트(15d)를 제거한 후 전면에 제 7 포토레지스트(15e)를 도포한 후 이번에는 PMOS게이트(14b)가 형성된 영역을 노출시킨 다음, N도전형의 고농도 불순물 이온주입을 실시한다.As shown in FIG. 1H, after removing the sixth photoresist 15d, the seventh photoresist 15e is applied to the entire surface, and this time, the region in which the PMOS gate 14b is formed is exposed, and then the N conductive type is exposed. High concentration impurity ion implantation is performed.

이어서, 도 1i에 도시한 바와같이 전면에 실리사이드화가 가능한 물질을 증착한 후 열처리하면 상기 물질과 실리콘과의 계면에 실리사이드(Silicide)(17)가 형성된다.Subsequently, as illustrated in FIG. 1I, a silicide 17 is formed at an interface between the material and the silicon by depositing a silicideable material on the entire surface and then performing heat treatment.

그리고 NMOS게이트(14a)와 PMOS게이트(14b)양측면에 반도체기판(11)내에 LDD영역을 갖는 소오스/드레인 불순물영역(18,19)이 형성된다.Source / drain impurity regions 18 and 19 having LDD regions are formed in the semiconductor substrate 11 on both sides of the NMOS gate 14a and the PMOS gate 14b.

이때 실리사이드(17)가 형성되는 부위는 NMOS게이트(14a) 및 PMOS게이트(14b)의 표면과 상기 소오스/드레인 불순물영역(18,19)상의 반도체기판(11)표면이다.The silicide 17 is formed at the surface of the NMOS gate 14a and the PMOS gate 14b and the surface of the semiconductor substrate 11 on the source / drain impurity regions 18 and 19.

이와같이 불순물이 도핑되지 않은 폴리실리콘상에 각각 선택적으로 N도전형 및 P도전형의 불순물을 주입한 후 식각공정을 통해 듀얼(dual)게이트를 형성하게 된다.In this way, impurities of N conductivity type and P conductivity type are selectively injected onto polysilicon that is not doped with impurities, and then a dual gate is formed through an etching process.

그러나 상기와 같은 종래 반도체소자 제조방법은 다음과 같은 문제점이 있었다.However, the conventional semiconductor device manufacturing method as described above has the following problems.

N도전형의 불순물이 주입된 폴리실리콘과 P도전형의 불순물이 주입된 폴리실리콘과의 식각비가 서로 달라 최종적인 게이트의 크기가 서로 다르게 된다.The final gate size is different because the etch ratio between polysilicon implanted with N-conductive impurities and polysilicon implanted with P-conductive impurities is different.

이는 N도전형의 폴리실리콘이 P도전형의 폴리실리콘에 비해 식각이 더 빨리 되기 때문이다.This is because the N-conducting polysilicon is etched faster than the P-conducting polysilicon.

본 발명은 상기한 문제점을 해결하기 위해 안출한 것으로서, P도전형의 폴리실리콘과의 식각속도를 고려하여 N도전형의 폴리실리콘층상에 절연막을 형성하므로서 듀얼 게이트의 크기를 서로 동일하게 형성하고 아울러 소자의 신뢰성을 향상시키는데 적당한 반도체소자의 제조방법을 제공하는데 그 목적이 있다.The present invention has been made to solve the above problems, in consideration of the etching rate with the polysilicon of P conductivity type to form an insulating film on the polysilicon layer of the N conductivity type to form the same size of the dual gate and It is an object of the present invention to provide a method for manufacturing a semiconductor device suitable for improving the reliability of the device.

도 1a 내지 1i는 종래 반도체소자 제조방법을 설명하기 위한 공정단면도1A to 1I are cross-sectional views illustrating a method of manufacturing a conventional semiconductor device.

도 2a 내지 2l은 본 발명의 반도체소자 제조방법을 설명하기 위한 공정단면도2A through 2L are cross-sectional views illustrating a method of manufacturing a semiconductor device of the present invention.

*도면의 주요부분에 대한 부호의 설명** Description of the symbols for the main parts of the drawings *

11,21 : 반도체기판12,22 : 필드산화막11,21: semiconductor substrate 12,22: field oxide film

13,23 : 필드산화막14,24 : 폴리실리콘층13,23: field oxide film 14,24: polysilicon layer

24a : NMOS게이트24b : PMOS게이트24a: NMOS gate 24b: PMOS gate

25 : 제 1 절연막26a' : NMOS 및 PMOS게이트형성용 패턴25: first insulating film 26a ': pattern for forming NMOS and PMOS gates

28,28a : 사이드월29 : 실리사이드28,28a: Sidewall 29: Silicide

30,31 : 소오스/드레인 불순물영역30,31: source / drain impurity region

상기의 목적을 달성하기 위한 본 발명에 따른 반도체소자의 제조방법은 필드산화막이 형성된 반도체기판상에 게이트절연막을 형성하고, 게이트절연막상에 불순물이 도핑되지 않은 폴리실리콘층을 형성하는 공정과, 상기 폴리실리콘층상에 제 1 절연막을 형성한 후 NMOS게이트가 형성될 제 1 영역과 PMOS게이트가 형성될 제 2 영역으로 정의한 다음, 각각의 영역에 해당하는 폴리실리콘층에 서로다른 불순물 이온주입을 실시하는 공정과, 상기 제 2 영역의 제 1 절연막을 제거하여 노출된 폴리실리콘층상에 PMOS게이트 형성용 패턴을 형성하고, 제 1 영역의 제 1 절연막상에 NMOS게이트 형성용 패턴을 형성하는 공정과, 상기 NMOS 및 PMOS게이트 형성용 패턴을 마스크로 상기 게이트절연막이 노출되도록 식각하여 NMOS게이트 및 PMOS게이트를 형성하는 공정과, 상기 NMOS게이트 및 PMOS게이트의 양측에 LDD영역을 갖는 소오스/드레인 불순물영역을 형성하는 공정과, 상기 NMOS게이트 및 PMOS게이트의 표면과, 소오스/드레인 불순물영역의 반도체기판상에 실리사이드를 형성하는 공정을 포함하여 이루어진다.A method of manufacturing a semiconductor device according to the present invention for achieving the above object comprises the steps of forming a gate insulating film on a semiconductor substrate on which a field oxide film is formed, and forming a polysilicon layer doped with impurities on the gate insulating film; After the first insulating film is formed on the polysilicon layer, it is defined as the first region where the NMOS gate is to be formed and the second region where the PMOS gate is to be formed, and then different impurity ions are implanted into the polysilicon layers corresponding to the respective regions. Forming a pattern for forming a PMOS gate on the exposed polysilicon layer by removing the first insulating film in the second region, and forming a pattern for forming an NMOS gate on the first insulating film in the first region; Forming an NMOS gate and a PMOS gate by etching the gate insulating layer using the NMOS and PMOS gate formation patterns as a mask to expose the gate insulating layer; Forming a source / drain impurity region having an LDD region at both sides of the OS gate and the PMOS gate, and forming a silicide on the surface of the NMOS gate and the PMOS gate and a semiconductor substrate of the source / drain impurity region; It is done by

이하, 본 발명에 따른 반도체소자의 제조방법을 첨부된 도면을 참조하여 설명하기로 한다.Hereinafter, a method of manufacturing a semiconductor device according to the present invention will be described with reference to the accompanying drawings.

도 2a 내지 2l은 본 발명에 따른 반도체소자의 제조방법을 설명하기 위한 공정단면도이다.2A through 2L are cross-sectional views illustrating a method of manufacturing a semiconductor device in accordance with the present invention.

도 2a에 도시한 바와같이 반도체기판(21)의 필드영역에 필드산화막(22)을 형성한 후 반도체기판(21)상에 게이트절연막(23)을 형성한다.As shown in FIG. 2A, the field oxide film 22 is formed in the field region of the semiconductor substrate 21, and then the gate insulating film 23 is formed on the semiconductor substrate 21.

게이트절연막(23)상에 불순물이 도핑되지 않은 폴리실리콘층(24)을 형성하고 폴리실리콘층(24)상에 제 1 절연막(25)으로서 실리콘질화막을 증착한다.A polysilicon layer 24 which is not doped with impurities is formed on the gate insulating film 23, and a silicon nitride film is deposited as the first insulating film 25 on the polysilicon layer 24.

도 2b에 도시한 바와같이 제 1 절연막(25)상에 제 1 포토레지스트(26)를 도포한 후 제 1 영역(Ⅰ)과 제 2 영역(Ⅱ)을 정의한 다음 노광 및 현상공정을 이용하여 제 1 영역의 제 1 포토레지스트(26)를 제거한다.As shown in FIG. 2B, after the first photoresist 26 is coated on the first insulating layer 25, the first region I and the second region II are defined, and then the exposure and development processes are performed. The first photoresist 26 in one region is removed.

이때 제 1 영역(Ⅰ)은 NMOS게이트가 형성될 영역이고 제 2 영역(Ⅱ)은 PMOS게이트가 형성될 영역이다.In this case, the first region I is a region where the NMOS gate is to be formed and the second region II is a region where the PMOS gate is to be formed.

물론 제 1 영역(Ⅰ)에 PMOS게이트를 형성하고 제 2 영역(Ⅱ)에 NMOS게이트를 형성하는 것도 무관하다.Of course, forming the PMOS gate in the first region (I) and the NMOS gate in the second region (II) is irrelevant.

제 1 포토레지스트(26)가 제거된 제 1 영역(Ⅰ)의 제 1 절연막(25)를 통해 폴리실리콘층(24)에 N도전형의 불순물 이온주입을 실시한다.N-conductive impurity ions are implanted into the polysilicon layer 24 through the first insulating film 25 in the first region I from which the first photoresist 26 is removed.

이어, 제 1 포토레지스트(26)를 제거한 후 반도체기판(21)전면에 제 2 포토레지스트(26a)를 도포한다. 노광 및 현상공정을 통해 도 2c에 도시한 바와같이 제 2 영역(Ⅱ)의 포토레지스트(26a)만을 제거한다.Subsequently, after the first photoresist 26 is removed, the second photoresist 26a is applied to the entire surface of the semiconductor substrate 21. Only the photoresist 26a of the second region II is removed as shown in Fig. 2C through the exposure and development processes.

그리고 도 2b에서와 마찬가지로, 노출된 제 1 절연막(25)을 통해 P도전형의 불순물 이온주입을 실시한다.As in FIG. 2B, P-conductive impurity ions are implanted through the exposed first insulating film 25.

이어서, 도 2d에 도시한 바와같이 패터닝된 제 2 포토레지스트(26a)를 마스크로 이용한 식각공정으로 제 2 영역(Ⅱ)의 제 1 절연막(25)을 제거한다.Subsequently, as illustrated in FIG. 2D, the first insulating layer 25 of the second region II is removed by an etching process using the patterned second photoresist 26a as a mask.

따라서 제 1 영역(Ⅰ)의 반도체기판(21)상에는 게이트절연막(22), 폴리실리콘층(24) 및 제 1 절연막(25)이 구성되고 제 2 영역(Ⅱ)의 반도체기판(21)상에는 게이트절연막(22)과 폴리실리콘층(24)이 구성된다.Therefore, the gate insulating film 22, the polysilicon layer 24, and the first insulating film 25 are formed on the semiconductor substrate 21 in the first region (I), and the gate is formed on the semiconductor substrate 21 in the second region (II). The insulating film 22 and the polysilicon layer 24 are comprised.

다음, 제 2 포토레지스트(26a)를 제거한 후 잔존하는 제 1 절연막(25)을 포함한 폴리실리콘층(24)상에 제 3 포토레지스트(26b)를 도포한다.Next, after removing the second photoresist 26a, the third photoresist 26b is applied onto the polysilicon layer 24 including the remaining first insulating film 25.

도 2e에 도시한 바와같이 노광 및 현상공정으로 제 3 포토레지스트(26b)를 패터닝하여 제 1 영역(Ⅰ)의 제 1 절연막(25)과 제 2 영역(Ⅱ)의 폴리실리콘층(24)상에 NMOS 및 PMOS게이트 형성을 위한 패턴(26b')를 형성한다.As shown in FIG. 2E, the third photoresist 26b is patterned by an exposure and development process to form the first insulating film 25 of the first region (I) and the polysilicon layer 24 of the second region (II). A pattern 26b 'for forming NMOS and PMOS gates is formed on the substrate.

이어, 도 2f에 도시한 바와같이 제 1 영역(Ⅰ)의 NMOS게이트패턴(26b')를 마스크로 이용한 식각공정으로 잔존하는 제 1 절연막(25)을 제거한다.Next, as shown in FIG. 2F, the remaining first insulating layer 25 is removed by an etching process using the NMOS gate pattern 26b ′ of the first region I as a mask.

이때 제 1 절연막(25)이 제거됨과 동시에 제 2 영역(Ⅱ)의 폴리실리콘층(24)이 소정깊이로 제거된다.At this time, the first insulating layer 25 is removed and the polysilicon layer 24 of the second region II is removed to a predetermined depth.

따라서 제 2 영역(Ⅱ)의 폴리실리콘층(24)이 제거되는 깊이는 제 1 절연막(25)의 두께를 어느정도 하느냐에 달려있다.Therefore, the depth at which the polysilicon layer 24 in the second region II is removed depends on the thickness of the first insulating film 25.

이어서, 도 2g에 도시한 바와같이 NMOS 및 PMOS게이트패턴(26b')를 마스크로 이용한 식각공정으로 제 1 영역(Ⅰ) 및 제 2 영역(Ⅱ)의 폴리실리콘층(24)을 제거하여 NMOS게이트(24a)와 PMOS게이트(24b)를 형성한다.Subsequently, as shown in FIG. 2G, the polysilicon layer 24 of the first region I and the second region II is removed by an etching process using the NMOS and PMOS gate patterns 26b ′ as masks. 24a and the PMOS gate 24b are formed.

그리고 도 2h에 도시한 바와같이 NMOS게이트(24a)와 PMOS게이트(24b)를 마스크로 이용한 식각공정으로 반도체기판(21)상의 게이트절연막(22)을 선택적으로 제거하고 상기 NMOS 및 PMOS게이트패턴(26b')을 제거한다.As shown in FIG. 2H, the gate insulating layer 22 on the semiconductor substrate 21 is selectively removed by an etching process using the NMOS gate 24a and the PMOS gate 24b as a mask, and the NMOS and PMOS gate patterns 26b are removed. Remove the ').

이어, 도 2i에 도시한 바와같이 NMOS게이트(24a)와 PMOS게이트(24b)를 포함한 전면에 제 4 포토레지스트(26c)를 도포한 후 제 1 영역(Ⅰ)을 노출시키고 NMOS게이트(24a)양측의 반도체기판(21)표면내에 P도전형의 저농도 불순물 이온주입을 실시한다.Subsequently, as shown in FIG. 2I, after the fourth photoresist 26c is coated on the entire surface including the NMOS gate 24a and the PMOS gate 24b, the first region I is exposed and both sides of the NMOS gate 24a are exposed. P-conductive low concentration impurity ions are implanted into the surface of the semiconductor substrate 21.

이어, 도 2j에 도시한 바와같이 제 5 포토레지스트(26d)를 도포한 후 패터닝하여 제 2 영역(Ⅱ)만을 노출시킨 후 PMOS게이트(24b)양측의 반도체기판(21)표면내에 N도전형의 저농도 불순물 이온주입을 실시한다.Subsequently, as shown in FIG. 2J, the fifth photoresist 26d is applied and patterned to expose only the second region II, and then the N-conductive type is formed in the surface of the semiconductor substrate 21 on both sides of the PMOS gate 24b. Low concentration impurity ion implantation is performed.

다음, 도 2k에 도시한 바와같이 NMOS게이트(24a)상측의 제 1 절연막(25)을 제거한 후 반도체기판(21)전면에 제 2 절연막을 증착한 다음, 에치백하여 NMOS게이트(24a) 및 PMOS게이트(24b)의 양측면에 사이드월(sidewall)(28,28a)을 형성한다.Next, as shown in FIG. 2K, after removing the first insulating film 25 on the NMOS gate 24a, the second insulating film is deposited on the entire surface of the semiconductor substrate 21, and then etched back to form the NMOS gate 24a and the PMOS. Sidewalls 28 and 28a are formed on both sides of the gate 24b.

그리고 제 6 포토레지스트(도면에 도시하지 않음)를 도포한 후 노광 및 현상공정으로 패터닝하여 제 1 영역(Ⅰ)을 노출시킨다.Then, the sixth photoresist (not shown) is applied, and then patterned by exposure and development to expose the first region (I).

노출된 제 1 영역(Ⅰ)에 P도전형의 고농도 불순물 이온주입을 실시한다.P-conductive high concentration impurity ion implantation is performed in the exposed first region (I).

또한 제 7 포토레지스트(도면에 도시하지 않음)를 도포한 후 노광 및 현상공정으로 패터닝하여 제 2 영역(Ⅱ)을 노출시키고 노출된 제 2 영역(Ⅱ)에 N도전형의 고농도 불순물 이온주입을 실시한다.In addition, after applying the seventh photoresist (not shown), patterning is performed by an exposure and development process to expose the second region (II), and an N-conductive high concentration impurity ion implantation is performed on the exposed second region (II). Conduct.

이어, 도 2l에 도시한 바와같이 반도체기판(21)전면에 실리사이드화가 가능한 물질, 예를들어 티타늄(Ti), 티타늄나이트라이드(TiN), 티타늄텅스텐(TiW)등과 같은 물질을 증착한 후 열처리하면 실리콘과의 계면에 실리사이드(29)가 형성된다.Subsequently, as illustrated in FIG. 2L, when a material, such as titanium (Ti), titanium nitride (TiN), titanium tungsten (TiW), or the like, may be deposited on the entire surface of the semiconductor substrate 21, and then heat-treated. Silicide 29 is formed at the interface with silicon.

이때 상기 열처리공정시 NMOS게이트(24a)와 PMOS게이트(24b)양측의 반도체기판(21)내에 이온주입된 불순물이 활성화되어 LDD영역을 갖는 소오스/드레인 불순물영역(30,31)이 형성된다.At this time, impurities implanted into the semiconductor substrate 21 on both sides of the NMOS gate 24a and the PMOS gate 24b are activated in the heat treatment process, so that source / drain impurity regions 30 and 31 having LDD regions are formed.

한편, 실리사이드(29)는 NMOS게이트(24a)의 표면과 PMOS게이트(24b)표면, 그리고 소오스/드레인 불순물영역(30,31)상의 반도체기판(21)의 표면에 형성된다.On the other hand, the silicide 29 is formed on the surface of the NMOS gate 24a, the surface of the PMOS gate 24b, and the surface of the semiconductor substrate 21 on the source / drain impurity regions 30 and 31.

이상 상술한 바와같이 본 발명의 반도체소자 제조방법은 다음과 같은 효과가 있다.As described above, the semiconductor device manufacturing method of the present invention has the following effects.

불순물이 도핑되지 않은 폴리실리콘층을 형성하고 그 위에 질화막을 형성한 후 마스킹공정을 통해 N도전형 및 P도전형의 불순물 이온주입을 실시하므로 질화막에 의해 불순물의 채널링(channeling)이 방지되어 소자의 신뢰성을 향상시킨다.After forming a polysilicon layer which is not doped with impurities and forming a nitride film thereon, an impurity ion implantation of N conductivity type and P conductivity type is performed through a masking process so that channeling of impurities is prevented by the nitride film. Improve reliability

또한 N도전형의 불순물이 주입된 폴리실리콘과 P도전형의 불순물이 주입된 폴리실리콘과의 식각속도의 차이를 질화막으로서 보상하므로서 최종적으로 서로 동일한 크기의 듀얼게이트를 형성할 수 있다.In addition, by compensating for the difference in etching speed between the polysilicon implanted with N-conductive impurities and the polysilicon implanted with P-conductive impurities as a nitride film, dual gates having the same size may be finally formed.

Claims (5)

필드산화막이 형성된 반도체기판상에 게이트절연막을 형성하고, 게이트절연막상에 불순물이 도핑되지 않은 폴리실리콘층을 형성하는 공정과,Forming a gate insulating film on the semiconductor substrate on which the field oxide film is formed, and forming a polysilicon layer not doped with impurities on the gate insulating film; 상기 폴리실리콘층상에 제 1 절연막을 형성한 후 NMOS게이트가 형성될 제 1 영역과 PMOS게이트가 형성될 제 2 영역으로 정의한 다음, 각각의 영역에 해당하는 폴리실리콘층에 서로다른 불순물 이온주입을 실시하는 공정과,After forming a first insulating film on the polysilicon layer, it is defined as a first region where an NMOS gate is to be formed and a second region where a PMOS gate is to be formed, and then different impurity ions are implanted into a polysilicon layer corresponding to each region. Process to do, 상기 제 2 영역의 제 1 절연막을 제거하여 노출된 폴리실리콘층상에 PMOS게이트 형성용 패턴을 형성하고, 제 1 영역의 제 1 절연막상에 NMOS게이트 형성용 패턴을 형성하는 공정과,Removing the first insulating film of the second region to form a PMOS gate forming pattern on the exposed polysilicon layer, and forming an NMOS gate forming pattern on the first insulating film of the first region; 상기 NMOS 및 PMOS게이트 형성용 패턴을 마스크로 상기 게이트절연막이 노출되도록 식각하여 NMOS게이트 및 PMOS게이트를 형성하는 공정과,Forming an NMOS gate and a PMOS gate by etching the gate insulating layer by using the NMOS and PMOS gate formation patterns as a mask; 상기 NMOS게이트 및 PMOS게이트의 양측에 LDD영역을 갖는 소오스/드레인 불순물영역을 형성하는 공정과,Forming a source / drain impurity region having an LDD region on both sides of the NMOS gate and the PMOS gate; 상기 NMOS게이트 및 PMOS게이트의 표면과, 소오스/드레인 불순물영역의 반도체기판상에 실리사이드를 형성하는 공정을 포함하여 이루어지는 것을 특징으로 하는 반도체소자 제조방법.And forming a silicide on the surfaces of the NMOS gate and the PMOS gate and the semiconductor substrate in the source / drain impurity region. 제 1 항에 있어서,The method of claim 1, 상기 NMOS게이트 양측의 소오스/드레인 불순물영역은 P도전형이고 PMOS게이트 양측의 소오스/드레인은 N도전형의 불순물로 이루어지는 것을 특징으로 하는 반도체소자 제조방법.The source / drain impurity regions on both sides of the NMOS gate are P conductive, and the source / drain on both sides of the PMOS gate are N conductive. 제 1 항에 있어서,The method of claim 1, 상기 제 1 절연막은 실리콘질화막으로 이루어지는 것을 특징으로 하는 반도체소자 제조방법.And the first insulating film is formed of a silicon nitride film. 제 1 항에 있어서,The method of claim 1, 상기 제 1 영역의 제 1 절연막을 식각할 때 제 2 영역의 폴리실리콘층이 소정두께로 식각되어지는 것을 특징으로 하는 반도체소자 제조방법.And when the first insulating film of the first region is etched, the polysilicon layer of the second region is etched to a predetermined thickness. 제 1 항에 있어서,The method of claim 1, 상기 실리사이드를 형성하는 공정은 NMOS게이트 상측의 제 1 절연막을 제거하는 공정과,The forming of the silicide may include removing the first insulating layer on the upper side of the NMOS gate; 전면에 제 2 절연막을 형성한 후 에치백하여 NMOS게이트 및 PMOS게이트의 양측면에 사이드월을 형성하는 공정과,Forming a sidewall on both sides of the NMOS gate and the PMOS gate by etching back after forming a second insulating film on the entire surface; 전면에 실리사이드화가 가능한 물질을 증착한 후 열처리하는 공정으로 이루어지는 것을 특징으로 하는 반도체소자 제조방법.A method of manufacturing a semiconductor device, comprising the step of depositing a silicideable material on the entire surface and then performing a heat treatment.
KR1019970021326A 1997-05-28 1997-05-28 Method of manufacturing semiconductor device KR100223935B1 (en)

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