JPS6052593B2 - Manufacturing method of semiconductor device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a semiconductor device, and particularly to a method for manufacturing a MOS semiconductor device.

[Technical background of the invention and its problems]

As elements become smaller in MOS semiconductor devices, drawbacks such as a decrease in drain breakdown voltage and short channel effects occur.

Therefore, for example, a deep channel ion implantation technique is known as a technique for improving the drain breakdown voltage and preventing the short channel effect.

This improves the drain breakdown voltage and prevents the short channel effect by deeply ion-implanting impurities of the opposite conductivity type to the source and drain regions (same conductivity type as the substrate) into the silicon substrate of the channel region. This technology is
It is also applied to the manufacture of semiconductor devices formed on insulating substrates, such as 505, to improve drain breakdown voltage and prevent short channel effects, as well as to reduce back channel leakage (leakage current flowing through the silicon surface on the insulating substrate side). ) In order to prevent this, impurities of the opposite conductivity type to the source and drain regions are ion-implanted into the vicinity of the interface with the silicon insulating substrate below the channel region. but,
When this deep channel ion implantation technique is used, the implanted impurities have a distribution in the depth direction, making it difficult to control the impurity concentration on the substrate surface (channel region).

In particular, as the dose of ion implantation increases, the effect on the surface concentration also increases, making it difficult to control the threshold voltage of the transistor. In addition, since the substrate concentration increases when this technology is used, the substrate effect (a phenomenon in which the threshold voltage 1 increases greatly as the source-substrate voltage 5 increases), where the substrate concentration is NA, Vth is (proportional to ) makes the threshold voltage more likely to fluctuate, which adversely affects the device. Furthermore, in SOS, an increase in the impurity concentration in silicon results in a reduction in the speed of the transistor. In order to eliminate the drawbacks mentioned above,
P (or N) pocket formation technology is known as a recent new technology (for example, S. Oguraetal
．． 66AhalfmicrOnMOSFETuning
dOudleimplantedlJ)D! 5.IED
M82, 718 (1982)).

This technology consists of a low concentration impurity region near the gate electrode and a high concentration impurity region adjacent to these regions.
) By forming a P-type (or N-type) impurity region (pocket region) in the vicinity of the gate electrode in contact with the source and drain regions of the structure, the drain breakdown voltage is improved and the short channel effect is prevented. The outline of this P (or N) pocket formation technique will be explained with reference to FIG.

First, a gate electrode 3 made of polycrystalline silicon is formed, for example, on a device region of a P-type silicon substrate 1 surrounded by a field oxide film (not shown) with a gate oxide film 2 interposed therebetween. Next, using the gate electrode 3 as a mask, a P-type impurity is added as a source.
Ions are implanted deeply into the entire surface of the planned drain area. Next, in order to form the source and drain regions of the LDD structure, N-type impurities are first ion-implanted at a low dose using the gate electrode 3 as a mask. Next, for example, C
After depositing the VD oxide film, remaining CVD oxide films 4, 4 are removed on the side surfaces of the gate electrode 3 by, for example, reactive etching.
form. Next, N-type impurities are ion-implanted at a high dose using the gate electrode 3 and the remaining C-containing films 4, 4 as masks. Next, the impurities are diffused by heat treatment to form the source and drain regions 5 and 6 and the source and drain regions, which are made up of shallow N type impurity regions 5a and 6a near the gate electrode 3 and deep N+ type impurity regions 5b and 6b adjacent to these regions. P-type impurity regions (pocket regions) 1 and 7 are formed in contact with the drain regions 5 and 6 and located deep in the vicinity of the gate electrode 3. Thereafter, wiring and the like are formed according to normal steps.
Note that the channel ion implantation for controlling the threshold value may be a shallow channel ion implantation. However, the above-mentioned P
In the (or N) pocket formation technique, P-type impurities are ion-implanted into the entire area where the source and drain are to be formed using the gate electrode 3 as a mask. will be mixed,
There is a drawback that the resistance of the source and drain regions 5 and 6 does not decrease much.

This also applies to the case where an N-type pocket region is formed in a P-channel transistor. Furthermore, in order to lower the resistance of the source and drain regions 5 and 6, it is necessary to lower the dose of P-type impurity ion implantation, but in such a case, unless the source and drain regions 5 and 6 are made into an LDD structure, The P-type impurity regions (pocket regions) 7, 7 are canceled out by the N-type impurity, making it impossible to achieve the intended purpose. Therefore, in order to form the source and drain regions 5 and 6 of the LJ)D structure, the number of photo-etching steps (PEP) may be increased, thereby complicating the process. Furthermore, when the above method is applied to an SOS device, the source and drain regions are canceled out by impurities of opposite conductivity type, making it difficult to extend to the silicon-insulating substrate interface, making it easier to form a PN junction.

This results in an increase in stray capacitance, resulting in a decrease in speed, and in the inverter circuit, resulting in an increase in leakage current. [Object of the Invention] The present invention has been made in view of the above circumstances, and it is possible to form a pocket region in a simple process, effectively improve the drain breakdown voltage, and prevent the short channel effect. Furthermore, the present invention aims to provide a method for manufacturing a semiconductor device that does not cause a decrease in speed or the like.

[Summary of the invention]

In the method for manufacturing a semiconductor device of the present invention, a gate electrode is formed on the surface of an element region of a first conductivity type semiconductor layer via a gate insulating film, and an insulating film (for example, a plasma SiO2 film) is deposited on the entire surface. The side walls of the gate electrode are selectively etched away, and then impurities of the first conductivity type are ion-implanted using the remaining insulating film as a mask. After further removing the remaining insulating film, the second conductive type is implanted using the gate electrode as a mask. The main idea is to ion-implant type impurities and form second conductivity type source and drain regions and first conductivity type impurity regions (pocket regions) by heat treatment.

According to this method, the first
Since the conductivity type impurity is ion-implanted only in the vicinity of the gate electrode, it does not increase the resistance of the source and drain regions, and it is also possible to implant high-dose ions, so that the source and drain regions can be easily implanted. It is not necessary to have an LDD structure.

Therefore, the pocket region can be formed in a simple process, the drain breakdown voltage can be effectively improved, the short channel effect can be prevented, and there is no reduction in speed. Note that the source and drain regions are
With the D structure, fluctuations in threshold voltage due to generation of hot carriers can also be prevented. [Embodiments of the Invention] Hereinafter, a second embodiment in which the present invention is applied to CMOS manufacturing will be described.
This will be explained with reference to Figure a-1.

First, an N-type silicon substrate 1 with a surface crystal orientation (100)
After selectively forming a P-type well region 12 in a part of 1,
Field oxide film 1 with a thickness of 8000A according to the selective oxidation method
form 3.

Next, a gate oxide film 14 with a thickness of 500A is formed on the surface of the element region surrounded by the field oxide film 13, and after shallow channel ion implantation is performed, a polycrystalline silicon film with a thickness of 5000A is deposited on the entire surface. Cl3 in one incident in 1995 (generation)
Perform diffusion. Next, CVD with a thickness of 7,000 people was applied to the entire surface.
After depositing the oxide film, this CVD oxide film and the polycrystalline silicon film are sequentially patterned to form the gate electrode 151.
, 152 and CVD oxide film patterns 161, 16 thereon.
form 2. This CVD oxide film pattern 161, 16
2 has the effect of significantly increasing the step difference in the gate electrode portion (as shown in FIG. 2a). Subsequently, a plasma SiO2 film 17 with a thickness of 1.2 μm is deposited on the entire surface (as shown in FIG. 1B). Subsequently, this plasma SiO2 film 17 is etched with a 5% HF buffer solution for 130 seconds. At this time, the thickness of the plasma SiO2 film 17 on the side wall of the gate electrode step part is slightly thinner than other parts, and the etching rate is faster, so the side wall part of the gate electrode is selectively etched (as shown in figure c). ). Next, the substrate 1 other than the P-type well region 12
After forming a photoresist pattern 18 on 1, using this photoresist pattern 18 and the remaining plasma SiO2 film 17 on the well region 12 as a mask, B+ is ion-implanted under the conditions of acceleration energy 100 keV1 dose amount 5×1P/c#I. (Illustrated in figure d).

Subsequently, using the photoresist pattern 18 as a mask, the plasma SiO film 17 on the well region 12 is removed by CVD.
The oxide film pattern 162 and the gate oxide film 14 are coated with 5% HF.
Etch away with buffer solution for 6 minutes. Subsequently, using the photoresist pattern 18 and the gate electrode 152 on the well region 12 as a mask, As+ ions are implanted into the well region 12 at an acceleration energy of 40 keV and a dose of 1.times.10@15 /d (as shown in the figure e). After removing the photoresist pattern 18, a photoresist pattern 19 is formed on the well region 12.

Next, using the photoresist pattern 19 and the remaining plasma SiO2 film 17 on the substrate 11 other than the well region 12 as a mask, P+ is applied to the substrate 11 with an acceleration energy of 3
Ion implantation is performed under the conditions of 50 ke and a dose of 5×10 13 /CFll (as shown in the figure f). Subsequently, using the photoresist pattern 19 as a mask, the plasma SlO2 film 17 remaining on the substrate 11 and the CVD oxide film pattern 161 are
Then, the gate oxide film 14 is removed by etching with a 5% buffer solution for 6 minutes. Next, using the photoresist pattern 19 and the gate electrode 151 on the substrate 11 as a mask, the substrate 11 is
Accelerate B+ to 1 with energy of 20 keV and dose of 1×1
Ion implantation is performed under the condition of 015/d (as shown in g in the figure). Next, after removing the previous photoresist pattern 18, 95
In step (3), impurities are diffused by three-step heat treatment, and the P+ type source and drain regions 2 are added to the substrate 11 other than the well region 12.
0, 21 and these source and drain regions 20, 21, N-type impurity regions (pocket regions) 22, 22 located deep near the gate electrode 151'' are well region 1.
2, N+ type source and drain regions 23 and 24 and a gate electrode 15 in contact with these source and drain regions 23 and 24;
P-type impurity regions (pocket regions) 25, 25 located at deep positions near 2 are formed, respectively (as shown in h in the figure).

Subsequently, after depositing a CVD oxide film 26 on the entire surface, contact holes 27, . . . are opened. Subsequently, after depositing an AI film on the entire surface, it is patterned to form interconnections 28, etc., thereby manufacturing a CMOS (as shown in FIG. 1). According to such a method, plasma SiQ. The sidewall portion of the gate electrode of the film 17 is selectively etched away, and in the process shown in FIG. In the step shown in FIG. f, phosphorus ions are implanted into the substrate 11 using the remaining plasma SiO2 film 17 as a mask to form an N-type pocket region.

That is, the impurity for forming the pocket region is ion-implanted only in the vicinity of the gate electrode. Therefore, unlike the conventional P (or N) pocket formation technique, in which ions are implanted into the entire surface of the intended source and drain regions, the resistance of the source and drain regions does not increase.
The speed never decreases. In addition, since there is no risk of increasing the resistance of the source and drain regions, even if the dose of impurity ion implantation for forming the P-type and N-type pocket regions 22, 22, 25, and 25 is increased, the source and drain regions will not increase in resistance. has no effect on the

Therefore, even if the source and drain regions are not formed into an LDD structure, the pocket regions are not canceled out. Therefore, even when the method of the present invention is applied to CMOS manufacturing as in the above embodiment, the number of images in the photo-etching process (PEP) does not increase, and reactive ion etching (reactive ion etching), which causes damage, does not increase. There is no need to use RIE. Furthermore,
In the method of the present invention, shallow channel ion implantation for threshold control is sufficient. Therefore, the threshold value can be easily controlled, and since the substrate concentration remains low, there is almost no substrate effect. From the above, if the method of the present invention is used, the drain breakdown voltage can be improved with a simple process, and the short channel effect can be prevented.
Furthermore, it is possible to manufacture fine elements with stable characteristics without reducing speed.

Note that if the method of the present invention is applied to an SOS device, the impurities forming the pocket region will not prevent the impurities forming the source and drain regions from spreading downward, so the source and drain regions can be easily formed using silicon. - Reaches the sapphire substrate. Therefore, an increase in stray capacitance due to the PN junction can be prevented, and an increase in leakage current in the inverter circuit can be prevented. Further, the resource and drain regions may have an LDD structure, which is different from the above embodiment.

The manufacturing process in this case will be explained with reference to FIGS. 3a-f. First, after going through the steps up to FIG. 2d, the photoresist pattern 18 is removed and a photoresist pattern 29 is formed on the well region 12.

Next, this photoresist pattern 29 and well region 1
Remaining plasma SiO2 film 17 on substrates 11 other than 2
For example, P+ ions are implanted into the substrate 11 using as a mask (as shown in FIG. 3A). Next, photoresist pattern 2
After removing 9, the remaining plasma SlO2 film 17, C
vDrl! The oxide film patterns 161 and 162 and a portion of the gate oxide film 14 are removed by etching. Next, after depositing a CV cut film on the entire surface, reactive ion etching (
Residual CVD oxide films 30, . . . are formed on the side walls of the gate electrodes 151, 152 by RIE). Subsequently, a photoresist pattern 31 is formed on the substrate 11 other than the well region 12.
After forming the photoresist pattern 31, the gate electrode 152, and the remaining CVD oxide films 30, 3 on the side walls thereof,
Using As+ as a mask, As+ ions are implanted into the well region 12 under the conditions of an acceleration energy of 40 keV1 and a dose of 3×10 15 /Cfi (as shown in FIG. After removing the remaining CVD oxide films 30, 30 on the side walls with an HF solution, As+ ions are implanted under the conditions of an acceleration energy of 40 ICEVl and a dose of 5×10 13 /Cii (as shown in the figure c). Next, after removing the photoresist pattern 31, the well region 12 is removed.
A photoresist pattern 32 is formed thereon.

Subsequently, this photoresist pattern 32, the gate electrode 151 on the substrate 11, and the remaining °C V diode film 3 on the side wall thereof.
Acceleration energy of B+ is 20ke using 0.30 as a mask
V1 dose 2×1P/C7l! Ion implantation is performed under the following conditions (as shown in figure d). Subsequently, after removing the remaining CVD oxide films 30, 30 on the side walls of the gate electrode 151 on the substrate 11, B+ is
Ion implantation is performed under the condition of 13/d (as shown in figure e). Next, heat treatment is performed to form source and drain regions 33 and 34 in the substrate 11 other than the well region 12 with an LDD structure consisting of P type impurity regions 33a and 34a near the channel region and P+ impurity regions 33b and 34b adjacent to these regions. 34
N-type impurity regions (pocket regions) 35, 35, which are in contact with these source and drain regions 33, 34 and located deep near the gate electrode 151, are placed in the well region 12, and N-type impurity regions 36a, 37a near the channel region. and N+ type impurity regions 36b, 37b adjacent to these regions.
P-type impurity regions (pocket regions) 38 and 38 are formed in contact with these source and drain regions 36 and 37 and located deep in the vicinity of the gate electrode 152 (as shown in figure f). Thereafter, wiring and the like are formed according to normal steps. According to such a method, although the process is complicated, it is possible to obtain the same effect as the above embodiment.Furthermore, since the source and drain regions have an LDD structure, the threshold voltage due to the generation of hot carriers can be reduced. Since fluctuations can be prevented, this method is suitable for miniaturizing thin layer elements. Note that in the above embodiment, CVD is applied on the gate electrode 151152.
Although oxide film patterns 161 and 162 were formed, this CV
The D oxide film patterns 161 and 162 do not necessarily need to be provided.

Furthermore, although the gate electrodes 151 and 152 are formed of polycrystalline silicon, they are not limited to this, and high melting point metal silicide such as MOSi2 may be used. [Effects of the Invention] As detailed above, according to the method for manufacturing a semiconductor device of the present invention, drain breakdown voltage can be improved, short channel effects can be prevented, and the speed can be maintained without decreasing, resulting in stable operation. This method has remarkable effects such as being able to manufacture fine elements with specific characteristics.

[Brief explanation of drawings]

Figure 1 shows an N-channel MOS manufactured by the conventional method.
A cross-sectional view of a transistor, FIG. 2 a-i is a cross-sectional view showing a CMOS manufacturing method in an embodiment of the present invention, and FIG.
f is a sectional view showing a CMOS manufacturing method in another embodiment of the present invention. 11...N-type silicon substrate, 12...P
type unil region, 13... field oxide film, 14...
...Gate oxide film, 151,152...Gate electrode, 161,162...CVD oxide film pattern, 1
7...Plasma SlO2 film, 18, 19, 29,
31, 32... Photoresist pattern, 20,
21...1P+source, drain region, 22...
N-type impurity region (pocket region), 23, 24...
N+ type source, drain region, 25...P type impurity region (pocket region), 26...CVD oxide film, 27...contact hole, 28...
・Wiring, 30...Remaining CVD oxide film, 33
a, 34a...P-type impurity region, 33b, 34b...
...P+ type impurity region, 33, 34...
Source, drain region, 35...N type impurity region (pocket region), 36a, 37a...N type impurity region, 36b, 37b...N type impurity region, 3
6, 37... Source, drain region, 38...
...P-type impurity region (pocket region).

Claims (1)

[Claims] 1. A step of forming a gate electrode on the surface of the element region of the first conductivity type semiconductor layer via a gate insulating film, and after depositing the insulating film on the entire surface, forming a gate electrode on the side wall of the gate electrode of the insulating film. a step of selectively etching away a portion; a step of ion-implanting a first conductivity type impurity using the remaining insulating film as a mask;
After removing the remaining insulating film, ion-implanting a second conductivity type impurity as the gate electrode mask;
The impurity is diffused by heat treatment to form a second conductivity type source,
In contact with the drain region and these source and drain regions,
A method of manufacturing a semiconductor device, comprising the step of forming an impurity region of a first conductivity type located near the gate electrode. 2. The method of manufacturing a semiconductor device according to claim 1, wherein a plasma SiO_2 film is used as the insulating film. 3. A patent characterized in that another insulating film is deposited on the gate electrode material deposited on the entire surface and sequentially patterned to form a gate electrode and a pattern of the other insulating film remaining on the gate electrode. A method for manufacturing a semiconductor device according to claim 1. 4 Using the gate electrode and remaining insulating film as a mask, first
Manufacturing a semiconductor device according to claim 1, characterized in that, before or after ion implantation of a conductivity type impurity, a second conductivity type impurity is implanted at a low dose using at least the gate electrode as a mask. Method.