JPS6055658A - Manufacture of semiconductor device - Google Patents

Abstract

PURPOSE:To prevent the short channel effect by effective improvement of the drain withstand voltage by a method wherein a pocket region is formed after the part of the side wall of a gate electrode is selectively removed by etching. CONSTITUTION:When a plasma SiO2 film 17 is deposited over the entire surface after formation of gate electrodes 151 and 152 and CVD oxide film patterns 161 and 162, and this film is successively etched, the part of the side wall of the gate electrode is selectively etched. Next, B<+> and P<+> are ion-implanted to a well region 12 and on a substrate, respectively, with the films 17 as a mask. Then, N type pocket regions 22 and 22 are formed in the neighborhood of the gate electrode 151, and P type pocket regions 25 and 25 in the neighborhood of the gate electrode 152, respectively. Thereby, the speed does not decrease because of no increase in resistances of the source and drain regions.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a method for manufacturing a cow conductor device, and more particularly to a method for manufacturing a MO8♀ conductor device.

[Technical background of the invention and its problems]

In the MO8-1 conductor device, as elements become smaller, disadvantages such as a decrease in drain breakdown voltage and a short channel effect occur.

Therefore, for example, a deep channel ion implantation technique is known as a technique for improving the drain breakdown voltage and preventing the short channel effect.

This sources the silicon substrate in the channel region.

By deeply ion-implanting impurities of the opposite conductivity type to the drain region (same conductivity type as the substrate), drain breakdown voltage is improved and short channel effects are prevented. This technology is also applied to the manufacture of conductor devices formed on insulating substrates, as typified by SO8.In addition to improving drain breakdown voltage and preventing short channel effects, this technology also reduces pack channel leakage (silicon on the insulating substrate side). In order to prevent (leakage current flowing through the surface), impurity ions of the opposite conductivity type to the source and drain regions are implanted near the interface between the silicon and the insulating substrate below the channel region.

However, using this deep channel ion implantation technique,
Since the implanted impurities have a distribution in the depth direction, it is difficult to control the impurity concentration at the substrate surface (channel region). In particular, when the dose of ion implantation increases, the effect on the surface concentration becomes large, and as a result, it becomes difficult to control the threshold voltage of the transistor. In addition, this technique increases the substrate concentration, so substrate effects (source and
A phenomenon in which the threshold voltage ■□ increases significantly as the voltage vth between the substrates increases, and when the substrate concentration is NA, vth
(is proportional to the width), the threshold voltage tends to fluctuate, which adversely affects the device. Furthermore, in SO8, when the impurity concentration in silicon increases, the speed of the transistor decreases.

In order to overcome the above-mentioned drawbacks, recently new techniques such as PC6 or N) pocket formation technology are known (for example, S, Ogura et al.

t'A half m1cron MOSFET us
ing double 1plantedLDD,”
, IEDM82.718. (1982)). This technique consists of low concentration impurity regions near the dirt electrodes and high concentration impurity regions adjacent to these regions. So-called LD
By forming a P-type (or N-type) impurity region (pocket region) near the dart electrode in contact with the source and drain regions of the D (Lightly Doped Drain) structure, υ improves drain breakdown voltage and prevents short circuits. This is intended to prevent channel effects.

The outline of this P (or N)/kerato formation technique will be explained with reference to FIG. First, for example, a P-type silicon substrate 1
f-) made of polycrystalline silicon through an oxide film 2 on the element region surrounded by a field oxide film (not shown).
Electrode 3 is formed. Next, using the dirt electrode 3 as a mask, P-type impurities are ion-implanted deeply into the entire surface of the intended source and drain regions. Next, in order to form the source and drain regions of the LDD structure, NW impurities are ion-implanted shallowly at a low dose using the r-to electrode 3 as a mask. Subsequently, after depositing, for example, a CVD oxide film on the entire surface, residual CVD oxide films 4, 4 are formed on the side surfaces of the r-to electrode 3 by, for example, reactive ion etching. Subsequently, the f-to-electrode 3 and the remaining CVD oxide films 4 are removed as a mass 5, and N-type impurities are ion-implanted at a high dose. Next, the cine fine particles are diffused by heat treatment to form a shallow N-type impurity region 5h near the dirt electrode 3.

6a and a deep furnace-type impurity region 5b adjacent to these regions.
, 6b and the dirt electrode 3 in contact with these source and drain regions 5°6.
P-type impurity regions (pocket regions) 7, 7 located deep in the vicinity are formed. Thereafter, wiring and the like are formed according to normal steps. Note that channel ion implantation for threshold control may be shallow channel ion implantation.

However, in the above-mentioned P (or N) pocket formation technique, P-type impurities are ion-implanted into the entire surface of the source/drain formation area using the dirt electrode 3 as a mask, so the N-type source/drain regions 5.6 P-type impurities are mixed in the source and drain regions 5 and 6.
The disadvantage is that the resistance of υ does not decrease.

This also applies to the case where an N-type pocket region is formed in a P-channel transistor. Furthermore, in order to lower the resistance of the source and drain regions 5 and 6, it is necessary to lower the dose of P-type impurity ion implantation;
If it is not made into an LDD structure, the P-type impurity regions (pocket regions) 7, 7 will be canceled by the N-type impurity,
Unable to achieve the intended purpose. Therefore, L
In order to form the source and drain regions 5 and 6 of the DD structure, the number of photo-etching steps (PEP) may increase in some cases, making the process complicated.

Furthermore, when the above method is applied to an SOS device, the source and drain regions are canceled out by impurities of opposite conductivity type, making it difficult to extend to the silicon-insulating substrate interface, making it easier to form a PN junction.

This results in an increase in stray capacitance, resulting in a decrease in speed, and in the inverter circuit, resulting in an increase in leakage current.

[Purpose of the invention]

The present invention has been made in view of the above circumstances, and it is possible to form a pocket region through a simple process, effectively improve drain breakdown voltage, prevent short channel effect, and reduce speed. It is an object of the present invention to provide a method for manufacturing a semiconductor device that does not cause problems such as the following.

[Summary of the invention]

In the method for manufacturing a semiconductor device of the present invention, an f-) electrode is formed on the surface of the element region of the first conductive type conductor layer via a dirt insulating film, and an insulating film (for example, a plasma SiO□ film) is deposited on the entire surface. After that, the sidewall portion of the y-upper electrode is selectively etched away, and then impurities of the first conductivity type are ion-implanted using the remaining insulating film as a mask. After removing the remaining insulating film, r- The main idea is to ion-implant impurities of the second conductivity type using the upper electrode as a mask, and then form the source and drain regions of the second conductivity type and the impurity regions (pocket regions) of the first conductivity type through heat treatment. .

According to this method, the first
What is the conductivity type impurity? -) Since ions are implanted only in the vicinity of the electrodes, there is no increase in the resistance of the source and drain regions, and a high dose of ion implantation is possible, making the source and drain regions LDD structure. No need. Therefore, the pocket region can be formed in a simple process, the drain breakdown voltage can be effectively improved, the short channel effect can be prevented, and there is no reduction in speed. Note that if the source and drain regions have an LDD structure, it is possible to prevent fluctuations in threshold voltage due to the generation of hot carriers.

[Example of the invention] Hereinafter, a second example in which the present invention is applied to the production of 0MO8 will be described.
This will be explained with reference to figures (,) to (i).

First, an N-type silicon substrate 1 with a surface crystal orientation (100)
After selectively forming a P-type well region 12 in a part of 1,
Thickness soo according to selective oxidation method.

A field oxide film 1s of λ is formed. Next, a 500x thick oxide film I4 is formed on the surface of the element region surrounded by the field oxide film 13, and after shallow channel ion implantation is performed, a polycrystalline silicon film 9-5000x thick is deposited on the entire surface. Then, perform diffusion at 950°C for 15 minutes. Subsequently, after depositing a CVD oxide film with a thickness of 700mm over the entire surface, this CVD oxide film and the polycrystalline silicon film are sequentially patterned to form dirt electrodes 15. , I.B.

and a CVD oxide film pattern 161.16@ thereon. This CVD oxide film, f-turn 161.

162 has the effect of making the difference in level of the dirt electrode portion significant (as shown in FIG. 2(, )). Next, apply a thickness of 1.
A 2 μm plasma SiO□ film 11 is deposited (see figure (b)
). Subsequently, this plasma S to 2 film 17 is etched for 130 seconds using a 5-chip buffer solution. On this occasion,
The thickness of the plasma 5IO2 film 17 on the side wall of the step part of the dirt electrode is slightly thinner than other parts, and the etching rate is faster, so the side wall part of the dirt electrode is selectively etched (as shown in FIG. 3(c)). ).

Next, after forming a photoresist pattern 18 on the substrate 11 other than the P-type well region 12, using the photoresist pattern 18 and the remaining plasma 5102 film 17 on the well region IO-12 as a mask, B is applied at an acceleration energy of 100 ksV. Dose amount 5
Ion implantation was performed under the condition of 10 7 cm” (see figure (d)
). Next, Photoregis) A? turn 1
Plasma 5102 on the well region 12 using 8 as a mask
The film 17, the CVD oxide film a4p:/162, and the dirt oxide film 14 are removed by etching with a 5% HF buffer solution for 6 minutes. Subsequently, using the photoresist pattern 18 and the f-) electrode 15 snow on the well region 12 as a mask, As+ ions are implanted into the well region 12 at an acceleration energy of 40 k@V and a dose of I x 107 cm.
Same figure (・) shown).

Next, after removing the photoresist pattern 18,
A photoresist pattern 19 is formed on the well region 12. Subsequently, the remaining plasma S on the substrate 11 other than this photoresist pattern 19 and the well region 12 is
Using the iO2 film 17 as a mask, P+ ions are implanted into the substrate 11 under the conditions of an acceleration energy of 350 ksV and a dose of 5.times.10.sup.15/2 (as shown in FIG. 4(f)). Subsequently, using the photoresist pattern I9 as a mask, the remaining plasma 5102 film 17, CvD oxide film pattern 261, and dirt oxide film 14 on the substrate 11 are etched away for 6 minutes using a 5000 ml buffer solution. Next, the photoresist pattern 19 and the dirt electrode 15 on the substrate 11! Accelerate B+ onto the substrate 11 using as a mask with an energy of 20 ke
Ion implantation is performed under the conditions of V and a dose of I x 10 /an (as shown in the same encyclopedia).

Next, after removing the photoresist pattern I9,
Heat treatment is performed at 950° C. for 30 minutes to diffuse impurities, and P+ type source and drain regions 20.21 and these source and drain regions 20.21 are formed in the substrate 11 other than the well region 12.
N located in a deep position near the dart electrode 151
Type impurity regions (pocket regions) z; t, zz are connected to type 1 source and drain regions 23 and 24 in the well region 12 and P which is in contact with these source and drain regions zs and z4 and located at a deep position near the dirt electrode 152. Type impurity regions (pocket regions) 25° and 25° are formed respectively (Figure (h)
(Illustrated). Subsequently, after depositing a CVD oxide film 26 on the entire surface, contact holes 27. ...Drill a hole. Subsequently, an At film is deposited on the entire surface and then patterned to form an At wiring 28. ... is formed to produce 0MO8 (see the same figure (
1) As shown).

According to this method, in the step shown in FIG. 2(C), the side wall portion of the Y-toe electrode of the plasma 5IO2 film 17 is selectively etched away, and in the step shown in FIG. Plasma 5 IO2 film 1 remaining for pocket region formation
Using 7 as a mask, ion implantation is performed into the well region 12, and phosphorus is implanted into the substrate 11 using the plasma 5in2 film 17 remaining as a mask for forming the N-type pocket region in the step shown in the same figure (f). . That is, the impurity for forming the pocket region is ion-implanted only in the vicinity of the dart electrode. Therefore, the conventional P (h or N), j? This method does not increase the resistance of the source and drain regions, unlike the ticket forming technique in which ions are implanted into the entire surface of the intended source and drain regions, so there is no reduction in speed.

Furthermore, since there is no risk of increasing the resistance of the source and drain regions, the P-type and N-type pocket regions 22, 22, 25
．． Even if the dose of impurity ion implantation is increased to form the source.

It does not affect the drain region. Therefore, even if the source and drain regions are not formed into an LDD structure, the pocket regions are not canceled out.

Therefore, as in the above embodiment, the method of the present invention is applied to 0MO8
Even when applied to the production of products, the number of photo-etching steps (PEP) does not increase, and there is no need to use reactive ion etching (RIE), which causes damage.

Furthermore, in the method of the present invention, only shallow ion implantation for controlling the threshold value is sufficient for channel ion implantation. therefore,
It is easy to control the threshold value, and since the substrate concentration remains low, there is almost no substrate effect.

14- Drain withstand voltage can be improved through a simple process, short channel effects can be prevented, and fine devices with stable characteristics can be manufactured without reducing speed.

Note that when the method of the present invention is applied to an SOS device, the impurity forming the pocket region becomes the source.

Since the downward spread of impurities forming the drain region does not prevent υ, the source and drain regions easily reach the silicon-sapphire substrate. However, P
An increase in stray capacitance due to the N junction can be prevented, and an increase in leakage current can be prevented in an inverter circuit.

Also, unlike the above embodiment, the source and drain regions are
It may also have a D structure. The manufacturing process in this case is shown in Figure 3 (
) to (f).

First, after going through the steps up to FIG. 2(d), the photoresist pattern 18 is removed, and photoresist 74 turns 29 are formed on the well region 12. Next, using this photoresist 74 turn 29 and the remaining plasma 5IO2 film 17 on the substrate ll other than the well region 12 as a mask, the substrate I
For example, P+ is ion-implanted into Z (as shown in Figure 3 (,)).
. Subsequently, after removing the photoresist pattern 29,
The remaining plasma S10□ film 17, CVD oxide film no-turn 161162, and part of the dirt oxide film 14 are removed by etching. Next, after depositing a CVD oxide film on the entire surface, reactive ion etching (RIE) is performed.
≠ Straw + Gate electrode 151.15 Remaining CVD oxide film 30. . . . Next, a photoresist layer 4 is formed on the substrate 11 other than the well region 12. After forming the turns 31, this photoresist 74 turns 31
, the date electrode 158 and the remaining CVD oxide film 30.30 on its sidewall are used as a mask to accelerate As+ into the well region 12 at an energy of 71/A' -40 k@V.

Ion implantation was performed at a dose of 3 x 10" 7 cm2 (as shown in FIG. 2(b)). Subsequently, the remaining CVD oxide film 30.30 on the side wall of the date electrode 152 on the well region 12 was implanted.
After removing As+ with HF solution, the acceleration energy of As+ is 40
Ion implantation is performed under the conditions of @V and a dose of 5×10”/cal (as shown in FIG. 2C).

Next, after removing the photoresist ZF turns 31, photoresist 74 turns 32 are formed on the well region 12. Next, this photoresist pattern 32,
Dirt electrode 15 on substrate Il and residual CV on its sidewall
B was accelerated at an energy of 20 keV using the D oxide film 30.30 as a mask.

Ion implantation is performed at a dose of 2×10 / under negative conditions (as shown in FIG. 2(d)). Next, the dart electrode 1 on the substrate 11
5. After removing the remaining CVD oxide film 30.30 on the sidewalls,
B+ to acceleration energy 20・V, )' −, 1”Ji
Ion implantation was performed under the conditions of 15 x 10”/- (see the same figure).
,) as shown).

Next, heat treatment is performed to remove the substrate 1 other than the well region 12.
1, P-type impurity regions 33*, 34h near the channel region
and a P+ type impurity region 33b adjacent to these regions,
Source and drain region 3 of LDD structure consisting of
3.34 and these source and drain regions 33.34, 17- An N-type impurity region (pocket region) 35.35 located deep near the dart electrode 151 is added to the well region 12, and an N-type impurity region (pocket region) 35.35 near the channel region is added to the well region 12. Impurity regions 36&, 31m and N+ type impurity #3'6b adjacent to these regions,
37. source and drain regions 36 and 37 of an LDD structure consisting of source and drain regions 36, . 9
A P-type impurity region (pocket region) 38, 38 is formed in contact with the dirt electrode 7 and located deep in the vicinity of the dart electrode 15 (as shown in FIG. 7(f)). Thereafter, wiring and the like are formed according to normal steps.

According to such a method, although the process becomes complicated, it is possible to obtain the same effect as in the above embodiment, and furthermore, the source,
Since the drain region has an LDD structure, it is possible to prevent fluctuations in the threshold voltage due to the generation of hot carriers, making this method even more suitable for further miniaturization of elements.

In the above embodiment, the dart electrode 15. .

CVD oxide film A on 152? l-7161,16° was formed, but this CVD oxide film/mother turn 161°18-16! does not necessarily have to be provided. Further, although the dart electrodes 151 and 152 are formed of polycrystalline silicon, they are not limited to this, and high melting point metal silicide such as Mo 812 may be used.

〔Effect of the invention〕

As detailed above, according to the method of manufacturing a hand conductor device of the present invention, it is possible to improve the drain breakdown voltage, prevent the short channel effect, and maintain stable characteristics without reducing the speed. It has remarkable effects such as being able to manufacture microscopic elements having the same characteristics.

[Brief explanation of drawings]

Figure 1 shows nine N-channel MO8s manufactured by conventional methods.
) A cross-sectional view of a transistor, FIGS. 2(,) to (1) are cross-sectional views showing a method of manufacturing 0MO8 in an embodiment of the present invention, and FIGS. 3(,) to (f) are other embodiments of the present invention. 0M in
FIG. 3 is a cross-sectional view showing a method for manufacturing O8. II...N-type silicon substrate, 12...P-type well region bLZ, 9...field oxide film, Z4...f-1
Oxide film, 151, 15t... dirt electrode, 161°1
62...CVD oxidation M'' turn, 17...Plasma 5IO2 film, 1B, 19,29,31.32...
Photoresist pattern, 20.21...PW source. Drain region, 22... N type impurity region (pocket region), 23.24... N+W source drain region, 25... P type impurity region (pocket region), 26.
...CVD oxide film, 27...contact hole, 2
B ・At wiring, 30-...Remaining CVD oxide film, 33a
. 34[...P-type impurity region, 33b, 34b...P
+ type impurity region, 33. 34... Source, drain region, 35... N type impurity region (pocket region), 36
*, 37th...N-type impurity region, 5...
36b, 37b...N4-type impurity region, s6
．． sy...source, drain region, 38...P
Type impurity region (pocket region).

Claims (4)

[Claims] (1) A step of forming a dirt electrode on the surface of the element region of the first conductive type conductor layer via a dirt insulating film, and after depositing an insulating film on the entire surface, selecting a side wall portion of the dirt electrode of the insulating film. a step of ion-implanting an impurity of a first conductivity type using the remaining insulating film as a mask; and a step of ion-implanting an impurity of a second conductivity type using the dirt electrode as a mask after removing the remaining insulating film; a step of ion-implanting and diffusing fine particles during heat treatment to form second conductivity type source and drain regions and first conductivity type impurity regions that are in contact with these source and drain regions and located near the dirt electrodes; A method for manufacturing a medium conductor device, comprising the steps of: (2) A method for manufacturing a hand conductor device according to claim 1, characterized in that a plasma 5io2 film is used as the insulating film. (3) Another insulating film is deposited on the dirt electrode material deposited on the entire surface, and these are sequentially patterned to form the dirt electrode and a pattern of the other insulating film remaining on the dirt electrode. A method for manufacturing a live conductor device i according to claim 1. (4) Before or after the ion implantation of the first conductivity type impurity using the dirt electrode and the remaining insulating film as a mask, the second conductivity type impurity is ion-implanted at a low dose using at least the dirt electrode as a mask. A method for manufacturing a conductor device according to claim 1.