JPS609139A - Semiconductor integrated circuit device - Google Patents

Abstract

PURPOSE:To enable to prevent generation of undesirable continuity between adjoining transistors without having a narrow channel effect by a method wherein a polycrystalline silicon thin film is brought into a low resistance state, and an electrode wherein a voltage can be applied from outside is formed in an element isolation region. CONSTITUTION:A silicon substrate 1 is oxidized by heat, a silicon oxide film 8 is formed on the surface, the part whereon an element isolation region will be formed is removed, and the surface of the substrate 1 is exposed. Boron is ion- implanted, an activating heat treatment is performed on the implanted ions, the silicon oxide film is removed, and a silicon nitride film 9 is coated on the whole surface. Subsequently, a silicon thin film 10 is selectively grown at the recessed part only of the substrate, phosphorus is diffused on the whole surface, and the above is brought into a sufficiently low resistance state. Then, the silicon thin film 10 is oxidized by heat, and a silicon oxide film 11 is formed. The silicon nitride film and the silicon oxide film are removed. Subsequently, a silicon thermal oxide film 4 is formed on the substrate 1, and a source diffusion layer and a drain diffusion layer are formed using a gate electrode 5 and another gate electrode as an ion-implantation mask.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to a semiconductor integrated circuit device, and in particular to element isolation technology for a semiconductor integrated circuit device composed of ultra-fine MO8 type field effect transistors that do not have a narrow channel effect. Regarding.

[Background of the invention]

In a semiconductor integrated circuit device (hereinafter abbreviated as IC) composed of conventional MO8 type field effect transistors,
It is known that a narrow channel effect occurs as the MO8 field effect transistor (hereinafter simply referred to as a transistor) is miniaturized. The above phenomenon occurs as the channel width in the direction perpendicular to the source-drain direction decreases, resulting in the threshold voltage value of the transistor, V? %, the phenomenon that the value increases is IC
This is an extremely troublesome problem in terms of design. The above phenomenon is due to the limitations of the conventional insulation isolation method called LOCO8, which is based on a selective oxidation method using a silicon nitride 16 film. That is, the conventional LOOO8 structure has a cross-sectional structure in the channel region as shown in FIG. 1 in a direction perpendicular to the source/drain direction. Reference numeral 1 designates a P conductivity type semiconductor substrate, 2 a P1 region which is constructed in self-alignment with a filled oxide film 3 and has a higher impurity concentration than the semiconductor substrate 1, 4 a gate oxide film, and 5 a gate electrode. In FIG. 1, as the channel width, that is, the interval between filled oxide films 3 becomes narrower, the proportion of the P0 region in the channel region increases. Therefore, in a narrow channel transistor, the current is smaller than the designed value, and the VT value increases as the channel width becomes narrower.

FIG. 2 shows another known technique, in which the transistors constituting the IC are separated from each other by a deposited oxide film 3 embedded in a semiconductor substrate l.

The element isolation technique using the buried oxide film described above has a drawback in that a phenomenon having characteristics opposite to the narrow channel effect in the LOCo8 structure occurs. That is, it is analytically known that when a voltage is applied to the gate electrode 5 in the direction of forming a channel, the gate potential in the channel region is high near the buried oxide film and low at the center of the channel region. Therefore, element isolation technology using a buried oxide film has the disadvantage that the VT value decreases as the channel width of the transistor becomes narrower.

FIG. 3 is a diagram showing another known technique regarding element isolation. By applying a ground potential or a negative potential to the electrode 7 isolated from the outside by the gate oxide film 4 and the interlayer insulating film 7, an inversion layer is formed on the semiconductor surface 1 of the υ electrode 7-level electrode. This method is called the υ filled plate method, which attempts to prevent this and isolate adjacent transistors. The device isolation method using the filled plate method described above also has a fatal drawback in I'Cs constructed using ultrafine transistors. That is, in the above IC, the element isolation region must also be miniaturized, but as the element isolation region is miniaturized, the distance between the drain of the transistor to be isolated and the north of the adjacent transistor also becomes shorter.

Therefore, even if an inversion layer is not formed on the surface of the semiconductor substrate 1 directly under the electrode 6, there is a risk of conduction between adjacent transistors due to punch-through or avalanche phenomenon when voltage is applied to the drain. There is. Therefore, the above-mentioned filled plate method is not suitable for ICs composed of fine transistors. Another drawback of the filled plate method is that unevenness occurs on the surface of the semiconductor substrate 1 due to the electrode 6, which impedes the miniaturization of the gate electrode 5 and, in the worst case, causes disconnection of the electrode wiring.

[Purpose of the invention]

SUMMARY OF THE INVENTION An object of the present invention is to provide an element isolation technique for semiconductor integrated circuits that eliminates the above-mentioned drawbacks of the prior art, does not have a narrow channel effect, and can prevent undesirable conduction between adjacent transistors.

Another object of the present invention is to provide a flat device isolation technique that does not cause wire breakage or hinder microfabrication.

[Summary of the invention]

The present invention focuses on the technology disclosed in Japanese Patent Application Laid-Open No. 58-9333, which is a variation of the element isolation technology using a buried insulating film shown in FIG. This is an improvement from the perspective of eliminating channel effects. The above-mentioned published patent relates to a structure in which the buried insulating film 3 in FIG. 2 is replaced with a polycrystalline silicon thin film isolated from the outside by an insulating film. The above-mentioned published patent was originally related to element isolation of an IC composed of bipolar transistors.
This was adopted to alleviate the strain remaining in the semiconductor substrate 1 and to prevent the occurrence of defects. Therefore, it is completely meaningless to lower the resistance of the polycrystalline silicon thin film by diffusing impurities, and the polycrystalline silicon thin film is completely isolated from the outside and kept in a floating state without any intentional diffusion of impurities. The above configuration is a variation of the device isolation technology using a buried insulating film shown in Figure 2, and the ultrafine transistor surrounded by the device isolation region exhibits narrow channel characteristics in which the VT value decreases as the channel width decreases. .

The present invention solves the conventionally unsolved narrow channel effect of ultrafine insulated gate field effect transistors by improving the element isolation technology using the buried insulating film method having a polycrystalline silicon thin film as described above. That is, the resistance of the polycrystalline silicon thin film is lowered by impurity diffusion or partial replacement with a high melting point metal film or a silicide film, and an electrode capable of applying stain pressure from the outside is formed in the element isolation region. . The above region is arranged in a mesh pattern over the entire surface of the semiconductor substrate on which the IC is constructed. Therefore, by applying a ground potential or a negative voltage to at least one part of the above electrode, the semiconductor surface potential near the element isolation region can be reduced. It can be controlled to be low regardless of the gate potential. The above control makes it possible to suppress the narrow channel effect in which the VT value of a transistor with an extremely narrow channel width decreases compared to a set value.

[Embodiments of the invention]

Hereinafter, the present invention will be explained in more detail with reference to Examples.

For convenience of explanation, the explanation will be made using drawings, but please note that important parts are shown enlarged.

Embodiment 1 FIGS. 4 and 5 are diagrams showing an embodiment of a semiconductor integrated circuit device according to the present invention, in which a P conductivity type resistivity 1Ω sub-silicon substrate 1 is thermally oxidized, and the surface of the silicon substrate 1 is Approximately 0.1
A silicon oxide film of μm thickness is formed. The silicon oxide film in the portion where the element isolation region is to be formed is removed by photolithography to expose the surface of the silicon substrate 1, and then the exposed portion of the silicon substrate 1 is coated with a thickness of approximately 0.5 μm by reactive sputtering.
Remove at a depth of . Next, boron ion implantation and activation heat treatment of the implanted ions were performed under the conditions of a dose of 5.times.10 "cm" and an acceleration energy of 30 KV. Under the above conditions, ions are not implanted directly under the silicon oxide film, but are implanted only into the bottom of the groove of the silicon substrate 1 that has been selectively removed. Note that the ion implantation and activation heat treatment described above may be omitted. Next, the silicon oxide film was removed, and a 20 μm silicon thermal oxide film 8 and a 100 μm thick silicon nitride film 9 deposited by chemical vapor phase reaction were deposited on the exposed entire surface of the semiconductor substrate 1. Thereafter, a silicon thin film 10 was selectively grown only in the recessed portions of the silicon substrate according to the method described in Japanese Patent Application No. 54-4302. Thereafter, phosphorus (P) was formed into a silicon thin film by a known thermal acid method.

It diffused into the inner metal surface and made the silicon thin film 1o sufficiently low in resistance. Next, the silicon thin film 1o was thermally oxidized to form a silicon oxide film 11 with a thickness of about 0.3 μm. In the above thermal oxidation, a silicon nitride film 8 is formed on the convex portion of the silicon substrate 1.
is present, and the growth of the oxide film is inhibited. After that,
The exposed silicon nitride film and the 20 μm thick silicon oxide film are removed. Thereafter, a 20 μm clean silicon thermal oxide film 4 is again formed on the silicon substrate 1, and gate electrodes 5 and gate electrodes are formed using known silicon gate technology.
A source diffusion layer and a drain diffusion layer were formed using the pole as a mask for ion implantation.

FIG. 5 is a cross-sectional view of the channel region in a direction perpendicular to the source/drain direction, and the source and drain diffusion layers are not shown. After the formation of the source/drain diffusion layer, a protective insulating film is formed and contact holes to the source diffusion layer, drain diffusion layer, gate electrode 5, and low resistance silicon thin film 10 are formed according to known techniques.

In forming the contact hole, the silicon thin film has a sufficiently low resistance and is arranged in a mesh pattern over the entire surface of the semiconductor integrated circuit device, so the contact hole can be formed at one location, preferably several locations within the semiconductor integrated circuit. That's fine. After forming the contact holes, aluminum wiring was provided according to the desired circuit configuration to manufacture a semiconductor integrated circuit device. In the wiring process described above, the silicon thin film 10 is configured so that a negative or zero potential is applied to the semiconductor substrate 1.

In the semiconductor integrated circuit device manufactured through the above manufacturing process, the Vt value of the ultrafine transistor with a channel width of 0.5 μIn and a channel length of 1 μm is -0.2■ in a floating state where no voltage is applied to the silicon thin film 10. The design value also showed a narrow channel effect that was -0.3V lower.
When configured to apply a voltage of -2 to the silicon thin film 10, the Vt value is -1-0, I V and the design value and M/ζ.
I was able to get a good match. When the voltage applied to the silicon thin film 10 is 12cm, the VT value of a transistor with a gate width of 1.0 μm increases by +〇 IV compared to the case where no voltage is applied to the silicon thin film 10. +
It became 0.2 ■. The above result shows that the channel width is 0.5μ
The VT value variation width of 0.3V due to the narrow channel effect of the ultrafine transistor of m is 0.3V. This means that it showed an improvement of 3 times compared to IV.

In this embodiment, an example is shown in which the resistance of the silicon thin film 10 is lowered by normal thermal diffusion, but the above-mentioned resistance reduction does not need to be achieved by impurity diffusion, and a silicide layer is formed on the silicon thin film 10 or silicon It may also be carried out by using a high melting point metal film for the edge of the thin film 10.

In this embodiment, for convenience of explanation, a semiconductor integrated circuit device constituted by an n-channel ultra-fine insulated gate field effect transistor using a P-conductivity type semiconductor substrate 1 is shown. It is clear that the present invention can also be applied to a semiconductor integrated circuit device configured with an ultra-fine channel insulated gate field effect transistor.

〔Effect of the invention〕

- According to the present invention, the potential on the surface of the semiconductor substrate in the vicinity of the element isolation region can be controlled as desired by the electrode embedded in the semiconductor substrate, resulting in a narrow channel effect in which the threshold voltage value rapidly decreases as the channel width decreases. tl to the channel width.
It is possible to construct a semiconductor integrated circuit device using ultra-fine insulated gate field effect transistors that do not depend on each other. The present invention relates to improvements in device isolation regions buried within a semiconductor substrate and is essentially independent of the narrow channel effect in which the threshold voltage value increases as the channel width decreases. Furthermore, since the present invention belongs to flat element isolation technology, there is no fear of disconnection of wiring or interference with fine processing.

[Brief explanation of drawings]

1 to 3 are cross-sectional views of a channel region in a direction perpendicular to the source/drain direction of a conventional insulated gate field effect transistor, and FIGS. 4 and 5 are cross-sectional views of the same as the above showing an embodiment of the present invention. 1 Figure Z Port 3 Figure d

Claims (1)

[Claims] 1. A region in a semiconductor substrate that insulates and separates insulated gate field effect transistors constituting a semiconductor integrated circuit device from each other is composed of an insulating film and a semiconductor or conductor isolated from the outside by the insulating film. In the semiconductor integrated circuit device, at least a portion of the semiconductor or conductor adjacent to the insulating isolation region has a low resistance, and a voltage that inhibits conduction of the insulated gate field effect transistor is applied to the semiconductor or conductor. A semiconductor integrated circuit device characterized in that a voltage is applied.